board/karo/tx53/tx53.c

   1 /*
   2  * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
   3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <common.h>
  21 #include <errno.h>
  22 #include <libfdt.h>
  23 #include <fdt_support.h>
  24 #include <lcd.h>
  25 #include <netdev.h>
  26 #include <mmc.h>
  27 #include <fsl_esdhc.h>
  28 #include <video_fb.h>
  29 #include <ipu.h>
  30 #include <mxcfb.h>
  31 #include <linux/fb.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <asm/arch/iomux-mx53.h>
  35 #include <asm/arch/clock.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include <asm/arch/sys_proto.h>
  39
  40 #include "../common/karo.h"
  41
  42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
  43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
  44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
  45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
  46
  47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
  48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
  49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
  50
  51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
  56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
  57
  58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
  59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
  60
  61 static iomux_v3_cfg_t tx53_pads[] = {
  62         /* NAND flash pads are set up in lowlevel_init.S */
  63
  64         /* UART pads */
  65 #if CONFIG_MXC_UART_BASE == UART1_BASE
  66         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  67         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  68         MX53_PAD_PATA_IORDY__UART1_RTS,
  69         MX53_PAD_PATA_RESET_B__UART1_CTS,
  70 #endif
  71 #if CONFIG_MXC_UART_BASE == UART2_BASE
  72         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
  73         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
  74         MX53_PAD_PATA_DIOR__UART2_RTS,
  75         MX53_PAD_PATA_INTRQ__UART2_CTS,
  76 #endif
  77 #if CONFIG_MXC_UART_BASE == UART3_BASE
  78         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
  79         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
  80         MX53_PAD_PATA_DA_2__UART3_RTS,
  81         MX53_PAD_PATA_DA_1__UART3_CTS,
  82 #endif
  83         /* internal I2C */
  84         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
  85         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
  86
  87         /* FEC PHY GPIO functions */
  88         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
  89         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
  90         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
  91
  92         /* FEC functions */
  93         MX53_PAD_FEC_MDC__FEC_MDC,
  94         MX53_PAD_FEC_MDIO__FEC_MDIO,
  95         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  96         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  97         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  98         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  99         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 100         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
 101         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
 102         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
 103 };
 104
 105 static const struct gpio tx53_gpios[] = {
 106         { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 107         { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 108         { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 109         { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 110 };
 111
 112 /*
 113  * Functions
 114  */
 115 /* placed in section '.data' to prevent overwriting relocation info
 116  * overlayed with bss
 117  */
 118 static u32 wrsr __attribute__((section(".data")));
 119
 120 #define WRSR_POR        (1 << 4)
 121 #define WRSR_TOUT       (1 << 1)
 122 #define WRSR_SFTW       (1 << 0)
 123
 124 static void print_reset_cause(void)
 125 {
 126         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 127         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 128         u32 srsr;
 129         char *dlm = "";
 130
 131         printf("Reset cause: ");
 132
 133         srsr = readl(&src_regs->srsr);
 134         wrsr = readw(wdt_base + 4);
 135
 136         if (wrsr & WRSR_POR) {
 137                 printf("%sPOR", dlm);
 138                 dlm = " | ";
 139         }
 140         if (srsr & 0x00004) {
 141                 printf("%sCSU", dlm);
 142                 dlm = " | ";
 143         }
 144         if (srsr & 0x00008) {
 145                 printf("%sIPP USER", dlm);
 146                 dlm = " | ";
 147         }
 148         if (srsr & 0x00010) {
 149                 if (wrsr & WRSR_SFTW) {
 150                         printf("%sSOFT", dlm);
 151                         dlm = " | ";
 152                 }
 153                 if (wrsr & WRSR_TOUT) {
 154                         printf("%sWDOG", dlm);
 155                         dlm = " | ";
 156                 }
 157         }
 158         if (srsr & 0x00020) {
 159                 printf("%sJTAG HIGH-Z", dlm);
 160                 dlm = " | ";
 161         }
 162         if (srsr & 0x00040) {
 163                 printf("%sJTAG SW", dlm);
 164                 dlm = " | ";
 165         }
 166         if (srsr & 0x10000) {
 167                 printf("%sWARM BOOT", dlm);
 168                 dlm = " | ";
 169         }
 170         if (dlm[0] == '\0')
 171                 printf("unknown");
 172
 173         printf("\n");
 174 }
 175
 176 static void tx53_print_cpuinfo(void)
 177 {
 178         u32 cpurev;
 179
 180         cpurev = get_cpu_rev();
 181
 182         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
 183                 (cpurev & 0x000F0) >> 4,
 184                 (cpurev & 0x0000F) >> 0,
 185                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 186
 187         print_reset_cause();
 188 }
 189
 190 int board_early_init_f(void)
 191 {
 192         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
 193
 194         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
 195         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
 196
 197         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
 198         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
 199
 200         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
 201         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
 202         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
 203         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
 204         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
 205
 206         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
 207         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
 208
 209         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
 210         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
 211         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
 212         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
 213         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
 214
 215         writel(0xffcf0fff, &ccm_regs->CCGR0);
 216         writel(0x000fffc3, &ccm_regs->CCGR1);
 217         writel(0x033c0000, &ccm_regs->CCGR2);
 218         writel(0x000000ff, &ccm_regs->CCGR3);
 219         writel(0x00000000, &ccm_regs->CCGR4);
 220         writel(0x00fff033, &ccm_regs->CCGR5);
 221         writel(0x0f00030f, &ccm_regs->CCGR6);
 222         writel(0xfff00000, &ccm_regs->CCGR7);
 223         writel(0x00000000, &ccm_regs->cmeor);
 224
 225         return 0;
 226 }
 227
 228 int board_init(void)
 229 {
 230         /* Address of boot parameters */
 231         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 232         return 0;
 233 }
 234
 235 int dram_init(void)
 236 {
 237         int ret;
 238
 239         /* dram_init must store complete ramsize in gd->ram_size */
 240         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 241                                 PHYS_SDRAM_1_SIZE);
 242
 243         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
 244                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
 245         if (ret)
 246                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
 247                         CONFIG_SYS_SDRAM_CLK, ret);
 248         else
 249                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
 250                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
 251                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
 252                         CONFIG_SYS_SDRAM_CLK);
 253         return ret;
 254 }
 255
 256 void dram_init_banksize(void)
 257 {
 258         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 259         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 260                         PHYS_SDRAM_1_SIZE);
 261 #if CONFIG_NR_DRAM_BANKS > 1
 262         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 263         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 264                         PHYS_SDRAM_2_SIZE);
 265 #endif
 266 }
 267
 268 #ifdef  CONFIG_CMD_MMC
 269 static const iomux_v3_cfg_t mmc0_pads[] = {
 270         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
 271         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
 272         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
 273         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
 274         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
 275         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
 276         /* SD1 CD */
 277         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
 278 };
 279
 280 static const iomux_v3_cfg_t mmc1_pads[] = {
 281         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
 282         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
 283         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
 284         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
 285         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
 286         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
 287         /* SD2 CD */
 288         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
 289 };
 290
 291 static struct tx53_esdhc_cfg {
 292         const iomux_v3_cfg_t *pads;
 293         int num_pads;
 294         struct fsl_esdhc_cfg cfg;
 295         int cd_gpio;
 296 } tx53_esdhc_cfg[] = {
 297         {
 298                 .pads = mmc0_pads,
 299                 .num_pads = ARRAY_SIZE(mmc0_pads),
 300                 .cfg = {
 301                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
 302                         .max_bus_width = 4,
 303                 },
 304                 .cd_gpio = IMX_GPIO_NR(3, 24),
 305         },
 306         {
 307                 .pads = mmc1_pads,
 308                 .num_pads = ARRAY_SIZE(mmc1_pads),
 309                 .cfg = {
 310                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
 311                         .max_bus_width = 4,
 312                 },
 313                 .cd_gpio = IMX_GPIO_NR(3, 25),
 314         },
 315 };
 316
 317 #if 1
 318 #define to_tx53_esdhc_cfg(p) container_of(p, struct tx53_esdhc_cfg, cfg)
 319 #else
 320 static struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 321 {
 322         void *p = cfg;
 323
 324         return p - offsetof(struct tx53_esdhc_cfg, cfg);
 325 }
 326 #endif
 327
 328 int board_mmc_getcd(struct mmc *mmc)
 329 {
 330         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
 331
 332         if (cfg->cd_gpio < 0)
 333                 return cfg->cd_gpio;
 334
 335         debug("SD card %d is %spresent\n",
 336                 cfg - tx53_esdhc_cfg,
 337                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 338         return !gpio_get_value(cfg->cd_gpio);
 339 }
 340
 341 int board_mmc_init(bd_t *bis)
 342 {
 343         int i;
 344
 345         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
 346                 struct mmc *mmc;
 347                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
 348                 int ret;
 349
 350                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 351                         break;
 352
 353                 imx_iomux_v3_setup_multiple_pads(cfg->pads,
 354                                                 cfg->num_pads);
 355                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 356
 357                 fsl_esdhc_initialize(bis, &cfg->cfg);
 358
 359                 ret = gpio_request_one(cfg->cd_gpio,
 360                                 GPIOF_INPUT, "MMC CD");
 361                 if (ret) {
 362                         printf("Error %d requesting GPIO%d_%d\n",
 363                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 364                         continue;
 365                 }
 366
 367                 mmc = find_mmc_device(i);
 368                 if (mmc == NULL)
 369                         continue;
 370                 if (board_mmc_getcd(mmc) > 0)
 371                         mmc_init(mmc);
 372         }
 373         return 0;
 374 }
 375 #endif /* CONFIG_CMD_MMC */
 376
 377 #ifdef CONFIG_FEC_MXC
 378
 379 #ifndef ETH_ALEN
 380 #define ETH_ALEN 6
 381 #endif
 382
 383 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 384 {
 385         int i;
 386         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 387         struct fuse_bank *bank = &iim->bank[1];
 388         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
 389
 390         if (dev_id > 0)
 391                 return;
 392
 393         for (i = 0; i < ETH_ALEN; i++)
 394                 mac[i] = readl(&fuse->mac_addr[i]);
 395 }
 396
 397 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 398                         PAD_CTL_SRE_FAST)
 399 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 400 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 401
 402 int board_eth_init(bd_t *bis)
 403 {
 404         int ret;
 405         unsigned char mac[ETH_ALEN];
 406
 407         /* delay at least 21ms for the PHY internal POR signal to deassert */
 408         udelay(22000);
 409
 410         /* Deassert RESET to the external phy */
 411         gpio_set_value(TX53_FEC_RST_GPIO, 1);
 412
 413         ret = cpu_eth_init(bis);
 414         if (ret) {
 415                 printf("cpu_eth_init() failed: %d\n", ret);
 416                 return ret;
 417         }
 418
 419         imx_get_mac_from_fuse(0, mac);
 420         eth_setenv_enetaddr("ethaddr", mac);
 421         printf("MAC addr from fuse: %pM\n", mac);
 422
 423         return ret;
 424 }
 425 #endif /* CONFIG_FEC_MXC */
 426
 427 enum {
 428         LED_STATE_INIT = -1,
 429         LED_STATE_OFF,
 430         LED_STATE_ON,
 431 };
 432
 433 void show_activity(int arg)
 434 {
 435         static int led_state = LED_STATE_INIT;
 436         static ulong last;
 437
 438         if (led_state == LED_STATE_INIT) {
 439                 last = get_timer(0);
 440                 gpio_set_value(TX53_LED_GPIO, 1);
 441                 led_state = LED_STATE_ON;
 442         } else {
 443                 if (get_timer(last) > CONFIG_SYS_HZ) {
 444                         last = get_timer(0);
 445                         if (led_state == LED_STATE_ON) {
 446                                 gpio_set_value(TX53_LED_GPIO, 0);
 447                         } else {
 448                                 gpio_set_value(TX53_LED_GPIO, 1);
 449                         }
 450                         led_state = 1 - led_state;
 451                 }
 452         }
 453 }
 454
 455 static const iomux_v3_cfg_t stk5_pads[] = {
 456         /* SW controlled LED on STK5 baseboard */
 457         MX53_PAD_EIM_A18__GPIO2_20,
 458
 459         /* I2C bus on DIMM pins 40/41 */
 460         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
 461         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
 462
 463         /* TSC200x PEN IRQ */
 464         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
 465
 466         /* EDT-FT5x06 Polytouch panel */
 467         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
 468         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
 469         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
 470
 471         /* USBH1 */
 472         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
 473         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
 474         /* USBOTG */
 475         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
 476         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
 477
 478         /* DS1339 Interrupt */
 479         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
 480 };
 481
 482 static const struct gpio stk5_gpios[] = {
 483         { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 484
 485         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 486         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 487         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 488         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 489 };
 490
 491 #ifdef CONFIG_LCD
 492 static ushort tx53_cmap[256];
 493 vidinfo_t panel_info = {
 494         /* set to max. size supported by SoC */
 495         .vl_col = 1600,
 496         .vl_row = 1200,
 497
 498         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 499         .cmap = tx53_cmap,
 500 };
 501
 502 static struct fb_videomode tx53_fb_modes[] = {
 503         {
 504                 /* Standard VGA timing */
 505                 .name           = "VGA",
 506                 .refresh        = 60,
 507                 .xres           = 640,
 508                 .yres           = 480,
 509                 .pixclock       = KHZ2PICOS(25175),
 510                 .left_margin    = 48,
 511                 .hsync_len      = 96,
 512                 .right_margin   = 16,
 513                 .upper_margin   = 31,
 514                 .vsync_len      = 2,
 515                 .lower_margin   = 12,
 516                 .sync           = FB_SYNC_CLK_LAT_FALL,
 517         },
 518         {
 519                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 520                  * DE high active, 115.2 mm x 86.4 mm display area
 521                  * VGA compatible timing
 522                  */
 523                 .name           = "ETV570",
 524                 .refresh        = 60,
 525                 .xres           = 640,
 526                 .yres           = 480,
 527                 .pixclock       = KHZ2PICOS(25175),
 528                 .left_margin    = 114,
 529                 .hsync_len      = 30,
 530                 .right_margin   = 16,
 531                 .upper_margin   = 32,
 532                 .vsync_len      = 3,
 533                 .lower_margin   = 10,
 534                 .sync           = FB_SYNC_CLK_LAT_FALL,
 535         },
 536         {
 537                 /* Emerging ET0350G0DH6 320 x 240 display.
 538                  * 70.08 mm x 52.56 mm display area.
 539                  */
 540                 .name           = "ET0350",
 541                 .refresh        = 60,
 542                 .xres           = 320,
 543                 .yres           = 240,
 544                 .pixclock       = KHZ2PICOS(6500),
 545                 .left_margin    = 68 - 34,
 546                 .hsync_len      = 34,
 547                 .right_margin   = 20,
 548                 .upper_margin   = 18 - 3,
 549                 .vsync_len      = 3,
 550                 .lower_margin   = 4,
 551                 .sync           = FB_SYNC_CLK_LAT_FALL,
 552         },
 553         {
 554                 /* Emerging ET0430G0DH6 480 x 272 display.
 555                  * 95.04 mm x 53.856 mm display area.
 556                  */
 557                 .name           = "ET0430",
 558                 .refresh        = 60,
 559                 .xres           = 480,
 560                 .yres           = 272,
 561                 .pixclock       = KHZ2PICOS(9000),
 562                 .left_margin    = 2,
 563                 .hsync_len      = 41,
 564                 .right_margin   = 2,
 565                 .upper_margin   = 2,
 566                 .vsync_len      = 10,
 567                 .lower_margin   = 2,
 568                 .sync           = FB_SYNC_CLK_LAT_FALL,
 569         },
 570         {
 571                 /* Emerging ET0500G0DH6 800 x 480 display.
 572                  * 109.6 mm x 66.4 mm display area.
 573                  */
 574                 .name           = "ET0500",
 575                 .refresh        = 60,
 576                 .xres           = 800,
 577                 .yres           = 480,
 578                 .pixclock       = KHZ2PICOS(33260),
 579                 .left_margin    = 216 - 128,
 580                 .hsync_len      = 128,
 581                 .right_margin   = 1056 - 800 - 216,
 582                 .upper_margin   = 35 - 2,
 583                 .vsync_len      = 2,
 584                 .lower_margin   = 525 - 480 - 35,
 585                 .sync           = FB_SYNC_CLK_LAT_FALL,
 586         },
 587         {
 588                 /* Emerging ETQ570G0DH6 320 x 240 display.
 589                  * 115.2 mm x 86.4 mm display area.
 590                  */
 591                 .name           = "ETQ570",
 592                 .refresh        = 60,
 593                 .xres           = 320,
 594                 .yres           = 240,
 595                 .pixclock       = KHZ2PICOS(6400),
 596                 .left_margin    = 38,
 597                 .hsync_len      = 30,
 598                 .right_margin   = 30,
 599                 .upper_margin   = 16, /* 15 according to datasheet */
 600                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 601                 .lower_margin   = 4, /* 4.5 according to datasheet */
 602                 .sync           = FB_SYNC_CLK_LAT_FALL,
 603         },
 604         {
 605                 /* Emerging ET0700G0DH6 800 x 480 display.
 606                  * 152.4 mm x 91.44 mm display area.
 607                  */
 608                 .name           = "ET0700",
 609                 .refresh        = 60,
 610                 .xres           = 800,
 611                 .yres           = 480,
 612                 .pixclock       = KHZ2PICOS(33260),
 613                 .left_margin    = 216 - 128,
 614                 .hsync_len      = 128,
 615                 .right_margin   = 1056 - 800 - 216,
 616                 .upper_margin   = 35 - 2,
 617                 .vsync_len      = 2,
 618                 .lower_margin   = 525 - 480 - 35,
 619                 .sync           = FB_SYNC_CLK_LAT_FALL,
 620         },
 621         {
 622                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 623                 .refresh        = 60,
 624                 .left_margin    = 48,
 625                 .hsync_len      = 96,
 626                 .right_margin   = 16,
 627                 .upper_margin   = 31,
 628                 .vsync_len      = 2,
 629                 .lower_margin   = 12,
 630                 .sync           = FB_SYNC_CLK_LAT_FALL,
 631         },
 632 };
 633
 634 static int lcd_enabled = 1;
 635
 636 void lcd_enable(void)
 637 {
 638         /* HACK ALERT:
 639          * global variable from common/lcd.c
 640          * Set to 0 here to prevent messages from going to LCD
 641          * rather than serial console
 642          */
 643         lcd_is_enabled = 0;
 644
 645         karo_load_splashimage(1);
 646         if (lcd_enabled) {
 647                 debug("Switching LCD on\n");
 648                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
 649                 udelay(100);
 650                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
 651                 udelay(300000);
 652                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
 653         }
 654 }
 655
 656 void lcd_disable(void)
 657 {
 658         printf("Disabling LCD\n");
 659 }
 660
 661 void lcd_panel_disable(void)
 662 {
 663         if (lcd_enabled) {
 664                 debug("Switching LCD off\n");
 665                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1);
 666                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
 667                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
 668         }
 669 }
 670
 671 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 672         /* LCD RESET */
 673         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
 674         /* LCD POWER_ENABLE */
 675         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
 676         /* LCD Backlight (PWM) */
 677         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
 678
 679         /* Display */
 680         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
 681         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
 682         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
 683         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
 684         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
 685         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
 686         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
 687         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
 688         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
 689         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
 690         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
 691         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
 692         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
 693         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
 694         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
 695         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
 696         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
 697         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
 698         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
 699         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
 700         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
 701         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
 702         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
 703         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
 704         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
 705         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
 706         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
 707         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
 708
 709         /* LVDS option */
 710         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
 711         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
 712         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
 713         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
 714         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
 715         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
 716         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
 717         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
 718         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
 719         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
 720 };
 721
 722 static const struct gpio stk5_lcd_gpios[] = {
 723         { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 724         { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 725         { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 726 };
 727
 728 void lcd_ctrl_init(void *lcdbase)
 729 {
 730         int color_depth = 24;
 731         char *vm;
 732         unsigned long val;
 733         int refresh = 60;
 734         struct fb_videomode *p = &tx53_fb_modes[0];
 735         struct fb_videomode fb_mode;
 736         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 737         int pix_fmt = 0;
 738         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 739         unsigned long di_clk_rate = 65000000;
 740
 741         if (!lcd_enabled) {
 742                 debug("LCD disabled\n");
 743                 return;
 744         }
 745
 746         if (tstc() || (wrsr & WRSR_TOUT)) {
 747                 debug("Disabling LCD\n");
 748                 lcd_enabled = 0;
 749                 return;
 750         }
 751
 752         karo_fdt_move_fdt();
 753
 754         vm = getenv("video_mode");
 755         if (vm == NULL) {
 756                 debug("Disabling LCD\n");
 757                 lcd_enabled = 0;
 758                 return;
 759         }
 760         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 761                 p = &fb_mode;
 762                 debug("Using video mode from FDT\n");
 763                 vm += strlen(vm);
 764                 if (fb_mode.xres < panel_info.vl_col)
 765                         panel_info.vl_col = fb_mode.xres;
 766                 if (fb_mode.yres < panel_info.vl_row)
 767                         panel_info.vl_row = fb_mode.yres;
 768         }
 769         if (p->name != NULL)
 770                 debug("Trying compiled-in video modes\n");
 771         while (p->name != NULL) {
 772                 if (strcmp(p->name, vm) == 0) {
 773                         debug("Using video mode: '%s'\n", p->name);
 774                         vm += strlen(vm);
 775                         break;
 776                 }
 777                 p++;
 778         }
 779         if (*vm != '\0')
 780                 debug("Trying to decode video_mode: '%s'\n", vm);
 781         while (*vm != '\0') {
 782                 if (*vm >= '0' && *vm <= '9') {
 783                         char *end;
 784
 785                         val = simple_strtoul(vm, &end, 0);
 786                         if (end > vm) {
 787                                 if (!xres_set) {
 788                                         if (val > panel_info.vl_col)
 789                                                 val = panel_info.vl_col;
 790                                         p->xres = val;
 791                                         panel_info.vl_col = val;
 792                                         xres_set = 1;
 793                                 } else if (!yres_set) {
 794                                         if (val > panel_info.vl_row)
 795                                                 val = panel_info.vl_row;
 796                                         p->yres = val;
 797                                         panel_info.vl_row = val;
 798                                         yres_set = 1;
 799                                 } else if (!bpp_set) {
 800                                         switch (val) {
 801                                         case 32:
 802                                         case 24:
 803                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
 804                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 805                                                 /* fallthru */
 806                                         case 16:
 807                                         case 8:
 808                                                 color_depth = val;
 809                                                 break;
 810
 811                                         case 18:
 812                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 813                                                         color_depth = val;
 814                                                         break;
 815                                                 }
 816                                                 /* fallthru */
 817                                         default:
 818                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 819                                                         end - vm, vm, color_depth);
 820                                         }
 821                                         bpp_set = 1;
 822                                 } else if (!refresh_set) {
 823                                         refresh = val;
 824                                         refresh_set = 1;
 825                                 }
 826                         }
 827                         vm = end;
 828                 }
 829                 switch (*vm) {
 830                 case '@':
 831                         bpp_set = 1;
 832                         /* fallthru */
 833                 case '-':
 834                         yres_set = 1;
 835                         /* fallthru */
 836                 case 'x':
 837                         xres_set = 1;
 838                         /* fallthru */
 839                 case 'M':
 840                 case 'R':
 841                         vm++;
 842                         break;
 843
 844                 default:
 845                         if (!pix_fmt) {
 846                                 char *tmp;
 847
 848                                 if (strncmp(vm, "LVDS", 4) == 0) {
 849                                         pix_fmt = IPU_PIX_FMT_LVDS666;
 850                                         di_clk_parent = DI_PCLK_LDB;
 851                                 } else {
 852                                         pix_fmt = IPU_PIX_FMT_RGB24;
 853                                 }
 854                                 tmp = strchr(vm, ':');
 855                                 if (tmp)
 856                                         vm = tmp;
 857                         }
 858                         if (*vm != '\0')
 859                                 vm++;
 860                 }
 861         }
 862         if (p->xres == 0 || p->yres == 0) {
 863                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 864                 lcd_enabled = 0;
 865                 printf("Supported video modes are:");
 866                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
 867                         printf(" %s", p->name);
 868                 }
 869                 printf("\n");
 870                 return;
 871         }
 872
 873         p->pixclock = KHZ2PICOS(refresh *
 874                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 875                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
 876                 / 1000);
 877         debug("Pixel clock set to %lu.%03lu MHz\n",
 878                 PICOS2KHZ(p->pixclock) / 1000,
 879                 PICOS2KHZ(p->pixclock) % 1000);
 880
 881         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
 882         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
 883                                         ARRAY_SIZE(stk5_lcd_pads));
 884
 885         debug("Initializing FB driver\n");
 886         if (!pix_fmt)
 887                 pix_fmt = IPU_PIX_FMT_RGB24;
 888         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
 889                 writel(0x01, IOMUXC_BASE_ADDR + 8);
 890         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
 891                 writel(0x21, IOMUXC_BASE_ADDR + 8);
 892         }
 893         if (pix_fmt != IPU_PIX_FMT_RGB24) {
 894                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 895                 /* enable LDB & DI0 clock */
 896                 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
 897                         &ccm_regs->CCGR6);
 898         }
 899
 900         if (karo_load_splashimage(0) == 0) {
 901                 debug("Initializing LCD controller\n");
 902                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
 903         } else {
 904                 debug("Skipping initialization of LCD controller\n");
 905         }
 906 }
 907 #else
 908 #define lcd_enabled 0
 909 #endif /* CONFIG_LCD */
 910
 911 static void stk5_board_init(void)
 912 {
 913         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
 914         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
 915 }
 916
 917 static void stk5v3_board_init(void)
 918 {
 919         stk5_board_init();
 920 }
 921
 922 static void stk5v5_board_init(void)
 923 {
 924         stk5_board_init();
 925
 926         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
 927                         "Flexcan Transceiver");
 928         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
 929 }
 930
 931 static void tx53_set_cpu_clock(void)
 932 {
 933         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
 934         int ret;
 935
 936         if (tstc() || (wrsr & WRSR_TOUT))
 937                 return;
 938
 939         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
 940                 return;
 941
 942         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
 943         if (ret != 0) {
 944                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
 945                 return;
 946         }
 947         printf("CPU clock set to %u.%03u MHz\n",
 948                 mxc_get_clock(MXC_ARM_CLK) / 1000000,
 949                 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
 950 }
 951
 952 int board_late_init(void)
 953 {
 954         int ret = 0;
 955         const char *baseboard;
 956
 957         tx53_set_cpu_clock();
 958         karo_fdt_move_fdt();
 959
 960         baseboard = getenv("baseboard");
 961         if (!baseboard)
 962                 goto exit;
 963
 964         if (strncmp(baseboard, "stk5", 4) == 0) {
 965                 printf("Baseboard: %s\n", baseboard);
 966                 if ((strlen(baseboard) == 4) ||
 967                         strcmp(baseboard, "stk5-v3") == 0) {
 968                         stk5v3_board_init();
 969                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
 970                         stk5v5_board_init();
 971                 } else {
 972                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
 973                                 baseboard + 4);
 974                 }
 975         } else {
 976                 printf("WARNING: Unsupported baseboard: '%s'\n",
 977                         baseboard);
 978                 ret = -EINVAL;
 979         }
 980
 981 exit:
 982         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
 983         return ret;
 984 }
 985
 986 int checkboard(void)
 987 {
 988         tx53_print_cpuinfo();
 989
 990         printf("Board: Ka-Ro TX53-xx3%s\n",
 991                 TX53_MOD_SUFFIX);
 992
 993         return 0;
 994 }
 995
 996 #if defined(CONFIG_OF_BOARD_SETUP)
 997 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 998 #include <jffs2/jffs2.h>
 999 #include <mtd_node.h>
1000 struct node_info nodes[] = {
1001         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1002 };
1003
1004 #else
1005 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1006 #endif
1007
1008 static void tx53_fixup_flexcan(void *blob)
1009 {
1010         const char *baseboard = getenv("baseboard");
1011
1012         if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
1013                 return;
1014
1015         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch");
1016         karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch");
1017 }
1018
1019 #ifdef CONFIG_SYS_TX53_HWREV_2
1020 void tx53_fixup_rtc(void *blob)
1021 {
1022         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1023         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1024 }
1025 #else
1026 static inline void tx53_fixup_rtc(void *blob)
1027 {
1028 }
1029 #endif
1030
1031 void ft_board_setup(void *blob, bd_t *bd)
1032 {
1033         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1034         fdt_fixup_ethernet(blob);
1035
1036         karo_fdt_enable_node(blob, "ipu", getenv("video_mode") != NULL);
1037         karo_fdt_fixup_touchpanel(blob);
1038         karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1039         tx53_fixup_flexcan(blob);
1040         tx53_fixup_rtc(blob);
1041 }
1042 #endif