2 * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
21 #include <fdt_support.h>
25 #include <fsl_esdhc.h>
33 #include <asm/arch/mx6-pins.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
39 #include "../common/karo.h"
42 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
43 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
44 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
45 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
47 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
48 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
49 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
51 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
53 #define TEMPERATURE_MIN -40
54 #define TEMPERATURE_HOT 80
55 #define TEMPERATURE_MAX 125
57 DECLARE_GLOBAL_DATA_PTR;
59 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
61 static const iomux_v3_cfg_t tx6qdl_pads[] = {
63 MX6_PAD_GPIO_17__GPIO_7_12,
66 #if CONFIG_MXC_UART_BASE == UART1_BASE
67 MX6_PAD_SD3_DAT7__UART1_TXD,
68 MX6_PAD_SD3_DAT6__UART1_RXD,
69 MX6_PAD_SD3_DAT1__UART1_RTS,
70 MX6_PAD_SD3_DAT0__UART1_CTS,
72 #if CONFIG_MXC_UART_BASE == UART2_BASE
73 MX6_PAD_SD4_DAT4__UART2_RXD,
74 MX6_PAD_SD4_DAT7__UART2_TXD,
75 MX6_PAD_SD4_DAT5__UART2_RTS,
76 MX6_PAD_SD4_DAT6__UART2_CTS,
78 #if CONFIG_MXC_UART_BASE == UART3_BASE
79 MX6_PAD_EIM_D24__UART3_TXD,
80 MX6_PAD_EIM_D25__UART3_RXD,
81 MX6_PAD_SD3_RST__UART3_RTS,
82 MX6_PAD_SD3_DAT3__UART3_CTS,
85 MX6_PAD_EIM_D28__I2C1_SDA,
86 MX6_PAD_EIM_D21__I2C1_SCL,
88 /* FEC PHY GPIO functions */
89 MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
90 MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
91 MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
94 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
96 MX6_PAD_ENET_MDC__ENET_MDC,
97 MX6_PAD_ENET_MDIO__ENET_MDIO,
98 MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
99 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
100 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
101 MX6_PAD_ENET_RXD1__ENET_RDATA_1,
102 MX6_PAD_ENET_RXD0__ENET_RDATA_0,
103 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
104 MX6_PAD_ENET_TXD1__ENET_TDATA_1,
105 MX6_PAD_ENET_TXD0__ENET_TDATA_0,
108 static const struct gpio tx6qdl_gpios[] = {
109 { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
110 { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
111 { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
112 { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
118 /* placed in section '.data' to prevent overwriting relocation info
121 static u32 wrsr __attribute__((section(".data")));
123 #define WRSR_POR (1 << 4)
124 #define WRSR_TOUT (1 << 1)
125 #define WRSR_SFTW (1 << 0)
127 static void print_reset_cause(void)
129 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
130 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
134 printf("Reset cause: ");
136 srsr = readl(&src_regs->srsr);
137 wrsr = readw(wdt_base + 4);
139 if (wrsr & WRSR_POR) {
140 printf("%sPOR", dlm);
143 if (srsr & 0x00004) {
144 printf("%sCSU", dlm);
147 if (srsr & 0x00008) {
148 printf("%sIPP USER", dlm);
151 if (srsr & 0x00010) {
152 if (wrsr & WRSR_SFTW) {
153 printf("%sSOFT", dlm);
156 if (wrsr & WRSR_TOUT) {
157 printf("%sWDOG", dlm);
161 if (srsr & 0x00020) {
162 printf("%sJTAG HIGH-Z", dlm);
165 if (srsr & 0x00040) {
166 printf("%sJTAG SW", dlm);
169 if (srsr & 0x10000) {
170 printf("%sWARM BOOT", dlm);
179 int read_cpu_temperature(void);
180 int check_cpu_temperature(int boot);
182 static void tx6qdl_print_cpuinfo(void)
184 u32 cpurev = get_cpu_rev();
187 switch ((cpurev >> 12) & 0xff) {
194 case MXC_CPU_MX6SOLO:
202 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
204 (cpurev & 0x000F0) >> 4,
205 (cpurev & 0x0000F) >> 0,
206 mxc_get_clock(MXC_ARM_CLK) / 1000000);
209 check_cpu_temperature(1);
212 int board_early_init_f(void)
214 gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
215 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
224 /* Address of boot parameters */
225 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
226 gd->bd->bi_arch_number = -1;
229 printf("CTRL-C detected; Skipping PMIC setup\n");
233 ret = setup_pmic_voltages();
235 printf("Failed to setup PMIC voltages\n");
243 /* dram_init must store complete ramsize in gd->ram_size */
244 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
249 void dram_init_banksize(void)
251 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
252 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
254 #if CONFIG_NR_DRAM_BANKS > 1
255 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
256 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
261 #ifdef CONFIG_CMD_MMC
262 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
263 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
264 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
266 static const iomux_v3_cfg_t mmc0_pads[] = {
267 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
268 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
269 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
270 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
271 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
272 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
274 MX6_PAD_SD3_CMD__GPIO_7_2,
277 static const iomux_v3_cfg_t mmc1_pads[] = {
278 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
279 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
280 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
281 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
282 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
283 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
285 MX6_PAD_SD3_CLK__GPIO_7_3,
288 static const iomux_v3_cfg_t mmc3_pads[] = {
289 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
290 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
291 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
292 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
293 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
294 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
296 MX6_PAD_NANDF_ALE__USDHC4_RST,
299 static struct tx6_esdhc_cfg {
300 const iomux_v3_cfg_t *pads;
302 enum mxc_clock clkid;
303 struct fsl_esdhc_cfg cfg;
305 } tx6qdl_esdhc_cfg[] = {
308 .num_pads = ARRAY_SIZE(mmc3_pads),
309 .clkid = MXC_ESDHC4_CLK,
311 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
318 .num_pads = ARRAY_SIZE(mmc0_pads),
319 .clkid = MXC_ESDHC_CLK,
321 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
324 .cd_gpio = IMX_GPIO_NR(7, 2),
328 .num_pads = ARRAY_SIZE(mmc1_pads),
329 .clkid = MXC_ESDHC2_CLK,
331 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
334 .cd_gpio = IMX_GPIO_NR(7, 3),
338 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
340 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
343 int board_mmc_getcd(struct mmc *mmc)
345 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
347 if (cfg->cd_gpio < 0)
350 debug("SD card %d is %spresent\n",
351 cfg - tx6qdl_esdhc_cfg,
352 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
353 return !gpio_get_value(cfg->cd_gpio);
356 int board_mmc_init(bd_t *bis)
360 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
362 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
365 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
366 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
368 if (cfg->cd_gpio >= 0) {
369 ret = gpio_request_one(cfg->cd_gpio,
370 GPIOF_INPUT, "MMC CD");
372 printf("Error %d requesting GPIO%d_%d\n",
373 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
378 debug("%s: Initializing MMC slot %d\n", __func__, i);
379 fsl_esdhc_initialize(bis, &cfg->cfg);
381 mmc = find_mmc_device(i);
384 if (board_mmc_getcd(mmc))
389 #endif /* CONFIG_CMD_MMC */
391 #ifdef CONFIG_FEC_MXC
393 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
395 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
396 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
402 int board_eth_init(bd_t *bis)
406 /* delay at least 21ms for the PHY internal POR signal to deassert */
409 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
411 /* Deassert RESET to the external phy */
412 gpio_set_value(TX6_FEC_RST_GPIO, 1);
414 ret = cpu_eth_init(bis);
416 printf("cpu_eth_init() failed: %d\n", ret);
420 #endif /* CONFIG_FEC_MXC */
428 static inline int calc_blink_rate(int tmp)
430 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
431 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
432 (TEMPERATURE_HOT - TEMPERATURE_MIN);
435 void show_activity(int arg)
437 static int led_state = LED_STATE_INIT;
438 static int blink_rate;
441 if (led_state == LED_STATE_INIT) {
443 gpio_set_value(TX6_LED_GPIO, 1);
444 led_state = LED_STATE_ON;
445 blink_rate = calc_blink_rate(check_cpu_temperature(0));
447 if (get_timer(last) > blink_rate) {
448 blink_rate = calc_blink_rate(check_cpu_temperature(0));
449 last = get_timer_masked();
450 if (led_state == LED_STATE_ON) {
451 gpio_set_value(TX6_LED_GPIO, 0);
453 gpio_set_value(TX6_LED_GPIO, 1);
455 led_state = 1 - led_state;
460 static const iomux_v3_cfg_t stk5_pads[] = {
461 /* SW controlled LED on STK5 baseboard */
462 MX6_PAD_EIM_A18__GPIO_2_20,
465 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
466 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
467 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
468 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
469 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
470 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
471 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
472 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
473 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
474 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
475 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
476 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
477 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
478 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
479 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
480 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
481 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
482 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
483 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
484 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
485 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
486 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
487 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
488 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
489 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
490 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
491 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
492 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
494 /* I2C bus on DIMM pins 40/41 */
495 MX6_PAD_GPIO_6__I2C3_SDA,
496 MX6_PAD_GPIO_3__I2C3_SCL,
498 /* TSC200x PEN IRQ */
499 MX6_PAD_EIM_D26__GPIO_3_26,
501 /* EDT-FT5x06 Polytouch panel */
502 MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
503 MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
504 MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
507 MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
508 MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
510 MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
511 MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
512 MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
515 static const struct gpio stk5_gpios[] = {
516 { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
518 { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
519 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
520 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
521 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
522 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
526 static u16 tx6_cmap[256];
527 vidinfo_t panel_info = {
528 /* set to max. size supported by SoC */
532 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
536 static struct fb_videomode tx6_fb_modes[] = {
537 #ifndef CONFIG_SYS_LVDS_IF
539 /* Standard VGA timing */
544 .pixclock = KHZ2PICOS(25175),
551 .sync = FB_SYNC_CLK_LAT_FALL,
554 /* Emerging ETV570 640 x 480 display. Syncs low active,
555 * DE high active, 115.2 mm x 86.4 mm display area
556 * VGA compatible timing
562 .pixclock = KHZ2PICOS(25175),
569 .sync = FB_SYNC_CLK_LAT_FALL,
572 /* Emerging ET0350G0DH6 320 x 240 display.
573 * 70.08 mm x 52.56 mm display area.
579 .pixclock = KHZ2PICOS(6500),
580 .left_margin = 68 - 34,
583 .upper_margin = 18 - 3,
586 .sync = FB_SYNC_CLK_LAT_FALL,
589 /* Emerging ET0430G0DH6 480 x 272 display.
590 * 95.04 mm x 53.856 mm display area.
596 .pixclock = KHZ2PICOS(9000),
603 .sync = FB_SYNC_CLK_LAT_FALL,
606 /* Emerging ET0500G0DH6 800 x 480 display.
607 * 109.6 mm x 66.4 mm display area.
613 .pixclock = KHZ2PICOS(33260),
614 .left_margin = 216 - 128,
616 .right_margin = 1056 - 800 - 216,
617 .upper_margin = 35 - 2,
619 .lower_margin = 525 - 480 - 35,
620 .sync = FB_SYNC_CLK_LAT_FALL,
623 /* Emerging ETQ570G0DH6 320 x 240 display.
624 * 115.2 mm x 86.4 mm display area.
630 .pixclock = KHZ2PICOS(6400),
634 .upper_margin = 16, /* 15 according to datasheet */
635 .vsync_len = 3, /* TVP -> 1>x>5 */
636 .lower_margin = 4, /* 4.5 according to datasheet */
637 .sync = FB_SYNC_CLK_LAT_FALL,
640 /* Emerging ET0700G0DH6 800 x 480 display.
641 * 152.4 mm x 91.44 mm display area.
647 .pixclock = KHZ2PICOS(33260),
648 .left_margin = 216 - 128,
650 .right_margin = 1056 - 800 - 216,
651 .upper_margin = 35 - 2,
653 .lower_margin = 525 - 480 - 35,
654 .sync = FB_SYNC_CLK_LAT_FALL,
657 /* Emerging ET070001DM6 800 x 480 display.
658 * 152.4 mm x 91.44 mm display area.
660 .name = "ET070001DM6",
664 .pixclock = KHZ2PICOS(33260),
665 .left_margin = 216 - 128,
667 .right_margin = 1056 - 800 - 216,
668 .upper_margin = 35 - 2,
670 .lower_margin = 525 - 480 - 35,
675 /* HannStar HSD100PXN1
676 * 202.7m mm x 152.06 mm display area.
678 .name = "HSD100PXN1",
682 .pixclock = KHZ2PICOS(65000),
689 .sync = FB_SYNC_CLK_LAT_FALL,
693 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
701 .sync = FB_SYNC_CLK_LAT_FALL,
705 static int lcd_enabled = 1;
706 static int lcd_bl_polarity;
708 static int lcd_backlight_polarity(void)
710 return lcd_bl_polarity;
713 void lcd_enable(void)
716 * global variable from common/lcd.c
717 * Set to 0 here to prevent messages from going to LCD
718 * rather than serial console
723 karo_load_splashimage(1);
725 debug("Switching LCD on\n");
726 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
728 gpio_set_value(TX6_LCD_RST_GPIO, 1);
730 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, lcd_backlight_polarity());
734 void lcd_disable(void)
737 printf("Disabling LCD\n");
742 void lcd_panel_disable(void)
745 debug("Switching LCD off\n");
746 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, !lcd_backlight_polarity());
747 gpio_set_value(TX6_LCD_RST_GPIO, 0);
748 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
752 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
754 MX6_PAD_EIM_D29__GPIO_3_29,
755 /* LCD POWER_ENABLE */
756 MX6_PAD_EIM_EB3__GPIO_2_31,
757 /* LCD Backlight (PWM) */
758 MX6_PAD_GPIO_1__GPIO_1_1,
761 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
762 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
763 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
764 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
765 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
766 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
767 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
768 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
769 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
770 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
771 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
772 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
773 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
774 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
775 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
776 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
777 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
778 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
779 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
780 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
781 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
782 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
783 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
784 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
785 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
786 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
787 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
788 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
791 static const struct gpio stk5_lcd_gpios[] = {
792 { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
793 { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
794 { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
797 void lcd_ctrl_init(void *lcdbase)
799 int color_depth = 24;
800 const char *video_mode = karo_get_vmode(getenv("video_mode"));
804 struct fb_videomode *p = &tx6_fb_modes[0];
805 struct fb_videomode fb_mode;
806 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
809 unsigned long di_clk_rate = 65000000;
812 debug("LCD disabled\n");
816 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
817 debug("Disabling LCD\n");
819 setenv("splashimage", NULL);
824 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
826 if (video_mode == NULL) {
827 debug("Disabling LCD\n");
832 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
834 debug("Using video mode from FDT\n");
836 if (fb_mode.xres > panel_info.vl_col ||
837 fb_mode.yres > panel_info.vl_row) {
838 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
839 fb_mode.xres, fb_mode.yres,
840 panel_info.vl_col, panel_info.vl_row);
846 debug("Trying compiled-in video modes\n");
847 while (p->name != NULL) {
848 if (strcmp(p->name, vm) == 0) {
849 debug("Using video mode: '%s'\n", p->name);
856 debug("Trying to decode video_mode: '%s'\n", vm);
857 while (*vm != '\0') {
858 if (*vm >= '0' && *vm <= '9') {
861 val = simple_strtoul(vm, &end, 0);
864 if (val > panel_info.vl_col)
865 val = panel_info.vl_col;
867 panel_info.vl_col = val;
869 } else if (!yres_set) {
870 if (val > panel_info.vl_row)
871 val = panel_info.vl_row;
873 panel_info.vl_row = val;
875 } else if (!bpp_set) {
880 pix_fmt = IPU_PIX_FMT_LVDS888;
894 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
895 end - vm, vm, color_depth);
898 } else if (!refresh_set) {
925 if (p->xres == 0 || p->yres == 0) {
926 printf("Invalid video mode: %s\n", getenv("video_mode"));
928 printf("Supported video modes are:");
929 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
930 printf(" %s", p->name);
935 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
936 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
937 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
941 panel_info.vl_col = p->xres;
942 panel_info.vl_row = p->yres;
944 switch (color_depth) {
946 panel_info.vl_bpix = LCD_COLOR8;
949 panel_info.vl_bpix = LCD_COLOR16;
952 panel_info.vl_bpix = LCD_COLOR24;
955 p->pixclock = KHZ2PICOS(refresh *
956 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
957 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
959 debug("Pixel clock set to %lu.%03lu MHz\n",
960 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
965 debug("Creating new display-timing node from '%s'\n",
967 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
969 printf("Failed to create new display-timing node from '%s': %d\n",
973 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
974 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
975 ARRAY_SIZE(stk5_lcd_pads));
977 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
978 switch (lcd_bus_width) {
980 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
984 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
989 pix_fmt = IPU_PIX_FMT_RGB565;
995 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1000 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1001 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1004 if (lvds_chan_mask == 0) {
1005 printf("No LVDS channel active\n");
1010 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1011 if (lcd_bus_width == 24)
1012 gpr2 |= (1 << 5) | (1 << 7);
1013 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1014 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1015 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1016 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1018 if (karo_load_splashimage(0) == 0) {
1021 debug("Initializing LCD controller\n");
1022 ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
1024 printf("Failed to initialize FB driver: %d\n", ret);
1028 debug("Skipping initialization of LCD controller\n");
1032 #define lcd_enabled 0
1033 #endif /* CONFIG_LCD */
1035 static void stk5_board_init(void)
1037 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1038 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1041 static void stk5v3_board_init(void)
1046 static void stk5v5_board_init(void)
1050 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1051 "Flexcan Transceiver");
1052 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1055 static void tx6qdl_set_cpu_clock(void)
1057 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1059 if (had_ctrlc() || (wrsr & WRSR_TOUT))
1062 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1065 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1066 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1067 printf("CPU clock set to %lu.%03lu MHz\n",
1068 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1070 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1074 static void tx6_init_mac(void)
1078 imx_get_mac_from_fuse(-1, mac);
1079 if (!is_valid_ether_addr(mac)) {
1080 printf("No valid MAC address programmed\n");
1084 printf("MAC addr from fuse: %pM\n", mac);
1085 eth_setenv_enetaddr("ethaddr", mac);
1088 int board_late_init(void)
1091 const char *baseboard;
1093 tx6qdl_set_cpu_clock();
1094 karo_fdt_move_fdt();
1096 baseboard = getenv("baseboard");
1100 printf("Baseboard: %s\n", baseboard);
1102 if (strncmp(baseboard, "stk5", 4) == 0) {
1103 if ((strlen(baseboard) == 4) ||
1104 strcmp(baseboard, "stk5-v3") == 0) {
1105 stk5v3_board_init();
1106 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1107 const char *otg_mode = getenv("otg_mode");
1109 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1110 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1111 otg_mode, baseboard);
1112 setenv("otg_mode", "none");
1114 stk5v5_board_init();
1116 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1120 printf("WARNING: Unsupported baseboard: '%s'\n",
1128 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1133 int checkboard(void)
1135 u32 cpurev = get_cpu_rev();
1136 int cpu_variant = (cpurev >> 12) & 0xff;
1138 tx6qdl_print_cpuinfo();
1140 printf("Board: Ka-Ro TX6%c-%d%d2%d\n",
1141 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1142 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1143 is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64);
1148 #ifdef CONFIG_SERIAL_TAG
1149 void get_board_serial(struct tag_serialnr *serialnr)
1151 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1152 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1154 serialnr->low = readl(&fuse->cfg0);
1155 serialnr->high = readl(&fuse->cfg1);
1159 #ifdef CONFIG_OF_BOARD_SETUP
1160 static const char *tx6_touchpanels[] = {
1166 void ft_board_setup(void *blob, bd_t *bd)
1168 const char *baseboard = getenv("baseboard");
1169 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1170 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1173 ret = fdt_increase_size(blob, 4096);
1175 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1178 karo_fdt_enable_node(blob, "stk5led", 0);
1180 fdt_fixup_ethernet(blob);
1182 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1183 ARRAY_SIZE(tx6_touchpanels));
1184 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1185 karo_fdt_fixup_flexcan(blob, stk5_v5);
1187 karo_fdt_update_fb_mode(blob, video_mode);
1189 #endif /* CONFIG_OF_BOARD_SETUP */