board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17 #include <common.h>
  18 #include <errno.h>
  19 #include <libfdt.h>
  20 #include <fdt_support.h>
  21 #include <lcd.h>
  22 #include <netdev.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <video_fb.h>
  26 #include <ipu.h>
  27 #include <mxcfb.h>
  28 #include <i2c.h>
  29 #include <linux/fb.h>
  30 #include <asm/io.h>
  31 #include <asm/gpio.h>
  32 #include <asm/arch/mx6-pins.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/imx-regs.h>
  35 #include <asm/arch/crm_regs.h>
  36 #include <asm/arch/sys_proto.h>
  37
  38 #include "../common/karo.h"
  39 #include "pmic.h"
  40
  41 #define __data __attribute__((section(".data")))
  42
  43 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  44 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  45 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  46 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  47
  48 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  49 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  50 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  51
  52 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 enum {
  70         MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
  71 };
  72
  73 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  74         MX6_PAD_GARBAGE,
  75 #ifdef CONFIG_TX6_NAND_
  76         /* NAND flash pads */
  77         MX6_PAD_NANDF_CLE__NAND_CLE,
  78         MX6_PAD_NANDF_ALE__NAND_ALE,
  79         MX6_PAD_NANDF_WP_B__NAND_RESETN,
  80         MX6_PAD_NANDF_RB0__NAND_READY0,
  81         MX6_PAD_NANDF_CS0__NAND_CE0N,
  82         MX6_PAD_SD4_CMD__NAND_RDN,
  83         MX6_PAD_SD4_CLK__NAND_WRN,
  84         MX6_PAD_NANDF_D0__NAND_D0,
  85         MX6_PAD_NANDF_D1__NAND_D1,
  86         MX6_PAD_NANDF_D2__NAND_D2,
  87         MX6_PAD_NANDF_D3__NAND_D3,
  88         MX6_PAD_NANDF_D4__NAND_D4,
  89         MX6_PAD_NANDF_D5__NAND_D5,
  90         MX6_PAD_NANDF_D6__NAND_D6,
  91         MX6_PAD_NANDF_D7__NAND_D7,
  92 #endif
  93         /* RESET_OUT */
  94         MX6_PAD_GPIO_17__GPIO7_IO12,
  95
  96         /* UART pads */
  97 #if CONFIG_MXC_UART_BASE == UART1_BASE
  98         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
  99         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
 100         MX6_PAD_SD3_DAT1__UART1_RTS_B,
 101         MX6_PAD_SD3_DAT0__UART1_CTS_B,
 102 #endif
 103 #if CONFIG_MXC_UART_BASE == UART2_BASE
 104         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
 105         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
 106         MX6_PAD_SD4_DAT5__UART2_RTS_B,
 107         MX6_PAD_SD4_DAT6__UART2_CTS_B,
 108 #endif
 109 #if CONFIG_MXC_UART_BASE == UART3_BASE
 110         MX6_PAD_EIM_D24__UART3_TX_DATA,
 111         MX6_PAD_EIM_D25__UART3_RX_DATA,
 112         MX6_PAD_SD3_RST__UART3_RTS_B,
 113         MX6_PAD_SD3_DAT3__UART3_CTS_B,
 114 #endif
 115         /* internal I2C */
 116         MX6_PAD_EIM_D28__I2C1_SDA,
 117         MX6_PAD_EIM_D21__I2C1_SCL,
 118
 119         /* FEC PHY GPIO functions */
 120         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
 121         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
 122         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
 123 };
 124
 125 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 126         /* FEC functions */
 127         MX6_PAD_ENET_MDC__ENET_MDC,
 128         MX6_PAD_ENET_MDIO__ENET_MDIO,
 129         MX6_PAD_GPIO_16__ENET_REF_CLK,
 130         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 131         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 132         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
 133         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
 134         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 135         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
 136         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 137 };
 138
 139 static const struct gpio const tx6qdl_gpios[] = {
 140         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 141         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 142         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 143         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 144 };
 145
 146 /*
 147  * Functions
 148  */
 149 /* placed in section '.data' to prevent overwriting relocation info
 150  * overlayed with bss
 151  */
 152 static u32 wrsr __attribute__((section(".data")));
 153
 154 #define WRSR_POR                        (1 << 4)
 155 #define WRSR_TOUT                       (1 << 1)
 156 #define WRSR_SFTW                       (1 << 0)
 157
 158 static void print_reset_cause(void)
 159 {
 160         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 161         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 162         u32 srsr;
 163         char *dlm = "";
 164
 165         printf("Reset cause: ");
 166
 167         srsr = readl(&src_regs->srsr);
 168         wrsr = readw(wdt_base + 4);
 169
 170         if (wrsr & WRSR_POR) {
 171                 printf("%sPOR", dlm);
 172                 dlm = " | ";
 173         }
 174         if (srsr & 0x00004) {
 175                 printf("%sCSU", dlm);
 176                 dlm = " | ";
 177         }
 178         if (srsr & 0x00008) {
 179                 printf("%sIPP USER", dlm);
 180                 dlm = " | ";
 181         }
 182         if (srsr & 0x00010) {
 183                 if (wrsr & WRSR_SFTW) {
 184                         printf("%sSOFT", dlm);
 185                         dlm = " | ";
 186                 }
 187                 if (wrsr & WRSR_TOUT) {
 188                         printf("%sWDOG", dlm);
 189                         dlm = " | ";
 190                 }
 191         }
 192         if (srsr & 0x00020) {
 193                 printf("%sJTAG HIGH-Z", dlm);
 194                 dlm = " | ";
 195         }
 196         if (srsr & 0x00040) {
 197                 printf("%sJTAG SW", dlm);
 198                 dlm = " | ";
 199         }
 200         if (srsr & 0x10000) {
 201                 printf("%sWARM BOOT", dlm);
 202                 dlm = " | ";
 203         }
 204         if (dlm[0] == '\0')
 205                 printf("unknown");
 206
 207         printf("\n");
 208 }
 209
 210 static const char __data *tx6_mod_suffix;
 211
 212 static void tx6qdl_print_cpuinfo(void)
 213 {
 214         u32 cpurev = get_cpu_rev();
 215         char *cpu_str = "?";
 216
 217         switch ((cpurev >> 12) & 0xff) {
 218         case MXC_CPU_MX6SL:
 219                 cpu_str = "SL";
 220                 tx6_mod_suffix = "?";
 221                 break;
 222         case MXC_CPU_MX6DL:
 223                 cpu_str = "DL";
 224                 tx6_mod_suffix = "U";
 225                 break;
 226         case MXC_CPU_MX6SOLO:
 227                 cpu_str = "SOLO";
 228                 tx6_mod_suffix = "S";
 229                 break;
 230         case MXC_CPU_MX6Q:
 231                 cpu_str = "Q";
 232                 tx6_mod_suffix = "Q";
 233                 break;
 234         }
 235
 236         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 237                 cpu_str,
 238                 (cpurev & 0x000F0) >> 4,
 239                 (cpurev & 0x0000F) >> 0,
 240                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 241
 242         print_reset_cause();
 243 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 244         check_cpu_temperature(1);
 245 #endif
 246 }
 247
 248 int board_early_init_f(void)
 249 {
 250         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 251         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 252
 253         return 0;
 254 }
 255
 256 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 257 static bool tx6_temp_check_enabled = true;
 258 #else
 259 #define tx6_temp_check_enabled  0
 260 #endif
 261
 262 int board_init(void)
 263 {
 264         int ret;
 265
 266         /* Address of boot parameters */
 267         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 268         gd->bd->bi_arch_number = -1;
 269
 270         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 271                 if (wrsr & WRSR_TOUT)
 272                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 273                 else
 274                         printf("<CTRL-C> detected; safeboot enabled\n");
 275 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 276                 tx6_temp_check_enabled = false;
 277 #endif
 278                 return 1;
 279         }
 280
 281         ret = tx6_pmic_init();
 282         if (ret) {
 283                 printf("Failed to setup PMIC voltages\n");
 284                 hang();
 285         }
 286         return 0;
 287 }
 288
 289 int dram_init(void)
 290 {
 291         /* dram_init must store complete ramsize in gd->ram_size */
 292         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 293                                 PHYS_SDRAM_1_SIZE);
 294         return 0;
 295 }
 296
 297 void dram_init_banksize(void)
 298 {
 299         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 300         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 301                         PHYS_SDRAM_1_SIZE);
 302 #if CONFIG_NR_DRAM_BANKS > 1
 303         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 304         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 305                         PHYS_SDRAM_2_SIZE);
 306 #endif
 307 }
 308
 309 #ifdef  CONFIG_CMD_MMC
 310 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |                       \
 311         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
 312         PAD_CTL_SRE_FAST)
 313
 314 static const iomux_v3_cfg_t mmc0_pads[] = {
 315         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 316         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 317         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 318         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 319         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 320         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 321         /* SD1 CD */
 322         MX6_PAD_SD3_CMD__GPIO7_IO02,
 323 };
 324
 325 static const iomux_v3_cfg_t mmc1_pads[] = {
 326         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 327         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 328         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 329         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 330         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 331         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 332         /* SD2 CD */
 333         MX6_PAD_SD3_CLK__GPIO7_IO03,
 334 };
 335
 336 #ifdef CONFIG_TX6_EMMC
 337 static const iomux_v3_cfg_t mmc3_pads[] = {
 338         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 339         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 340         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 341         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 342         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 343         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 344         /* eMMC RESET */
 345         MX6_PAD_NANDF_ALE__SD4_RESET,
 346 };
 347 #endif
 348
 349 static struct tx6_esdhc_cfg {
 350         const iomux_v3_cfg_t *pads;
 351         int num_pads;
 352         enum mxc_clock clkid;
 353         struct fsl_esdhc_cfg cfg;
 354         int cd_gpio;
 355 } tx6qdl_esdhc_cfg[] = {
 356 #ifdef CONFIG_TX6_EMMC
 357         {
 358                 .pads = mmc3_pads,
 359                 .num_pads = ARRAY_SIZE(mmc3_pads),
 360                 .clkid = MXC_ESDHC4_CLK,
 361                 .cfg = {
 362                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 363                         .max_bus_width = 4,
 364                 },
 365                 .cd_gpio = -EINVAL,
 366         },
 367 #endif
 368         {
 369                 .pads = mmc0_pads,
 370                 .num_pads = ARRAY_SIZE(mmc0_pads),
 371                 .clkid = MXC_ESDHC_CLK,
 372                 .cfg = {
 373                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 374                         .max_bus_width = 4,
 375                 },
 376                 .cd_gpio = IMX_GPIO_NR(7, 2),
 377         },
 378         {
 379                 .pads = mmc1_pads,
 380                 .num_pads = ARRAY_SIZE(mmc1_pads),
 381                 .clkid = MXC_ESDHC2_CLK,
 382                 .cfg = {
 383                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 384                         .max_bus_width = 4,
 385                 },
 386                 .cd_gpio = IMX_GPIO_NR(7, 3),
 387         },
 388 };
 389
 390 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 391 {
 392         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 393 }
 394
 395 int board_mmc_getcd(struct mmc *mmc)
 396 {
 397         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 398
 399         if (cfg->cd_gpio < 0)
 400                 return 1;
 401
 402         debug("SD card %d is %spresent (GPIO %d)\n",
 403                 cfg - tx6qdl_esdhc_cfg,
 404                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 405                 cfg->cd_gpio);
 406         return !gpio_get_value(cfg->cd_gpio);
 407 }
 408
 409 int board_mmc_init(bd_t *bis)
 410 {
 411         int i;
 412
 413         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 414                 struct mmc *mmc;
 415                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 416                 int ret;
 417
 418                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 419                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 420
 421                 if (cfg->cd_gpio >= 0) {
 422                         ret = gpio_request_one(cfg->cd_gpio,
 423                                         GPIOFLAG_INPUT, "MMC CD");
 424                         if (ret) {
 425                                 printf("Error %d requesting GPIO%d_%d\n",
 426                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 427                                 continue;
 428                         }
 429                 }
 430
 431                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 432                 fsl_esdhc_initialize(bis, &cfg->cfg);
 433
 434                 mmc = find_mmc_device(i);
 435                 if (mmc == NULL)
 436                         continue;
 437                 if (board_mmc_getcd(mmc))
 438                         mmc_init(mmc);
 439         }
 440         return 0;
 441 }
 442 #endif /* CONFIG_CMD_MMC */
 443
 444 #ifdef CONFIG_FEC_MXC
 445
 446 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 447                         PAD_CTL_SRE_FAST)
 448 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 449 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 450
 451 #ifndef ETH_ALEN
 452 #define ETH_ALEN 6
 453 #endif
 454
 455 int board_eth_init(bd_t *bis)
 456 {
 457         int ret;
 458
 459         /* delay at least 21ms for the PHY internal POR signal to deassert */
 460         udelay(22000);
 461
 462         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 463                                         ARRAY_SIZE(tx6qdl_fec_pads));
 464
 465         /* Deassert RESET to the external phy */
 466         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 467
 468         ret = cpu_eth_init(bis);
 469         if (ret)
 470                 printf("cpu_eth_init() failed: %d\n", ret);
 471
 472         return ret;
 473 }
 474
 475 static void tx6_init_mac(void)
 476 {
 477         u8 mac[ETH_ALEN];
 478
 479         imx_get_mac_from_fuse(-1, mac);
 480         if (!is_valid_ether_addr(mac)) {
 481                 printf("No valid MAC address programmed\n");
 482                 return;
 483         }
 484
 485         printf("MAC addr from fuse: %pM\n", mac);
 486         eth_setenv_enetaddr("ethaddr", mac);
 487 }
 488 #else
 489 static inline void tx6_init_mac(void)
 490 {
 491 }
 492 #endif /* CONFIG_FEC_MXC */
 493
 494 enum {
 495         LED_STATE_INIT = -1,
 496         LED_STATE_OFF,
 497         LED_STATE_ON,
 498 };
 499
 500 static inline int calc_blink_rate(void)
 501 {
 502         if (!tx6_temp_check_enabled)
 503                 return CONFIG_SYS_HZ;
 504
 505         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 506                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 507                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 508 }
 509
 510 void show_activity(int arg)
 511 {
 512         static int led_state = LED_STATE_INIT;
 513         static int blink_rate;
 514         static ulong last;
 515
 516         if (led_state == LED_STATE_INIT) {
 517                 last = get_timer(0);
 518                 gpio_set_value(TX6_LED_GPIO, 1);
 519                 led_state = LED_STATE_ON;
 520                 blink_rate = calc_blink_rate();
 521         } else {
 522                 if (get_timer(last) > blink_rate) {
 523                         blink_rate = calc_blink_rate();
 524                         last = get_timer_masked();
 525                         if (led_state == LED_STATE_ON) {
 526                                 gpio_set_value(TX6_LED_GPIO, 0);
 527                         } else {
 528                                 gpio_set_value(TX6_LED_GPIO, 1);
 529                         }
 530                         led_state = 1 - led_state;
 531                 }
 532         }
 533 }
 534
 535 static const iomux_v3_cfg_t stk5_pads[] = {
 536         /* SW controlled LED on STK5 baseboard */
 537         MX6_PAD_EIM_A18__GPIO2_IO20,
 538
 539         /* I2C bus on DIMM pins 40/41 */
 540         MX6_PAD_GPIO_6__I2C3_SDA,
 541         MX6_PAD_GPIO_3__I2C3_SCL,
 542
 543         /* TSC200x PEN IRQ */
 544         MX6_PAD_EIM_D26__GPIO3_IO26,
 545
 546         /* EDT-FT5x06 Polytouch panel */
 547         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
 548         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
 549         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
 550
 551         /* USBH1 */
 552         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
 553         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
 554         /* USBOTG */
 555         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
 556         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
 557         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
 558 };
 559
 560 static const struct gpio stk5_gpios[] = {
 561         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 562
 563         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 564         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 565         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 566         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 567         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 568 };
 569
 570 #ifdef CONFIG_LCD
 571 static u16 tx6_cmap[256];
 572 vidinfo_t panel_info = {
 573         /* set to max. size supported by SoC */
 574         .vl_col = 1920,
 575         .vl_row = 1080,
 576
 577         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 578         .cmap = tx6_cmap,
 579 };
 580
 581 static struct fb_videomode tx6_fb_modes[] = {
 582 #ifndef CONFIG_SYS_LVDS_IF
 583         {
 584                 /* Standard VGA timing */
 585                 .name           = "VGA",
 586                 .refresh        = 60,
 587                 .xres           = 640,
 588                 .yres           = 480,
 589                 .pixclock       = KHZ2PICOS(25175),
 590                 .left_margin    = 48,
 591                 .hsync_len      = 96,
 592                 .right_margin   = 16,
 593                 .upper_margin   = 31,
 594                 .vsync_len      = 2,
 595                 .lower_margin   = 12,
 596                 .sync           = FB_SYNC_CLK_LAT_FALL,
 597         },
 598         {
 599                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 600                  * DE high active, 115.2 mm x 86.4 mm display area
 601                  * VGA compatible timing
 602                  */
 603                 .name           = "ETV570",
 604                 .refresh        = 60,
 605                 .xres           = 640,
 606                 .yres           = 480,
 607                 .pixclock       = KHZ2PICOS(25175),
 608                 .left_margin    = 114,
 609                 .hsync_len      = 30,
 610                 .right_margin   = 16,
 611                 .upper_margin   = 32,
 612                 .vsync_len      = 3,
 613                 .lower_margin   = 10,
 614                 .sync           = FB_SYNC_CLK_LAT_FALL,
 615         },
 616         {
 617                 /* Emerging ET0350G0DH6 320 x 240 display.
 618                  * 70.08 mm x 52.56 mm display area.
 619                  */
 620                 .name           = "ET0350",
 621                 .refresh        = 60,
 622                 .xres           = 320,
 623                 .yres           = 240,
 624                 .pixclock       = KHZ2PICOS(6500),
 625                 .left_margin    = 68 - 34,
 626                 .hsync_len      = 34,
 627                 .right_margin   = 20,
 628                 .upper_margin   = 18 - 3,
 629                 .vsync_len      = 3,
 630                 .lower_margin   = 4,
 631                 .sync           = FB_SYNC_CLK_LAT_FALL,
 632         },
 633         {
 634                 /* Emerging ET0430G0DH6 480 x 272 display.
 635                  * 95.04 mm x 53.856 mm display area.
 636                  */
 637                 .name           = "ET0430",
 638                 .refresh        = 60,
 639                 .xres           = 480,
 640                 .yres           = 272,
 641                 .pixclock       = KHZ2PICOS(9000),
 642                 .left_margin    = 2,
 643                 .hsync_len      = 41,
 644                 .right_margin   = 2,
 645                 .upper_margin   = 2,
 646                 .vsync_len      = 10,
 647                 .lower_margin   = 2,
 648                 .sync           = FB_SYNC_CLK_LAT_FALL,
 649         },
 650         {
 651                 /* Emerging ET0500G0DH6 800 x 480 display.
 652                  * 109.6 mm x 66.4 mm display area.
 653                  */
 654                 .name           = "ET0500",
 655                 .refresh        = 60,
 656                 .xres           = 800,
 657                 .yres           = 480,
 658                 .pixclock       = KHZ2PICOS(33260),
 659                 .left_margin    = 216 - 128,
 660                 .hsync_len      = 128,
 661                 .right_margin   = 1056 - 800 - 216,
 662                 .upper_margin   = 35 - 2,
 663                 .vsync_len      = 2,
 664                 .lower_margin   = 525 - 480 - 35,
 665                 .sync           = FB_SYNC_CLK_LAT_FALL,
 666         },
 667         {
 668                 /* Emerging ETQ570G0DH6 320 x 240 display.
 669                  * 115.2 mm x 86.4 mm display area.
 670                  */
 671                 .name           = "ETQ570",
 672                 .refresh        = 60,
 673                 .xres           = 320,
 674                 .yres           = 240,
 675                 .pixclock       = KHZ2PICOS(6400),
 676                 .left_margin    = 38,
 677                 .hsync_len      = 30,
 678                 .right_margin   = 30,
 679                 .upper_margin   = 16, /* 15 according to datasheet */
 680                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 681                 .lower_margin   = 4, /* 4.5 according to datasheet */
 682                 .sync           = FB_SYNC_CLK_LAT_FALL,
 683         },
 684         {
 685                 /* Emerging ET0700G0DH6 800 x 480 display.
 686                  * 152.4 mm x 91.44 mm display area.
 687                  */
 688                 .name           = "ET0700",
 689                 .refresh        = 60,
 690                 .xres           = 800,
 691                 .yres           = 480,
 692                 .pixclock       = KHZ2PICOS(33260),
 693                 .left_margin    = 216 - 128,
 694                 .hsync_len      = 128,
 695                 .right_margin   = 1056 - 800 - 216,
 696                 .upper_margin   = 35 - 2,
 697                 .vsync_len      = 2,
 698                 .lower_margin   = 525 - 480 - 35,
 699                 .sync           = FB_SYNC_CLK_LAT_FALL,
 700         },
 701         {
 702                 /* Emerging ET070001DM6 800 x 480 display.
 703                  * 152.4 mm x 91.44 mm display area.
 704                  */
 705                 .name           = "ET070001DM6",
 706                 .refresh        = 60,
 707                 .xres           = 800,
 708                 .yres           = 480,
 709                 .pixclock       = KHZ2PICOS(33260),
 710                 .left_margin    = 216 - 128,
 711                 .hsync_len      = 128,
 712                 .right_margin   = 1056 - 800 - 216,
 713                 .upper_margin   = 35 - 2,
 714                 .vsync_len      = 2,
 715                 .lower_margin   = 525 - 480 - 35,
 716                 .sync           = 0,
 717         },
 718 #else
 719         {
 720                 /* HannStar HSD100PXN1
 721                  * 202.7m mm x 152.06 mm display area.
 722                  */
 723                 .name           = "HSD100PXN1",
 724                 .refresh        = 60,
 725                 .xres           = 1024,
 726                 .yres           = 768,
 727                 .pixclock       = KHZ2PICOS(65000),
 728                 .left_margin    = 0,
 729                 .hsync_len      = 0,
 730                 .right_margin   = 320,
 731                 .upper_margin   = 0,
 732                 .vsync_len      = 0,
 733                 .lower_margin   = 38,
 734                 .sync           = FB_SYNC_CLK_LAT_FALL,
 735         },
 736 #endif
 737         {
 738                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 739                 .refresh        = 60,
 740                 .left_margin    = 48,
 741                 .hsync_len      = 96,
 742                 .right_margin   = 16,
 743                 .upper_margin   = 31,
 744                 .vsync_len      = 2,
 745                 .lower_margin   = 12,
 746                 .sync           = FB_SYNC_CLK_LAT_FALL,
 747         },
 748 };
 749
 750 static int lcd_enabled = 1;
 751 static int lcd_bl_polarity;
 752
 753 static int lcd_backlight_polarity(void)
 754 {
 755         return lcd_bl_polarity;
 756 }
 757
 758 void lcd_enable(void)
 759 {
 760         /* HACK ALERT:
 761          * global variable from common/lcd.c
 762          * Set to 0 here to prevent messages from going to LCD
 763          * rather than serial console
 764          */
 765         lcd_is_enabled = 0;
 766
 767         karo_load_splashimage(1);
 768
 769         if (lcd_enabled) {
 770                 debug("Switching LCD on\n");
 771                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 772                 udelay(100);
 773                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 774                 udelay(300000);
 775                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 776                         lcd_backlight_polarity());
 777         }
 778 }
 779
 780 void lcd_disable(void)
 781 {
 782         if (lcd_enabled) {
 783                 printf("Disabling LCD\n");
 784                 ipuv3_fb_shutdown();
 785         }
 786 }
 787
 788 void lcd_panel_disable(void)
 789 {
 790         if (lcd_enabled) {
 791                 debug("Switching LCD off\n");
 792                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 793                         !lcd_backlight_polarity());
 794                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 795                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 796         }
 797 }
 798
 799 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 800         /* LCD RESET */
 801         MX6_PAD_EIM_D29__GPIO3_IO29,
 802         /* LCD POWER_ENABLE */
 803         MX6_PAD_EIM_EB3__GPIO2_IO31,
 804         /* LCD Backlight (PWM) */
 805         MX6_PAD_GPIO_1__GPIO1_IO01,
 806
 807 #ifndef CONFIG_SYS_LVDS_IF
 808         /* Display */
 809         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 810         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 811         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 812         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 813         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 814         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 815         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 816         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 817         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 818         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 819         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 820         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 821         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 822         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 823         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 824         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 825         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 826         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 827         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 828         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 829         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 830         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 831         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 832         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 833         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
 834         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
 835         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 836         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 837 #endif
 838 };
 839
 840 static const struct gpio stk5_lcd_gpios[] = {
 841         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
 842         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
 843         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 844 };
 845
 846 void lcd_ctrl_init(void *lcdbase)
 847 {
 848         int color_depth = 24;
 849         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 850         const char *vm;
 851         unsigned long val;
 852         int refresh = 60;
 853         struct fb_videomode *p = &tx6_fb_modes[0];
 854         struct fb_videomode fb_mode;
 855         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 856         int pix_fmt;
 857         int lcd_bus_width;
 858         unsigned long di_clk_rate = 65000000;
 859
 860         if (!lcd_enabled) {
 861                 debug("LCD disabled\n");
 862                 return;
 863         }
 864
 865         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 866                 debug("Disabling LCD\n");
 867                 lcd_enabled = 0;
 868                 setenv("splashimage", NULL);
 869                 return;
 870         }
 871
 872         karo_fdt_move_fdt();
 873         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 874
 875         if (video_mode == NULL) {
 876                 debug("Disabling LCD\n");
 877                 lcd_enabled = 0;
 878                 return;
 879         }
 880         vm = video_mode;
 881         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 882                 p = &fb_mode;
 883                 debug("Using video mode from FDT\n");
 884                 vm += strlen(vm);
 885                 if (fb_mode.xres > panel_info.vl_col ||
 886                         fb_mode.yres > panel_info.vl_row) {
 887                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 888                                 fb_mode.xres, fb_mode.yres,
 889                                 panel_info.vl_col, panel_info.vl_row);
 890                         lcd_enabled = 0;
 891                         return;
 892                 }
 893         }
 894         if (p->name != NULL)
 895                 debug("Trying compiled-in video modes\n");
 896         while (p->name != NULL) {
 897                 if (strcmp(p->name, vm) == 0) {
 898                         debug("Using video mode: '%s'\n", p->name);
 899                         vm += strlen(vm);
 900                         break;
 901                 }
 902                 p++;
 903         }
 904         if (*vm != '\0')
 905                 debug("Trying to decode video_mode: '%s'\n", vm);
 906         while (*vm != '\0') {
 907                 if (*vm >= '0' && *vm <= '9') {
 908                         char *end;
 909
 910                         val = simple_strtoul(vm, &end, 0);
 911                         if (end > vm) {
 912                                 if (!xres_set) {
 913                                         if (val > panel_info.vl_col)
 914                                                 val = panel_info.vl_col;
 915                                         p->xres = val;
 916                                         panel_info.vl_col = val;
 917                                         xres_set = 1;
 918                                 } else if (!yres_set) {
 919                                         if (val > panel_info.vl_row)
 920                                                 val = panel_info.vl_row;
 921                                         p->yres = val;
 922                                         panel_info.vl_row = val;
 923                                         yres_set = 1;
 924                                 } else if (!bpp_set) {
 925                                         switch (val) {
 926                                         case 32:
 927                                         case 24:
 928                                                 if (is_lvds())
 929                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 930                                                 /* fallthru */
 931                                         case 16:
 932                                         case 8:
 933                                                 color_depth = val;
 934                                                 break;
 935
 936                                         case 18:
 937                                                 if (is_lvds()) {
 938                                                         color_depth = val;
 939                                                         break;
 940                                                 }
 941                                                 /* fallthru */
 942                                         default:
 943                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 944                                                         end - vm, vm, color_depth);
 945                                         }
 946                                         bpp_set = 1;
 947                                 } else if (!refresh_set) {
 948                                         refresh = val;
 949                                         refresh_set = 1;
 950                                 }
 951                         }
 952                         vm = end;
 953                 }
 954                 switch (*vm) {
 955                 case '@':
 956                         bpp_set = 1;
 957                         /* fallthru */
 958                 case '-':
 959                         yres_set = 1;
 960                         /* fallthru */
 961                 case 'x':
 962                         xres_set = 1;
 963                         /* fallthru */
 964                 case 'M':
 965                 case 'R':
 966                         vm++;
 967                         break;
 968
 969                 default:
 970                         if (*vm != '\0')
 971                                 vm++;
 972                 }
 973         }
 974         if (p->xres == 0 || p->yres == 0) {
 975                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 976                 lcd_enabled = 0;
 977                 printf("Supported video modes are:");
 978                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 979                         printf(" %s", p->name);
 980                 }
 981                 printf("\n");
 982                 return;
 983         }
 984         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 985                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 986                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 987                 lcd_enabled = 0;
 988                 return;
 989         }
 990         panel_info.vl_col = p->xres;
 991         panel_info.vl_row = p->yres;
 992
 993         switch (color_depth) {
 994         case 8:
 995                 panel_info.vl_bpix = LCD_COLOR8;
 996                 break;
 997         case 16:
 998                 panel_info.vl_bpix = LCD_COLOR16;
 999                 break;
1000         default:
1001                 panel_info.vl_bpix = LCD_COLOR32;
1002         }
1003
1004         p->pixclock = KHZ2PICOS(refresh *
1005                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1006                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1007                                 1000);
1008         debug("Pixel clock set to %lu.%03lu MHz\n",
1009                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1010
1011         if (p != &fb_mode) {
1012                 int ret;
1013
1014                 debug("Creating new display-timing node from '%s'\n",
1015                         video_mode);
1016                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1017                 if (ret)
1018                         printf("Failed to create new display-timing node from '%s': %d\n",
1019                                 video_mode, ret);
1020         }
1021
1022         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1023         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1024                                         ARRAY_SIZE(stk5_lcd_pads));
1025
1026         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1027         switch (lcd_bus_width) {
1028         case 24:
1029                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1030                 break;
1031
1032         case 18:
1033                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1034                 break;
1035
1036         case 16:
1037                 if (!is_lvds()) {
1038                         pix_fmt = IPU_PIX_FMT_RGB565;
1039                         break;
1040                 }
1041                 /* fallthru */
1042         default:
1043                 lcd_enabled = 0;
1044                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1045                         lcd_bus_width);
1046                 return;
1047         }
1048         if (is_lvds()) {
1049                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1050                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1051                 uint32_t gpr2;
1052                 uint32_t gpr3;
1053
1054                 if (lvds_chan_mask == 0) {
1055                         printf("No LVDS channel active\n");
1056                         lcd_enabled = 0;
1057                         return;
1058                 }
1059
1060                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1061                 if (lcd_bus_width == 24)
1062                         gpr2 |= (1 << 5) | (1 << 7);
1063                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1064                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1065                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1066                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1067
1068                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1069                 gpr3 &= ~((3 << 8) | (3 << 6));
1070                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1071         }
1072         if (karo_load_splashimage(0) == 0) {
1073                 int ret;
1074
1075                 debug("Initializing LCD controller\n");
1076                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1077                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1078                                 di_clk_rate, -1);
1079                 if (ret) {
1080                         printf("Failed to initialize FB driver: %d\n", ret);
1081                         lcd_enabled = 0;
1082                 }
1083         } else {
1084                 debug("Skipping initialization of LCD controller\n");
1085         }
1086 }
1087 #else
1088 #define lcd_enabled 0
1089 #endif /* CONFIG_LCD */
1090
1091 static void stk5_board_init(void)
1092 {
1093         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1094         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1095 }
1096
1097 static void stk5v3_board_init(void)
1098 {
1099         stk5_board_init();
1100 }
1101
1102 static void stk5v5_board_init(void)
1103 {
1104         stk5_board_init();
1105
1106         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1107                         "Flexcan Transceiver");
1108         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1109 }
1110
1111 static void tx6qdl_set_cpu_clock(void)
1112 {
1113         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1114
1115         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1116                 return;
1117
1118         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1119                 printf("%s detected; skipping cpu clock change\n",
1120                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1121                 return;
1122         }
1123         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1124                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1125                 printf("CPU clock set to %lu.%03lu MHz\n",
1126                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1127         } else {
1128                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1129         }
1130 }
1131
1132 int board_late_init(void)
1133 {
1134         int ret = 0;
1135         const char *baseboard;
1136
1137         env_cleanup();
1138
1139         if (tx6_temp_check_enabled)
1140                 check_cpu_temperature(1);
1141
1142         tx6qdl_set_cpu_clock();
1143
1144         if (had_ctrlc())
1145                 setenv_ulong("safeboot", 1);
1146         else if (wrsr & WRSR_TOUT)
1147                 setenv_ulong("wdreset", 1);
1148         else
1149                 karo_fdt_move_fdt();
1150
1151         baseboard = getenv("baseboard");
1152         if (!baseboard)
1153                 goto exit;
1154
1155         printf("Baseboard: %s\n", baseboard);
1156
1157         if (strncmp(baseboard, "stk5", 4) == 0) {
1158                 if ((strlen(baseboard) == 4) ||
1159                         strcmp(baseboard, "stk5-v3") == 0) {
1160                         stk5v3_board_init();
1161                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1162                         const char *otg_mode = getenv("otg_mode");
1163
1164                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1165                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1166                                         otg_mode, baseboard);
1167                                 setenv("otg_mode", "none");
1168                         }
1169                         stk5v5_board_init();
1170                 } else {
1171                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1172                                 baseboard + 4);
1173                 }
1174         } else {
1175                 printf("WARNING: Unsupported baseboard: '%s'\n",
1176                         baseboard);
1177                 ret = -EINVAL;
1178         }
1179
1180 exit:
1181         tx6_init_mac();
1182
1183         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1184         clear_ctrlc();
1185         return ret;
1186 }
1187
1188 #ifdef CONFIG_TX6_NAND
1189 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1190 #else
1191 #ifdef CONFIG_MMC_BOOT_SIZE
1192 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
1193 #else
1194 #define TX6_FLASH_SZ    2
1195 #endif
1196 #endif /* CONFIG_TX6_NAND */
1197
1198 #define TX6_DDR_SZ      (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
1199
1200 static char tx6_mem_table[] = {
1201         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
1202         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
1203         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
1204         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
1205         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
1206         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
1207         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
1208         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
1209         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
1210         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
1211         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
1212         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
1213 };
1214
1215 static inline char tx6_mem_suffix(void)
1216 {
1217         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1218
1219         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1220                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1221
1222         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1223                 return '?';
1224
1225         return tx6_mem_table[mem_idx];
1226 };
1227
1228 static struct {
1229         uchar addr;
1230         uchar rev;
1231 } tx6_mod_revs[] = {
1232         { 0x3c, 1, },
1233         { 0x32, 2, },
1234         { 0x33, 3, },
1235 };
1236
1237 static int tx6_get_mod_rev(void)
1238 {
1239         int i;
1240
1241         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
1242                 int ret = i2c_probe(tx6_mod_revs[i].addr);
1243                 if (ret == 0) {
1244                         debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr);
1245                         return tx6_mod_revs[i].rev;
1246                 }
1247                 debug("I2C probe returned %d for addr %02x\n", ret,
1248                         tx6_mod_revs[i].addr);
1249         }
1250         return 0;
1251 }
1252
1253 int checkboard(void)
1254 {
1255         u32 cpurev = get_cpu_rev();
1256         int cpu_variant = (cpurev >> 12) & 0xff;
1257
1258         tx6qdl_print_cpuinfo();
1259
1260         i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */);
1261
1262         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1263                 tx6_mod_suffix,
1264                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1265                 is_lvds(), tx6_get_mod_rev(),
1266                 tx6_mem_suffix());
1267
1268         return 0;
1269 }
1270
1271 #ifdef CONFIG_SERIAL_TAG
1272 void get_board_serial(struct tag_serialnr *serialnr)
1273 {
1274         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1275         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1276
1277         serialnr->low = readl(&fuse->cfg0);
1278         serialnr->high = readl(&fuse->cfg1);
1279 }
1280 #endif
1281
1282 #if defined(CONFIG_OF_BOARD_SETUP)
1283 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1284 #include <jffs2/jffs2.h>
1285 #include <mtd_node.h>
1286 static struct node_info nodes[] = {
1287         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1288 };
1289 #else
1290 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1291 #endif
1292
1293 static const char *tx6_touchpanels[] = {
1294         "ti,tsc2007",
1295         "edt,edt-ft5x06",
1296         "eeti,egalax_ts",
1297 };
1298
1299 int ft_board_setup(void *blob, bd_t *bd)
1300 {
1301         const char *baseboard = getenv("baseboard");
1302         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1303         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1304         int ret;
1305
1306         ret = fdt_increase_size(blob, 4096);
1307         if (ret) {
1308                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1309                 return ret;
1310         }
1311         if (stk5_v5)
1312                 karo_fdt_enable_node(blob, "stk5led", 0);
1313
1314         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1315         fdt_fixup_ethernet(blob);
1316
1317         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1318                                 ARRAY_SIZE(tx6_touchpanels));
1319         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1320         karo_fdt_fixup_flexcan(blob, stk5_v5);
1321
1322         karo_fdt_update_fb_mode(blob, video_mode);
1323
1324         return 0;
1325 }
1326 #endif /* CONFIG_OF_BOARD_SETUP */