board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  38
  39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  42
  43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
  45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
  46
  47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  49 #else
  50 #define TEMPERATURE_MIN                 (-40)
  51 #endif
  52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  54 #else
  55 #define TEMPERATURE_HOT                 80
  56 #endif
  57
  58 DECLARE_GLOBAL_DATA_PTR;
  59
  60 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  61
  62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  63 #ifdef CONFIG_SECURE_BOOT
  64 char __csf_data[0] __attribute__((section(".__csf_data")));
  65 #endif
  66
  67 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  68         /* RESET_OUT */
  69         MX6_PAD_GPIO_17__GPIO7_IO12,
  70
  71         /* UART pads */
  72 #if CONFIG_MXC_UART_BASE == UART1_BASE
  73         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
  74         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
  75         MX6_PAD_SD3_DAT1__UART1_RTS_B,
  76         MX6_PAD_SD3_DAT0__UART1_CTS_B,
  77 #endif
  78 #if CONFIG_MXC_UART_BASE == UART2_BASE
  79         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
  80         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
  81         MX6_PAD_SD4_DAT5__UART2_RTS_B,
  82         MX6_PAD_SD4_DAT6__UART2_CTS_B,
  83 #endif
  84 #if CONFIG_MXC_UART_BASE == UART3_BASE
  85         MX6_PAD_EIM_D24__UART3_TX_DATA,
  86         MX6_PAD_EIM_D25__UART3_RX_DATA,
  87         MX6_PAD_SD3_RST__UART3_RTS_B,
  88         MX6_PAD_SD3_DAT3__UART3_CTS_B,
  89 #endif
  90         /* internal I2C */
  91         MX6_PAD_EIM_D28__I2C1_SDA,
  92         MX6_PAD_EIM_D21__I2C1_SCL,
  93
  94         /* FEC PHY GPIO functions */
  95         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
  96         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
  97         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
  98 };
  99
 100 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 101         /* FEC functions */
 102         MX6_PAD_ENET_MDC__ENET_MDC,
 103         MX6_PAD_ENET_MDIO__ENET_MDIO,
 104         MX6_PAD_GPIO_16__ENET_REF_CLK,
 105         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 106         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 107         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
 108         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
 109         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 110         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
 111         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 112 };
 113
 114 #define TX6_I2C_GPIO_PAD_CTRL   (PAD_CTL_PUS_22K_UP |   \
 115                                 PAD_CTL_SPEED_MED |     \
 116                                 PAD_CTL_DSE_34ohm |     \
 117                                 PAD_CTL_SRE_FAST)
 118
 119 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 120         /* internal I2C */
 121         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
 122         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
 123 };
 124
 125 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
 126         /* internal I2C */
 127         MX6_PAD_EIM_D28__I2C1_SDA,
 128         MX6_PAD_EIM_D21__I2C1_SCL,
 129 };
 130
 131 static const struct gpio const tx6qdl_gpios[] = {
 132         /* These two entries are used to forcefully reinitialize the I2C bus */
 133         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 134         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 135
 136         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 137         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 138         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 139         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 140 };
 141
 142 static int pmic_addr __data;
 143
 144 #if defined(CONFIG_SOC_MX6Q)
 145 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
 146 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
 147 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
 148 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
 149 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
 150 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
 151 #define I2C1_SEL_INPUT_VAL                      0
 152 #endif
 153 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 154 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
 155 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
 156 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
 157 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
 158 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
 159 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
 160 #define I2C1_SEL_INPUT_VAL                      1
 161 #endif
 162
 163 #define GPIO_DR 0
 164 #define GPIO_DIR 4
 165 #define GPIO_PSR 8
 166
 167 static void tx6_i2c_recover(void)
 168 {
 169         int i;
 170         int bad = 0;
 171 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
 172 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
 173
 174         if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
 175                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
 176                 return;
 177
 178         debug("Clearing I2C bus\n");
 179         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
 180                 printf("I2C SCL stuck LOW\n");
 181                 bad++;
 182
 183                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
 184                         GPIO3_BASE_ADDR + GPIO_DR);
 185                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
 186                         GPIO3_BASE_ADDR + GPIO_DIR);
 187         }
 188         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
 189                 printf("I2C SDA stuck LOW\n");
 190                 bad++;
 191
 192                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
 193                         GPIO3_BASE_ADDR + GPIO_DIR);
 194                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
 195                         GPIO3_BASE_ADDR + GPIO_DR);
 196                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
 197                         GPIO3_BASE_ADDR + GPIO_DIR);
 198
 199                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 200                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
 201                 udelay(10);
 202
 203                 for (i = 0; i < 18; i++) {
 204                         u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
 205
 206                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 207                         writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
 208                         udelay(10);
 209                         if (reg & SCL_BIT &&
 210                                 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
 211                                 break;
 212                 }
 213         }
 214         if (bad) {
 215                 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
 216
 217                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
 218                         printf("I2C bus recovery succeeded\n");
 219                 } else {
 220                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
 221                                 SCL_BIT | SDA_BIT);
 222                 }
 223         }
 224         debug("Setting up I2C Pads\n");
 225         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
 226                                         ARRAY_SIZE(tx6_i2c_pads));
 227 }
 228
 229 /* placed in section '.data' to prevent overwriting relocation info
 230  * overlayed with bss
 231  */
 232 static u32 wrsr __data;
 233
 234 #define WRSR_POR                        (1 << 4)
 235 #define WRSR_TOUT                       (1 << 1)
 236 #define WRSR_SFTW                       (1 << 0)
 237
 238 static void print_reset_cause(void)
 239 {
 240         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 241         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 242         u32 srsr;
 243         char *dlm = "";
 244
 245         printf("Reset cause: ");
 246
 247         srsr = readl(&src_regs->srsr);
 248         wrsr = readw(wdt_base + 4);
 249
 250         if (wrsr & WRSR_POR) {
 251                 printf("%sPOR", dlm);
 252                 dlm = " | ";
 253         }
 254         if (srsr & 0x00004) {
 255                 printf("%sCSU", dlm);
 256                 dlm = " | ";
 257         }
 258         if (srsr & 0x00008) {
 259                 printf("%sIPP USER", dlm);
 260                 dlm = " | ";
 261         }
 262         if (srsr & 0x00010) {
 263                 if (wrsr & WRSR_SFTW) {
 264                         printf("%sSOFT", dlm);
 265                         dlm = " | ";
 266                 }
 267                 if (wrsr & WRSR_TOUT) {
 268                         printf("%sWDOG", dlm);
 269                         dlm = " | ";
 270                 }
 271         }
 272         if (srsr & 0x00020) {
 273                 printf("%sJTAG HIGH-Z", dlm);
 274                 dlm = " | ";
 275         }
 276         if (srsr & 0x00040) {
 277                 printf("%sJTAG SW", dlm);
 278                 dlm = " | ";
 279         }
 280         if (srsr & 0x10000) {
 281                 printf("%sWARM BOOT", dlm);
 282                 dlm = " | ";
 283         }
 284         if (dlm[0] == '\0')
 285                 printf("unknown");
 286
 287         printf("\n");
 288 }
 289
 290 static const char __data *tx6_mod_suffix;
 291
 292 #ifdef CONFIG_IMX6_THERMAL
 293 #include <thermal.h>
 294 #include <imx_thermal.h>
 295 #include <fuse.h>
 296
 297 static void print_temperature(void)
 298 {
 299         struct udevice *thermal_dev;
 300         int cpu_tmp, minc, maxc, ret;
 301         char const *grade_str;
 302         static u32 __data thermal_calib;
 303
 304         puts("Temperature: ");
 305         switch (get_cpu_temp_grade(&minc, &maxc)) {
 306         case TEMP_AUTOMOTIVE:
 307                 grade_str = "Automotive";
 308                 break;
 309         case TEMP_INDUSTRIAL:
 310                 grade_str = "Industrial";
 311                 break;
 312         case TEMP_EXTCOMMERCIAL:
 313                 grade_str = "Extended Commercial";
 314                 break;
 315         default:
 316                 grade_str = "Commercial";
 317         }
 318         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 319         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 320         if (ret == 0) {
 321                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 322
 323                 if (ret == 0)
 324                         printf(" at %dC", cpu_tmp);
 325                 else
 326                         puts(" - failed to read sensor data");
 327         } else {
 328                 puts(" - no sensor device found");
 329         }
 330
 331         if (fuse_read(1, 6, &thermal_calib) == 0) {
 332                 printf(" - calibration data 0x%08x\n", thermal_calib);
 333         } else {
 334                 puts(" - Failed to read thermal calib fuse\n");
 335         }
 336 }
 337 #else
 338 static inline void print_temperature(void)
 339 {
 340 }
 341 #endif
 342
 343 int checkboard(void)
 344 {
 345         u32 cpurev = get_cpu_rev();
 346         char *cpu_str = "?";
 347
 348         switch ((cpurev >> 12) & 0xff) {
 349         case MXC_CPU_MX6SL:
 350                 cpu_str = "SL";
 351                 tx6_mod_suffix = "?";
 352                 break;
 353         case MXC_CPU_MX6DL:
 354                 cpu_str = "DL";
 355                 tx6_mod_suffix = "U";
 356                 break;
 357         case MXC_CPU_MX6SOLO:
 358                 cpu_str = "SOLO";
 359                 tx6_mod_suffix = "S";
 360                 break;
 361         case MXC_CPU_MX6Q:
 362                 cpu_str = "Q";
 363                 tx6_mod_suffix = "Q";
 364                 break;
 365         }
 366
 367         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
 368                 cpu_str,
 369                 (cpurev & 0x000F0) >> 4,
 370                 (cpurev & 0x0000F) >> 0,
 371                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 372
 373         print_temperature();
 374         print_reset_cause();
 375 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 376         check_cpu_temperature(1);
 377 #endif
 378         tx6_i2c_recover();
 379         return 0;
 380 }
 381
 382 /* serial port not initialized at this point */
 383 int board_early_init_f(void)
 384 {
 385         return 0;
 386 }
 387
 388 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 389 static bool tx6_temp_check_enabled = true;
 390 #else
 391 #define tx6_temp_check_enabled  0
 392 #endif
 393
 394 #ifdef CONFIG_TX6_NAND
 395 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
 396 #else
 397 #ifdef CONFIG_MMC_BOOT_SIZE
 398 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
 399 #else
 400 #define TX6_FLASH_SZ    2
 401 #endif
 402 #endif /* CONFIG_TX6_NAND */
 403
 404 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
 405
 406 static char tx6_mem_table[] = {
 407         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
 408         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
 409         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
 410         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
 411         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
 412         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
 413         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
 414         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
 415         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
 416         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
 417         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
 418         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
 419 };
 420
 421 static struct {
 422         uchar addr;
 423         uchar rev;
 424 } tx6_mod_revs[] = {
 425         { 0x3c, 1, },
 426         { 0x32, 2, },
 427         { 0x33, 3, },
 428 };
 429
 430 static inline char tx6_mem_suffix(void)
 431 {
 432         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
 433
 434         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
 435                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
 436
 437         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
 438                 return '?';
 439
 440         return tx6_mem_table[mem_idx];
 441 };
 442
 443 static int tx6_get_mod_rev(unsigned int pmic_id)
 444 {
 445         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
 446                 return tx6_mod_revs[pmic_id].rev;
 447
 448         return 0;
 449 }
 450
 451 static int tx6_pmic_probe(void)
 452 {
 453         int i;
 454
 455         debug("%s@%d: \n", __func__, __LINE__);
 456
 457         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
 458                 u8 i2c_addr = tx6_mod_revs[i].addr;
 459                 int ret = i2c_probe(i2c_addr);
 460
 461                 if (ret == 0) {
 462                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
 463                         return i;
 464                 }
 465                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
 466         }
 467         return -EINVAL;
 468 }
 469
 470 int board_init(void)
 471 {
 472         int ret;
 473         u32 cpurev = get_cpu_rev();
 474         int cpu_variant = (cpurev >> 12) & 0xff;
 475         int pmic_id;
 476
 477         debug("%s@%d: \n", __func__, __LINE__);
 478
 479         pmic_id = tx6_pmic_probe();
 480         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
 481                 pmic_addr = tx6_mod_revs[pmic_id].addr;
 482
 483         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
 484                 tx6_mod_suffix,
 485                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
 486                 is_lvds(), tx6_get_mod_rev(pmic_id),
 487                 tx6_mem_suffix());
 488
 489         get_hab_status();
 490
 491         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 492         if (ret < 0) {
 493                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
 494         }
 495         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 496
 497         /* Address of boot parameters */
 498         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 499         gd->bd->bi_arch_number = -1;
 500
 501         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 502                 if (wrsr & WRSR_TOUT)
 503                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 504                 else
 505                         printf("<CTRL-C> detected; safeboot enabled\n");
 506 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 507                 tx6_temp_check_enabled = false;
 508 #endif
 509                 return 0;
 510         }
 511
 512         ret = tx6_pmic_init(pmic_addr, NULL, 0);
 513         if (ret) {
 514                 printf("Failed to setup PMIC voltages: %d\n", ret);
 515                 hang();
 516         }
 517         return 0;
 518 }
 519
 520 int dram_init(void)
 521 {
 522         debug("%s@%d: \n", __func__, __LINE__);
 523
 524         /* dram_init must store complete ramsize in gd->ram_size */
 525         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 526                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 527         return 0;
 528 }
 529
 530 void dram_init_banksize(void)
 531 {
 532         debug("%s@%d: \n", __func__, __LINE__);
 533
 534         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 535         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 536                         PHYS_SDRAM_1_SIZE);
 537 #if CONFIG_NR_DRAM_BANKS > 1
 538         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 539         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 540                         PHYS_SDRAM_2_SIZE);
 541 #endif
 542 }
 543
 544 #ifdef  CONFIG_FSL_ESDHC
 545 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
 546         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
 547         PAD_CTL_SRE_FAST)
 548
 549 static const iomux_v3_cfg_t mmc0_pads[] = {
 550         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 551         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 552         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 553         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 554         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 555         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 556         /* SD1 CD */
 557         MX6_PAD_SD3_CMD__GPIO7_IO02,
 558 };
 559
 560 static const iomux_v3_cfg_t mmc1_pads[] = {
 561         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 562         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 563         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 564         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 565         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 566         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 567         /* SD2 CD */
 568         MX6_PAD_SD3_CLK__GPIO7_IO03,
 569 };
 570
 571 #ifdef CONFIG_TX6_EMMC
 572 static const iomux_v3_cfg_t mmc3_pads[] = {
 573         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 574         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 575         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 576         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 577         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 578         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 579         /* eMMC RESET */
 580         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 581                                                 PAD_CTL_DSE_40ohm),
 582 };
 583 #endif
 584
 585 static struct tx6_esdhc_cfg {
 586         const iomux_v3_cfg_t *pads;
 587         int num_pads;
 588         enum mxc_clock clkid;
 589         struct fsl_esdhc_cfg cfg;
 590         int cd_gpio;
 591 } tx6qdl_esdhc_cfg[] = {
 592 #ifdef CONFIG_TX6_EMMC
 593         {
 594                 .pads = mmc3_pads,
 595                 .num_pads = ARRAY_SIZE(mmc3_pads),
 596                 .clkid = MXC_ESDHC4_CLK,
 597                 .cfg = {
 598                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 599                         .max_bus_width = 4,
 600                 },
 601                 .cd_gpio = -EINVAL,
 602         },
 603 #endif
 604         {
 605                 .pads = mmc0_pads,
 606                 .num_pads = ARRAY_SIZE(mmc0_pads),
 607                 .clkid = MXC_ESDHC_CLK,
 608                 .cfg = {
 609                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 610                         .max_bus_width = 4,
 611                 },
 612                 .cd_gpio = IMX_GPIO_NR(7, 2),
 613         },
 614         {
 615                 .pads = mmc1_pads,
 616                 .num_pads = ARRAY_SIZE(mmc1_pads),
 617                 .clkid = MXC_ESDHC2_CLK,
 618                 .cfg = {
 619                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 620                         .max_bus_width = 4,
 621                 },
 622                 .cd_gpio = IMX_GPIO_NR(7, 3),
 623         },
 624 };
 625
 626 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 627 {
 628         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 629 }
 630
 631 int board_mmc_getcd(struct mmc *mmc)
 632 {
 633         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 634
 635         if (cfg->cd_gpio < 0)
 636                 return 1;
 637
 638         debug("SD card %d is %spresent (GPIO %d)\n",
 639                 cfg - tx6qdl_esdhc_cfg,
 640                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 641                 cfg->cd_gpio);
 642         return !gpio_get_value(cfg->cd_gpio);
 643 }
 644
 645 int board_mmc_init(bd_t *bis)
 646 {
 647         int i;
 648
 649         debug("%s@%d: \n", __func__, __LINE__);
 650
 651         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 652                 struct mmc *mmc;
 653                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 654                 int ret;
 655
 656                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 657                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 658
 659                 if (cfg->cd_gpio >= 0) {
 660                         ret = gpio_request_one(cfg->cd_gpio,
 661                                         GPIOFLAG_INPUT, "MMC CD");
 662                         if (ret) {
 663                                 printf("Error %d requesting GPIO%d_%d\n",
 664                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 665                                 continue;
 666                         }
 667                 }
 668
 669                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 670                 fsl_esdhc_initialize(bis, &cfg->cfg);
 671
 672                 mmc = find_mmc_device(i);
 673                 if (mmc == NULL)
 674                         continue;
 675                 if (board_mmc_getcd(mmc))
 676                         mmc_init(mmc);
 677         }
 678         return 0;
 679 }
 680 #endif /* CONFIG_CMD_MMC */
 681
 682 #ifdef CONFIG_FEC_MXC
 683
 684 #ifndef ETH_ALEN
 685 #define ETH_ALEN 6
 686 #endif
 687
 688 int board_eth_init(bd_t *bis)
 689 {
 690         int ret;
 691
 692         debug("%s@%d: \n", __func__, __LINE__);
 693
 694         /* delay at least 21ms for the PHY internal POR signal to deassert */
 695         udelay(22000);
 696
 697         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 698                                         ARRAY_SIZE(tx6qdl_fec_pads));
 699
 700         /* Deassert RESET to the external phy */
 701         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 702
 703         ret = cpu_eth_init(bis);
 704         if (ret)
 705                 printf("cpu_eth_init() failed: %d\n", ret);
 706
 707         return ret;
 708 }
 709
 710 static void tx6_init_mac(void)
 711 {
 712         u8 mac[ETH_ALEN];
 713
 714         imx_get_mac_from_fuse(0, mac);
 715         if (!is_valid_ethaddr(mac)) {
 716                 printf("No valid MAC address programmed\n");
 717                 return;
 718         }
 719
 720         printf("MAC addr from fuse: %pM\n", mac);
 721         eth_setenv_enetaddr("ethaddr", mac);
 722 }
 723 #else
 724 static inline void tx6_init_mac(void)
 725 {
 726 }
 727 #endif /* CONFIG_FEC_MXC */
 728
 729 enum {
 730         LED_STATE_INIT = -1,
 731         LED_STATE_OFF,
 732         LED_STATE_ON,
 733 };
 734
 735 static inline int calc_blink_rate(void)
 736 {
 737         if (!tx6_temp_check_enabled)
 738                 return CONFIG_SYS_HZ;
 739
 740         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 741                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 742                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 743 }
 744
 745 void show_activity(int arg)
 746 {
 747         static int led_state = LED_STATE_INIT;
 748         static int blink_rate;
 749         static ulong last;
 750
 751         if (led_state == LED_STATE_INIT) {
 752                 last = get_timer(0);
 753                 gpio_set_value(TX6_LED_GPIO, 1);
 754                 led_state = LED_STATE_ON;
 755                 blink_rate = calc_blink_rate();
 756         } else {
 757                 if (get_timer(last) > blink_rate) {
 758                         blink_rate = calc_blink_rate();
 759                         last = get_timer_masked();
 760                         if (led_state == LED_STATE_ON) {
 761                                 gpio_set_value(TX6_LED_GPIO, 0);
 762                         } else {
 763                                 gpio_set_value(TX6_LED_GPIO, 1);
 764                         }
 765                         led_state = 1 - led_state;
 766                 }
 767         }
 768 }
 769
 770 static const iomux_v3_cfg_t stk5_pads[] = {
 771         /* SW controlled LED on STK5 baseboard */
 772         MX6_PAD_EIM_A18__GPIO2_IO20,
 773
 774         /* I2C bus on DIMM pins 40/41 */
 775         MX6_PAD_GPIO_6__I2C3_SDA,
 776         MX6_PAD_GPIO_3__I2C3_SCL,
 777
 778         /* TSC200x PEN IRQ */
 779         MX6_PAD_EIM_D26__GPIO3_IO26,
 780
 781         /* EDT-FT5x06 Polytouch panel */
 782         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
 783         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
 784         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
 785
 786         /* USBH1 */
 787         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
 788         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
 789         /* USBOTG */
 790         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
 791         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
 792         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
 793 };
 794
 795 static const struct gpio stk5_gpios[] = {
 796         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 797
 798         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 799         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 800         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 801         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 802         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 803 };
 804
 805 #ifdef CONFIG_LCD
 806 static u16 tx6_cmap[256];
 807 vidinfo_t panel_info = {
 808         /* set to max. size supported by SoC */
 809         .vl_col = 1920,
 810         .vl_row = 1080,
 811
 812         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 813         .cmap = tx6_cmap,
 814 };
 815
 816 static struct fb_videomode tx6_fb_modes[] = {
 817 #ifndef CONFIG_SYS_LVDS_IF
 818         {
 819                 /* Standard VGA timing */
 820                 .name           = "VGA",
 821                 .refresh        = 60,
 822                 .xres           = 640,
 823                 .yres           = 480,
 824                 .pixclock       = KHZ2PICOS(25175),
 825                 .left_margin    = 48,
 826                 .hsync_len      = 96,
 827                 .right_margin   = 16,
 828                 .upper_margin   = 31,
 829                 .vsync_len      = 2,
 830                 .lower_margin   = 12,
 831                 .sync           = FB_SYNC_CLK_LAT_FALL,
 832         },
 833         {
 834                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 835                  * DE high active, 115.2 mm x 86.4 mm display area
 836                  * VGA compatible timing
 837                  */
 838                 .name           = "ETV570",
 839                 .refresh        = 60,
 840                 .xres           = 640,
 841                 .yres           = 480,
 842                 .pixclock       = KHZ2PICOS(25175),
 843                 .left_margin    = 114,
 844                 .hsync_len      = 30,
 845                 .right_margin   = 16,
 846                 .upper_margin   = 32,
 847                 .vsync_len      = 3,
 848                 .lower_margin   = 10,
 849                 .sync           = FB_SYNC_CLK_LAT_FALL,
 850         },
 851         {
 852                 /* Emerging ET0350G0DH6 320 x 240 display.
 853                  * 70.08 mm x 52.56 mm display area.
 854                  */
 855                 .name           = "ET0350",
 856                 .refresh        = 60,
 857                 .xres           = 320,
 858                 .yres           = 240,
 859                 .pixclock       = KHZ2PICOS(6500),
 860                 .left_margin    = 68 - 34,
 861                 .hsync_len      = 34,
 862                 .right_margin   = 20,
 863                 .upper_margin   = 18 - 3,
 864                 .vsync_len      = 3,
 865                 .lower_margin   = 4,
 866                 .sync           = FB_SYNC_CLK_LAT_FALL,
 867         },
 868         {
 869                 /* Emerging ET0430G0DH6 480 x 272 display.
 870                  * 95.04 mm x 53.856 mm display area.
 871                  */
 872                 .name           = "ET0430",
 873                 .refresh        = 60,
 874                 .xres           = 480,
 875                 .yres           = 272,
 876                 .pixclock       = KHZ2PICOS(9000),
 877                 .left_margin    = 2,
 878                 .hsync_len      = 41,
 879                 .right_margin   = 2,
 880                 .upper_margin   = 2,
 881                 .vsync_len      = 10,
 882                 .lower_margin   = 2,
 883         },
 884         {
 885                 /* Emerging ET0500G0DH6 800 x 480 display.
 886                  * 109.6 mm x 66.4 mm display area.
 887                  */
 888                 .name           = "ET0500",
 889                 .refresh        = 60,
 890                 .xres           = 800,
 891                 .yres           = 480,
 892                 .pixclock       = KHZ2PICOS(33260),
 893                 .left_margin    = 216 - 128,
 894                 .hsync_len      = 128,
 895                 .right_margin   = 1056 - 800 - 216,
 896                 .upper_margin   = 35 - 2,
 897                 .vsync_len      = 2,
 898                 .lower_margin   = 525 - 480 - 35,
 899                 .sync           = FB_SYNC_CLK_LAT_FALL,
 900         },
 901         {
 902                 /* Emerging ETQ570G0DH6 320 x 240 display.
 903                  * 115.2 mm x 86.4 mm display area.
 904                  */
 905                 .name           = "ETQ570",
 906                 .refresh        = 60,
 907                 .xres           = 320,
 908                 .yres           = 240,
 909                 .pixclock       = KHZ2PICOS(6400),
 910                 .left_margin    = 38,
 911                 .hsync_len      = 30,
 912                 .right_margin   = 30,
 913                 .upper_margin   = 16, /* 15 according to datasheet */
 914                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 915                 .lower_margin   = 4, /* 4.5 according to datasheet */
 916                 .sync           = FB_SYNC_CLK_LAT_FALL,
 917         },
 918         {
 919                 /* Emerging ET0700G0DH6 800 x 480 display.
 920                  * 152.4 mm x 91.44 mm display area.
 921                  */
 922                 .name           = "ET0700",
 923                 .refresh        = 60,
 924                 .xres           = 800,
 925                 .yres           = 480,
 926                 .pixclock       = KHZ2PICOS(33260),
 927                 .left_margin    = 216 - 128,
 928                 .hsync_len      = 128,
 929                 .right_margin   = 1056 - 800 - 216,
 930                 .upper_margin   = 35 - 2,
 931                 .vsync_len      = 2,
 932                 .lower_margin   = 525 - 480 - 35,
 933                 .sync           = FB_SYNC_CLK_LAT_FALL,
 934         },
 935         {
 936                 /* Emerging ET070001DM6 800 x 480 display.
 937                  * 152.4 mm x 91.44 mm display area.
 938                  */
 939                 .name           = "ET070001DM6",
 940                 .refresh        = 60,
 941                 .xres           = 800,
 942                 .yres           = 480,
 943                 .pixclock       = KHZ2PICOS(33260),
 944                 .left_margin    = 216 - 128,
 945                 .hsync_len      = 128,
 946                 .right_margin   = 1056 - 800 - 216,
 947                 .upper_margin   = 35 - 2,
 948                 .vsync_len      = 2,
 949                 .lower_margin   = 525 - 480 - 35,
 950                 .sync           = 0,
 951         },
 952 #else
 953         {
 954                 /* HannStar HSD100PXN1
 955                  * 202.7m mm x 152.06 mm display area.
 956                  */
 957                 .name           = "HSD100PXN1",
 958                 .refresh        = 60,
 959                 .xres           = 1024,
 960                 .yres           = 768,
 961                 .pixclock       = KHZ2PICOS(65000),
 962                 .left_margin    = 0,
 963                 .hsync_len      = 0,
 964                 .right_margin   = 320,
 965                 .upper_margin   = 0,
 966                 .vsync_len      = 0,
 967                 .lower_margin   = 38,
 968                 .sync           = FB_SYNC_CLK_LAT_FALL,
 969         },
 970 #endif
 971         {
 972                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 973                 .refresh        = 60,
 974                 .left_margin    = 48,
 975                 .hsync_len      = 96,
 976                 .right_margin   = 16,
 977                 .upper_margin   = 31,
 978                 .vsync_len      = 2,
 979                 .lower_margin   = 12,
 980                 .sync           = FB_SYNC_CLK_LAT_FALL,
 981         },
 982 };
 983
 984 static int lcd_enabled = 1;
 985 static int lcd_bl_polarity;
 986
 987 static int lcd_backlight_polarity(void)
 988 {
 989         return lcd_bl_polarity;
 990 }
 991
 992 void lcd_enable(void)
 993 {
 994         /* HACK ALERT:
 995          * global variable from common/lcd.c
 996          * Set to 0 here to prevent messages from going to LCD
 997          * rather than serial console
 998          */
 999         lcd_is_enabled = 0;
1000
1001         if (lcd_enabled) {
1002                 karo_load_splashimage(1);
1003
1004                 debug("Switching LCD on\n");
1005                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1006                 udelay(100);
1007                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1008                 udelay(300000);
1009                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1010                         lcd_backlight_polarity());
1011         }
1012 }
1013
1014 void lcd_disable(void)
1015 {
1016         if (lcd_enabled) {
1017                 printf("Disabling LCD\n");
1018                 ipuv3_fb_shutdown();
1019         }
1020 }
1021
1022 void lcd_panel_disable(void)
1023 {
1024         if (lcd_enabled) {
1025                 debug("Switching LCD off\n");
1026                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1027                         !lcd_backlight_polarity());
1028                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1029                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1030         }
1031 }
1032
1033 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1034         /* LCD RESET */
1035         MX6_PAD_EIM_D29__GPIO3_IO29,
1036         /* LCD POWER_ENABLE */
1037         MX6_PAD_EIM_EB3__GPIO2_IO31,
1038         /* LCD Backlight (PWM) */
1039         MX6_PAD_GPIO_1__GPIO1_IO01,
1040
1041 #ifndef CONFIG_SYS_LVDS_IF
1042         /* Display */
1043         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
1044         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
1045         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
1046         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
1047         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
1048         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
1049         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
1050         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
1051         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
1052         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
1053         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
1054         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
1055         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
1056         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
1057         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
1058         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
1059         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
1060         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
1061         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
1062         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
1063         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
1064         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
1065         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
1066         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
1067         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
1068         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
1069         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
1070         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
1071 #endif
1072 };
1073
1074 static const struct gpio stk5_lcd_gpios[] = {
1075         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1076         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1077         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1078 };
1079
1080 void lcd_ctrl_init(void *lcdbase)
1081 {
1082         int color_depth = 24;
1083         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1084         const char *vm;
1085         unsigned long val;
1086         int refresh = 60;
1087         struct fb_videomode *p = &tx6_fb_modes[0];
1088         struct fb_videomode fb_mode;
1089         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1090         int pix_fmt;
1091         int lcd_bus_width;
1092         unsigned long di_clk_rate = 65000000;
1093
1094         if (!lcd_enabled) {
1095                 debug("LCD disabled\n");
1096                 return;
1097         }
1098
1099         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1100                 debug("Disabling LCD\n");
1101                 lcd_enabled = 0;
1102                 setenv("splashimage", NULL);
1103                 return;
1104         }
1105
1106         karo_fdt_move_fdt();
1107         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1108
1109         if (video_mode == NULL) {
1110                 debug("Disabling LCD\n");
1111                 lcd_enabled = 0;
1112                 return;
1113         }
1114         vm = video_mode;
1115         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1116                 p = &fb_mode;
1117                 debug("Using video mode from FDT\n");
1118                 vm += strlen(vm);
1119                 if (fb_mode.xres > panel_info.vl_col ||
1120                         fb_mode.yres > panel_info.vl_row) {
1121                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1122                                 fb_mode.xres, fb_mode.yres,
1123                                 panel_info.vl_col, panel_info.vl_row);
1124                         lcd_enabled = 0;
1125                         return;
1126                 }
1127         }
1128         if (p->name != NULL)
1129                 debug("Trying compiled-in video modes\n");
1130         while (p->name != NULL) {
1131                 if (strcmp(p->name, vm) == 0) {
1132                         debug("Using video mode: '%s'\n", p->name);
1133                         vm += strlen(vm);
1134                         break;
1135                 }
1136                 p++;
1137         }
1138         if (*vm != '\0')
1139                 debug("Trying to decode video_mode: '%s'\n", vm);
1140         while (*vm != '\0') {
1141                 if (*vm >= '0' && *vm <= '9') {
1142                         char *end;
1143
1144                         val = simple_strtoul(vm, &end, 0);
1145                         if (end > vm) {
1146                                 if (!xres_set) {
1147                                         if (val > panel_info.vl_col)
1148                                                 val = panel_info.vl_col;
1149                                         p->xres = val;
1150                                         panel_info.vl_col = val;
1151                                         xres_set = 1;
1152                                 } else if (!yres_set) {
1153                                         if (val > panel_info.vl_row)
1154                                                 val = panel_info.vl_row;
1155                                         p->yres = val;
1156                                         panel_info.vl_row = val;
1157                                         yres_set = 1;
1158                                 } else if (!bpp_set) {
1159                                         switch (val) {
1160                                         case 32:
1161                                         case 24:
1162                                                 if (is_lvds())
1163                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1164                                                 /* fallthru */
1165                                         case 16:
1166                                         case 8:
1167                                                 color_depth = val;
1168                                                 break;
1169
1170                                         case 18:
1171                                                 if (is_lvds()) {
1172                                                         color_depth = val;
1173                                                         break;
1174                                                 }
1175                                                 /* fallthru */
1176                                         default:
1177                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1178                                                         end - vm, vm, color_depth);
1179                                         }
1180                                         bpp_set = 1;
1181                                 } else if (!refresh_set) {
1182                                         refresh = val;
1183                                         refresh_set = 1;
1184                                 }
1185                         }
1186                         vm = end;
1187                 }
1188                 switch (*vm) {
1189                 case '@':
1190                         bpp_set = 1;
1191                         /* fallthru */
1192                 case '-':
1193                         yres_set = 1;
1194                         /* fallthru */
1195                 case 'x':
1196                         xres_set = 1;
1197                         /* fallthru */
1198                 case 'M':
1199                 case 'R':
1200                         vm++;
1201                         break;
1202
1203                 default:
1204                         if (*vm != '\0')
1205                                 vm++;
1206                 }
1207         }
1208         if (p->xres == 0 || p->yres == 0) {
1209                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1210                 lcd_enabled = 0;
1211                 printf("Supported video modes are:");
1212                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1213                         printf(" %s", p->name);
1214                 }
1215                 printf("\n");
1216                 return;
1217         }
1218         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1219                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1220                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1221                 lcd_enabled = 0;
1222                 return;
1223         }
1224         panel_info.vl_col = p->xres;
1225         panel_info.vl_row = p->yres;
1226
1227         switch (color_depth) {
1228         case 8:
1229                 panel_info.vl_bpix = LCD_COLOR8;
1230                 break;
1231         case 16:
1232                 panel_info.vl_bpix = LCD_COLOR16;
1233                 break;
1234         default:
1235                 panel_info.vl_bpix = LCD_COLOR32;
1236         }
1237
1238         p->pixclock = KHZ2PICOS(refresh *
1239                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1240                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1241                                 1000);
1242         debug("Pixel clock set to %lu.%03lu MHz\n",
1243                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1244
1245         if (p != &fb_mode) {
1246                 int ret;
1247
1248                 debug("Creating new display-timing node from '%s'\n",
1249                         video_mode);
1250                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1251                 if (ret)
1252                         printf("Failed to create new display-timing node from '%s': %d\n",
1253                                 video_mode, ret);
1254         }
1255
1256         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1257         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1258                                         ARRAY_SIZE(stk5_lcd_pads));
1259
1260         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1261         switch (lcd_bus_width) {
1262         case 24:
1263                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1264                 break;
1265
1266         case 18:
1267                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1268                 break;
1269
1270         case 16:
1271                 if (!is_lvds()) {
1272                         pix_fmt = IPU_PIX_FMT_RGB565;
1273                         break;
1274                 }
1275                 /* fallthru */
1276         default:
1277                 lcd_enabled = 0;
1278                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1279                         lcd_bus_width);
1280                 return;
1281         }
1282         if (is_lvds()) {
1283                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1284                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1285                 uint32_t gpr2;
1286                 uint32_t gpr3;
1287
1288                 if (lvds_chan_mask == 0) {
1289                         printf("No LVDS channel active\n");
1290                         lcd_enabled = 0;
1291                         return;
1292                 }
1293
1294                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1295                 if (lcd_bus_width == 24)
1296                         gpr2 |= (1 << 5) | (1 << 7);
1297                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1298                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1299                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1300                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1301
1302                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1303                 gpr3 &= ~((3 << 8) | (3 << 6));
1304                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1305         }
1306         if (karo_load_splashimage(0) == 0) {
1307                 int ret;
1308
1309                 debug("Initializing LCD controller\n");
1310                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1311                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1312                                 di_clk_rate, -1);
1313                 if (ret) {
1314                         printf("Failed to initialize FB driver: %d\n", ret);
1315                         lcd_enabled = 0;
1316                 }
1317         } else {
1318                 debug("Skipping initialization of LCD controller\n");
1319         }
1320 }
1321 #else
1322 #define lcd_enabled 0
1323 #endif /* CONFIG_LCD */
1324
1325 static void stk5_board_init(void)
1326 {
1327         int ret;
1328
1329         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1330         if (ret < 0) {
1331                 printf("Failed to request stk5_gpios: %d\n", ret);
1332                 return;
1333         }
1334         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1335 }
1336
1337 static void stk5v3_board_init(void)
1338 {
1339         stk5_board_init();
1340 }
1341
1342 static void stk5v5_board_init(void)
1343 {
1344         int ret;
1345
1346         stk5_board_init();
1347
1348         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1349                         "Flexcan Transceiver");
1350         if (ret) {
1351                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1352                 return;
1353         }
1354
1355         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1356 }
1357
1358 static void tx6qdl_set_cpu_clock(void)
1359 {
1360         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1361
1362         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1363                 return;
1364
1365         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1366                 printf("%s detected; skipping cpu clock change\n",
1367                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1368                 return;
1369         }
1370         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1371                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1372                 printf("CPU clock set to %lu.%03lu MHz\n",
1373                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1374         } else {
1375                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1376         }
1377 }
1378
1379 int board_late_init(void)
1380 {
1381         int ret = 0;
1382         const char *baseboard;
1383
1384         debug("%s@%d: \n", __func__, __LINE__);
1385
1386         env_cleanup();
1387
1388         if (tx6_temp_check_enabled)
1389                 check_cpu_temperature(1);
1390
1391         tx6qdl_set_cpu_clock();
1392
1393         if (had_ctrlc())
1394                 setenv_ulong("safeboot", 1);
1395         else if (wrsr & WRSR_TOUT)
1396                 setenv_ulong("wdreset", 1);
1397         else
1398                 karo_fdt_move_fdt();
1399
1400         baseboard = getenv("baseboard");
1401         if (!baseboard)
1402                 goto exit;
1403
1404         printf("Baseboard: %s\n", baseboard);
1405
1406         if (strncmp(baseboard, "stk5", 4) == 0) {
1407                 if ((strlen(baseboard) == 4) ||
1408                         strcmp(baseboard, "stk5-v3") == 0) {
1409                         stk5v3_board_init();
1410                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1411                         const char *otg_mode = getenv("otg_mode");
1412
1413                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1414                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1415                                         otg_mode, baseboard);
1416                                 setenv("otg_mode", "none");
1417                         }
1418                         stk5v5_board_init();
1419                 } else {
1420                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1421                                 baseboard + 4);
1422                 }
1423         } else {
1424                 printf("WARNING: Unsupported baseboard: '%s'\n",
1425                         baseboard);
1426                 ret = -EINVAL;
1427         }
1428
1429 exit:
1430         tx6_init_mac();
1431
1432         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1433         clear_ctrlc();
1434         return ret;
1435 }
1436
1437 #ifdef CONFIG_SERIAL_TAG
1438 void get_board_serial(struct tag_serialnr *serialnr)
1439 {
1440         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1441         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1442
1443         serialnr->low = readl(&fuse->cfg0);
1444         serialnr->high = readl(&fuse->cfg1);
1445 }
1446 #endif
1447
1448 #if defined(CONFIG_OF_BOARD_SETUP)
1449 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1450 #include <jffs2/jffs2.h>
1451 #include <mtd_node.h>
1452 static struct node_info nodes[] = {
1453         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1454 };
1455 #else
1456 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1457 #endif
1458
1459 static const char *tx6_touchpanels[] = {
1460         "ti,tsc2007",
1461         "edt,edt-ft5x06",
1462         "eeti,egalax_ts",
1463 };
1464
1465 int ft_board_setup(void *blob, bd_t *bd)
1466 {
1467         const char *baseboard = getenv("baseboard");
1468         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1469         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1470         int ret;
1471
1472         ret = fdt_increase_size(blob, 4096);
1473         if (ret) {
1474                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1475                 return ret;
1476         }
1477         if (stk5_v5)
1478                 karo_fdt_enable_node(blob, "stk5led", 0);
1479
1480         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1481
1482         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1483                                 ARRAY_SIZE(tx6_touchpanels));
1484         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1485         karo_fdt_fixup_flexcan(blob, stk5_v5);
1486
1487         karo_fdt_update_fb_mode(blob, video_mode);
1488
1489         return 0;
1490 }
1491 #endif /* CONFIG_OF_BOARD_SETUP */