board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  35 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  36 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  37 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  38
  39 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  40 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  41 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  42
  43 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  44 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
  45 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
  46
  47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  48 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  49 #else
  50 #define TEMPERATURE_MIN                 (-40)
  51 #endif
  52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  53 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  54 #else
  55 #define TEMPERATURE_HOT                 80
  56 #endif
  57
  58 DECLARE_GLOBAL_DATA_PTR;
  59
  60 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  61
  62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  63 #ifdef CONFIG_SECURE_BOOT
  64 char __csf_data[0] __attribute__((section(".__csf_data")));
  65 #endif
  66
  67 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  68         /* RESET_OUT */
  69         MX6_PAD_GPIO_17__GPIO7_IO12,
  70
  71         /* UART pads */
  72 #if CONFIG_MXC_UART_BASE == UART1_BASE
  73         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
  74         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
  75         MX6_PAD_SD3_DAT1__UART1_RTS_B,
  76         MX6_PAD_SD3_DAT0__UART1_CTS_B,
  77 #endif
  78 #if CONFIG_MXC_UART_BASE == UART2_BASE
  79         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
  80         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
  81         MX6_PAD_SD4_DAT5__UART2_RTS_B,
  82         MX6_PAD_SD4_DAT6__UART2_CTS_B,
  83 #endif
  84 #if CONFIG_MXC_UART_BASE == UART3_BASE
  85         MX6_PAD_EIM_D24__UART3_TX_DATA,
  86         MX6_PAD_EIM_D25__UART3_RX_DATA,
  87         MX6_PAD_SD3_RST__UART3_RTS_B,
  88         MX6_PAD_SD3_DAT3__UART3_CTS_B,
  89 #endif
  90         /* internal I2C */
  91         MX6_PAD_EIM_D28__I2C1_SDA,
  92         MX6_PAD_EIM_D21__I2C1_SCL,
  93
  94         /* FEC PHY GPIO functions */
  95         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
  96         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
  97         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
  98 };
  99
 100 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 101         /* FEC functions */
 102         MX6_PAD_ENET_MDC__ENET_MDC,
 103         MX6_PAD_ENET_MDIO__ENET_MDIO,
 104         MX6_PAD_GPIO_16__ENET_REF_CLK,
 105         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 106         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 107         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
 108         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
 109         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 110         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
 111         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 112 };
 113
 114 #define TX6_I2C_GPIO_PAD_CTRL   (PAD_CTL_PUS_22K_UP |   \
 115                                 PAD_CTL_SPEED_MED |     \
 116                                 PAD_CTL_DSE_34ohm |     \
 117                                 PAD_CTL_SRE_FAST)
 118
 119 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 120         /* internal I2C */
 121         MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
 122         MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
 123 };
 124
 125 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
 126         /* internal I2C */
 127         MX6_PAD_EIM_D28__I2C1_SDA,
 128         MX6_PAD_EIM_D21__I2C1_SCL,
 129 };
 130
 131 static const struct gpio const tx6qdl_gpios[] = {
 132         /* These two entries are used to forcefully reinitialize the I2C bus */
 133         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 134         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 135
 136         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 137         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 138         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 139         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 140 };
 141
 142 static int pmic_addr __data;
 143
 144 #if defined(CONFIG_SOC_MX6Q)
 145 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
 146 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
 147 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
 148 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
 149 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
 150 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
 151 #define I2C1_SEL_INPUT_VAL                      0
 152 #endif
 153 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 154 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
 155 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
 156 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
 157 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
 158 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
 159 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
 160 #define I2C1_SEL_INPUT_VAL                      1
 161 #endif
 162
 163 #define GPIO_DR 0
 164 #define GPIO_DIR 4
 165 #define GPIO_PSR 8
 166
 167 static void tx6_i2c_recover(void)
 168 {
 169         int i;
 170         int bad = 0;
 171 #define SCL_BIT         (1 << (TX6_I2C1_SCL_GPIO % 32))
 172 #define SDA_BIT         (1 << (TX6_I2C1_SDA_GPIO % 32))
 173
 174         if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
 175                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
 176                 return;
 177
 178         debug("Clearing I2C bus\n");
 179         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
 180                 printf("I2C SCL stuck LOW\n");
 181                 bad++;
 182
 183                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
 184                         GPIO3_BASE_ADDR + GPIO_DR);
 185                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
 186                         GPIO3_BASE_ADDR + GPIO_DIR);
 187         }
 188         if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
 189                 printf("I2C SDA stuck LOW\n");
 190                 bad++;
 191
 192                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
 193                         GPIO3_BASE_ADDR + GPIO_DIR);
 194                 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
 195                         GPIO3_BASE_ADDR + GPIO_DR);
 196                 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
 197                         GPIO3_BASE_ADDR + GPIO_DIR);
 198
 199                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 200                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
 201                 udelay(10);
 202
 203                 for (i = 0; i < 18; i++) {
 204                         u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
 205
 206                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 207                         writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
 208                         udelay(10);
 209                         if (reg & SCL_BIT &&
 210                                 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
 211                                 break;
 212                 }
 213         }
 214         if (bad) {
 215                 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
 216
 217                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
 218                         printf("I2C bus recovery succeeded\n");
 219                 } else {
 220                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
 221                                 SCL_BIT | SDA_BIT);
 222                 }
 223         }
 224         debug("Setting up I2C Pads\n");
 225         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
 226                                         ARRAY_SIZE(tx6_i2c_pads));
 227 }
 228
 229 /* placed in section '.data' to prevent overwriting relocation info
 230  * overlayed with bss
 231  */
 232 static u32 wrsr __data;
 233
 234 #define WRSR_POR                        (1 << 4)
 235 #define WRSR_TOUT                       (1 << 1)
 236 #define WRSR_SFTW                       (1 << 0)
 237
 238 static void print_reset_cause(void)
 239 {
 240         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 241         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 242         u32 srsr;
 243         char *dlm = "";
 244
 245         printf("Reset cause: ");
 246
 247         srsr = readl(&src_regs->srsr);
 248         wrsr = readw(wdt_base + 4);
 249
 250         if (wrsr & WRSR_POR) {
 251                 printf("%sPOR", dlm);
 252                 dlm = " | ";
 253         }
 254         if (srsr & 0x00004) {
 255                 printf("%sCSU", dlm);
 256                 dlm = " | ";
 257         }
 258         if (srsr & 0x00008) {
 259                 printf("%sIPP USER", dlm);
 260                 dlm = " | ";
 261         }
 262         if (srsr & 0x00010) {
 263                 if (wrsr & WRSR_SFTW) {
 264                         printf("%sSOFT", dlm);
 265                         dlm = " | ";
 266                 }
 267                 if (wrsr & WRSR_TOUT) {
 268                         printf("%sWDOG", dlm);
 269                         dlm = " | ";
 270                 }
 271         }
 272         if (srsr & 0x00020) {
 273                 printf("%sJTAG HIGH-Z", dlm);
 274                 dlm = " | ";
 275         }
 276         if (srsr & 0x00040) {
 277                 printf("%sJTAG SW", dlm);
 278                 dlm = " | ";
 279         }
 280         if (srsr & 0x10000) {
 281                 printf("%sWARM BOOT", dlm);
 282                 dlm = " | ";
 283         }
 284         if (dlm[0] == '\0')
 285                 printf("unknown");
 286
 287         printf("\n");
 288 }
 289
 290 static const char __data *tx6_mod_suffix;
 291
 292 #ifdef CONFIG_IMX6_THERMAL
 293 #include <thermal.h>
 294 #include <imx_thermal.h>
 295 #include <fuse.h>
 296
 297 static void print_temperature(void)
 298 {
 299         struct udevice *thermal_dev;
 300         int cpu_tmp, minc, maxc, ret;
 301         char const *grade_str;
 302         static u32 __data thermal_calib;
 303
 304         puts("Temperature: ");
 305         switch (get_cpu_temp_grade(&minc, &maxc)) {
 306         case TEMP_AUTOMOTIVE:
 307                 grade_str = "Automotive";
 308                 break;
 309         case TEMP_INDUSTRIAL:
 310                 grade_str = "Industrial";
 311                 break;
 312         case TEMP_EXTCOMMERCIAL:
 313                 grade_str = "Extended Commercial";
 314                 break;
 315         default:
 316                 grade_str = "Commercial";
 317         }
 318         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 319         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 320         if (ret == 0) {
 321                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 322
 323                 if (ret == 0)
 324                         printf(" at %dC", cpu_tmp);
 325                 else
 326                         puts(" - failed to read sensor data");
 327         } else {
 328                 puts(" - no sensor device found");
 329         }
 330
 331         if (fuse_read(1, 6, &thermal_calib) == 0) {
 332                 printf(" - calibration data 0x%08x\n", thermal_calib);
 333         } else {
 334                 puts(" - Failed to read thermal calib fuse\n");
 335         }
 336 }
 337 #else
 338 static inline void print_temperature(void)
 339 {
 340 }
 341 #endif
 342
 343 int checkboard(void)
 344 {
 345         u32 cpurev = get_cpu_rev();
 346         char *cpu_str = "?";
 347
 348         if (is_cpu_type(MXC_CPU_MX6SL)) {
 349                 cpu_str = "SL";
 350                 tx6_mod_suffix = "?";
 351         } else if (is_cpu_type(MXC_CPU_MX6DL)) {
 352                 cpu_str = "DL";
 353                 tx6_mod_suffix = "U";
 354         } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 355                 cpu_str = "SOLO";
 356                 tx6_mod_suffix = "S";
 357         } else if (is_cpu_type(MXC_CPU_MX6Q)) {
 358                 cpu_str = "Q";
 359                 tx6_mod_suffix = "Q";
 360         } else if (is_cpu_type(MXC_CPU_MX6QP)) {
 361                 cpu_str = "QP";
 362                 tx6_mod_suffix = "QP";
 363         }
 364
 365         printf("CPU:         Freescale i.MX6%s rev%d.%d at %d MHz\n",
 366                 cpu_str,
 367                 (cpurev & 0x000F0) >> 4,
 368                 (cpurev & 0x0000F) >> 0,
 369                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 370
 371         print_temperature();
 372         print_reset_cause();
 373 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 374         check_cpu_temperature(1);
 375 #endif
 376         tx6_i2c_recover();
 377         return 0;
 378 }
 379
 380 /* serial port not initialized at this point */
 381 int board_early_init_f(void)
 382 {
 383         return 0;
 384 }
 385
 386 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 387 static bool tx6_temp_check_enabled = true;
 388 #else
 389 #define tx6_temp_check_enabled  0
 390 #endif
 391
 392 #ifdef CONFIG_TX6_NAND
 393 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
 394 #else
 395 #ifdef CONFIG_MMC_BOOT_SIZE
 396 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
 397 #else
 398 #define TX6_FLASH_SZ    2
 399 #endif
 400 #endif /* CONFIG_TX6_NAND */
 401
 402 #define TX6_DDR_SZ      (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
 403
 404 static char tx6_mem_table[] = {
 405         '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
 406         '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
 407         '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
 408         '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
 409         '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
 410         '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
 411         '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
 412         '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
 413         '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
 414         '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
 415         '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
 416 #if defined(CONFIG_TX6_REV) && CONFIG_TX6_REV == 2
 417         '0', /* TX6Q-1020 (legacy) 1GiB SDRAM 64bit; 8GiB eMMC */
 418 #else
 419         '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
 420 #endif
 421 };
 422
 423 static struct {
 424         uchar addr;
 425         uchar rev;
 426 } tx6_mod_revs[] = {
 427         { 0x3c, 1, },
 428         { 0x32, 2, },
 429         { 0x33, 3, },
 430 };
 431
 432 static inline char tx6_mem_suffix(void)
 433 {
 434         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
 435
 436         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
 437                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
 438
 439         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
 440                 return '?';
 441         if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
 442                 return '7';
 443         if (mem_idx == 8)
 444                 return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
 445         return tx6_mem_table[mem_idx];
 446 };
 447
 448 static int tx6_get_mod_rev(unsigned int pmic_id)
 449 {
 450         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
 451                 return tx6_mod_revs[pmic_id].rev;
 452
 453         return 0;
 454 }
 455
 456 static int tx6_pmic_probe(void)
 457 {
 458         int i;
 459
 460         debug("%s@%d: \n", __func__, __LINE__);
 461
 462         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
 463                 u8 i2c_addr = tx6_mod_revs[i].addr;
 464                 int ret = i2c_probe(i2c_addr);
 465
 466                 if (ret == 0) {
 467                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
 468                         return i;
 469                 }
 470                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
 471         }
 472         return -EINVAL;
 473 }
 474
 475 int board_init(void)
 476 {
 477         int ret;
 478         int pmic_id;
 479
 480         debug("%s@%d: \n", __func__, __LINE__);
 481
 482         pmic_id = tx6_pmic_probe();
 483         if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
 484                 pmic_addr = tx6_mod_revs[pmic_id].addr;
 485
 486         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
 487                 tx6_mod_suffix,
 488                 is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
 489                 is_lvds(), tx6_get_mod_rev(pmic_id),
 490                 tx6_mem_suffix());
 491
 492         get_hab_status();
 493
 494         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 495         if (ret < 0) {
 496                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
 497         }
 498         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 499
 500         /* Address of boot parameters */
 501         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 502         gd->bd->bi_arch_number = -1;
 503
 504         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 505                 if (wrsr & WRSR_TOUT)
 506                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 507                 else
 508                         printf("<CTRL-C> detected; safeboot enabled\n");
 509 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 510                 tx6_temp_check_enabled = false;
 511 #endif
 512                 return 0;
 513         }
 514
 515         ret = tx6_pmic_init(pmic_addr, NULL, 0);
 516         if (ret) {
 517                 printf("Failed to setup PMIC voltages: %d\n", ret);
 518                 hang();
 519         }
 520         return 0;
 521 }
 522
 523 int dram_init(void)
 524 {
 525         debug("%s@%d: \n", __func__, __LINE__);
 526
 527         /* dram_init must store complete ramsize in gd->ram_size */
 528         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 529                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 530         return 0;
 531 }
 532
 533 void dram_init_banksize(void)
 534 {
 535         debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
 536                 CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
 537         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 538         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 539                         PHYS_SDRAM_1_SIZE);
 540 #if CONFIG_NR_DRAM_BANKS > 1
 541         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 542         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 543                         PHYS_SDRAM_2_SIZE);
 544 #endif
 545 }
 546
 547 #ifdef  CONFIG_FSL_ESDHC
 548 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
 549         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
 550         PAD_CTL_SRE_FAST)
 551
 552 static const iomux_v3_cfg_t mmc0_pads[] = {
 553         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 554         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 555         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 556         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 557         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 558         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 559         /* SD1 CD */
 560         MX6_PAD_SD3_CMD__GPIO7_IO02,
 561 };
 562
 563 static const iomux_v3_cfg_t mmc1_pads[] = {
 564         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 565         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 566         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 567         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 568         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 569         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 570         /* SD2 CD */
 571         MX6_PAD_SD3_CLK__GPIO7_IO03,
 572 };
 573
 574 #ifdef CONFIG_TX6_EMMC
 575 static const iomux_v3_cfg_t mmc3_pads[] = {
 576         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 577         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 578         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 579         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 580         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 581         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 582         /* eMMC RESET */
 583         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 584                                                 PAD_CTL_DSE_40ohm),
 585 };
 586 #endif
 587
 588 static struct tx6_esdhc_cfg {
 589         const iomux_v3_cfg_t *pads;
 590         int num_pads;
 591         enum mxc_clock clkid;
 592         struct fsl_esdhc_cfg cfg;
 593         int cd_gpio;
 594 } tx6qdl_esdhc_cfg[] = {
 595 #ifdef CONFIG_TX6_EMMC
 596         {
 597                 .pads = mmc3_pads,
 598                 .num_pads = ARRAY_SIZE(mmc3_pads),
 599                 .clkid = MXC_ESDHC4_CLK,
 600                 .cfg = {
 601                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 602                         .max_bus_width = 4,
 603                 },
 604                 .cd_gpio = -EINVAL,
 605         },
 606 #endif
 607         {
 608                 .pads = mmc0_pads,
 609                 .num_pads = ARRAY_SIZE(mmc0_pads),
 610                 .clkid = MXC_ESDHC_CLK,
 611                 .cfg = {
 612                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 613                         .max_bus_width = 4,
 614                 },
 615                 .cd_gpio = IMX_GPIO_NR(7, 2),
 616         },
 617         {
 618                 .pads = mmc1_pads,
 619                 .num_pads = ARRAY_SIZE(mmc1_pads),
 620                 .clkid = MXC_ESDHC2_CLK,
 621                 .cfg = {
 622                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 623                         .max_bus_width = 4,
 624                 },
 625                 .cd_gpio = IMX_GPIO_NR(7, 3),
 626         },
 627 };
 628
 629 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 630 {
 631         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 632 }
 633
 634 int board_mmc_getcd(struct mmc *mmc)
 635 {
 636         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 637
 638         if (cfg->cd_gpio < 0)
 639                 return 1;
 640
 641         debug("SD card %d is %spresent (GPIO %d)\n",
 642                 cfg - tx6qdl_esdhc_cfg,
 643                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 644                 cfg->cd_gpio);
 645         return !gpio_get_value(cfg->cd_gpio);
 646 }
 647
 648 int board_mmc_init(bd_t *bis)
 649 {
 650         int i;
 651
 652         debug("%s@%d: \n", __func__, __LINE__);
 653
 654         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 655                 struct mmc *mmc;
 656                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 657                 int ret;
 658
 659                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 660                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 661
 662                 if (cfg->cd_gpio >= 0) {
 663                         ret = gpio_request_one(cfg->cd_gpio,
 664                                         GPIOFLAG_INPUT, "MMC CD");
 665                         if (ret) {
 666                                 printf("Error %d requesting GPIO%d_%d\n",
 667                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 668                                 continue;
 669                         }
 670                 }
 671
 672                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 673                 fsl_esdhc_initialize(bis, &cfg->cfg);
 674
 675                 mmc = find_mmc_device(i);
 676                 if (mmc == NULL)
 677                         continue;
 678                 if (board_mmc_getcd(mmc))
 679                         mmc_init(mmc);
 680         }
 681         return 0;
 682 }
 683 #endif /* CONFIG_CMD_MMC */
 684
 685 #ifdef CONFIG_FEC_MXC
 686
 687 #ifndef ETH_ALEN
 688 #define ETH_ALEN 6
 689 #endif
 690
 691 int board_eth_init(bd_t *bis)
 692 {
 693         int ret;
 694
 695         debug("%s@%d: \n", __func__, __LINE__);
 696
 697         /* delay at least 21ms for the PHY internal POR signal to deassert */
 698         udelay(22000);
 699
 700         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 701                                         ARRAY_SIZE(tx6qdl_fec_pads));
 702
 703         /* Deassert RESET to the external phy */
 704         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 705
 706         ret = cpu_eth_init(bis);
 707         if (ret)
 708                 printf("cpu_eth_init() failed: %d\n", ret);
 709
 710         return ret;
 711 }
 712
 713 static void tx6_init_mac(void)
 714 {
 715         u8 mac[ETH_ALEN];
 716
 717         imx_get_mac_from_fuse(0, mac);
 718         if (!is_valid_ethaddr(mac)) {
 719                 printf("No valid MAC address programmed\n");
 720                 return;
 721         }
 722
 723         printf("MAC addr from fuse: %pM\n", mac);
 724         eth_setenv_enetaddr("ethaddr", mac);
 725 }
 726 #else
 727 static inline void tx6_init_mac(void)
 728 {
 729 }
 730 #endif /* CONFIG_FEC_MXC */
 731
 732 enum {
 733         LED_STATE_INIT = -1,
 734         LED_STATE_OFF,
 735         LED_STATE_ON,
 736 };
 737
 738 static inline int calc_blink_rate(void)
 739 {
 740         if (!tx6_temp_check_enabled)
 741                 return CONFIG_SYS_HZ;
 742
 743         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 744                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 745                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 746 }
 747
 748 void show_activity(int arg)
 749 {
 750         static int led_state = LED_STATE_INIT;
 751         static int blink_rate;
 752         static ulong last;
 753
 754         if (led_state == LED_STATE_INIT) {
 755                 last = get_timer(0);
 756                 gpio_set_value(TX6_LED_GPIO, 1);
 757                 led_state = LED_STATE_ON;
 758                 blink_rate = calc_blink_rate();
 759         } else {
 760                 if (get_timer(last) > blink_rate) {
 761                         blink_rate = calc_blink_rate();
 762                         last = get_timer_masked();
 763                         if (led_state == LED_STATE_ON) {
 764                                 gpio_set_value(TX6_LED_GPIO, 0);
 765                         } else {
 766                                 gpio_set_value(TX6_LED_GPIO, 1);
 767                         }
 768                         led_state = 1 - led_state;
 769                 }
 770         }
 771 }
 772
 773 static const iomux_v3_cfg_t stk5_pads[] = {
 774         /* SW controlled LED on STK5 baseboard */
 775         MX6_PAD_EIM_A18__GPIO2_IO20,
 776
 777         /* I2C bus on DIMM pins 40/41 */
 778         MX6_PAD_GPIO_6__I2C3_SDA,
 779         MX6_PAD_GPIO_3__I2C3_SCL,
 780
 781         /* TSC200x PEN IRQ */
 782         MX6_PAD_EIM_D26__GPIO3_IO26,
 783
 784         /* EDT-FT5x06 Polytouch panel */
 785         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
 786         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
 787         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
 788
 789         /* USBH1 */
 790         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
 791         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
 792         /* USBOTG */
 793         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
 794         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
 795         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
 796 };
 797
 798 static const struct gpio stk5_gpios[] = {
 799         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 800
 801         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 802         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 803         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 804         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 805         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 806 };
 807
 808 #ifdef CONFIG_LCD
 809 vidinfo_t panel_info = {
 810         /* set to max. size supported by SoC */
 811         .vl_col = 1920,
 812         .vl_row = 1080,
 813
 814         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 815 };
 816
 817 static struct fb_videomode tx6_fb_modes[] = {
 818 #ifndef CONFIG_SYS_LVDS_IF
 819         {
 820                 /* Standard VGA timing */
 821                 .name           = "VGA",
 822                 .refresh        = 60,
 823                 .xres           = 640,
 824                 .yres           = 480,
 825                 .pixclock       = KHZ2PICOS(25175),
 826                 .left_margin    = 48,
 827                 .hsync_len      = 96,
 828                 .right_margin   = 16,
 829                 .upper_margin   = 31,
 830                 .vsync_len      = 2,
 831                 .lower_margin   = 12,
 832                 .sync           = FB_SYNC_CLK_LAT_FALL,
 833         },
 834         {
 835                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 836                  * DE high active, 115.2 mm x 86.4 mm display area
 837                  * VGA compatible timing
 838                  */
 839                 .name           = "ETV570",
 840                 .refresh        = 60,
 841                 .xres           = 640,
 842                 .yres           = 480,
 843                 .pixclock       = KHZ2PICOS(25175),
 844                 .left_margin    = 114,
 845                 .hsync_len      = 30,
 846                 .right_margin   = 16,
 847                 .upper_margin   = 32,
 848                 .vsync_len      = 3,
 849                 .lower_margin   = 10,
 850                 .sync           = FB_SYNC_CLK_LAT_FALL,
 851         },
 852         {
 853                 /* Emerging ET0350G0DH6 320 x 240 display.
 854                  * 70.08 mm x 52.56 mm display area.
 855                  */
 856                 .name           = "ET0350",
 857                 .refresh        = 60,
 858                 .xres           = 320,
 859                 .yres           = 240,
 860                 .pixclock       = KHZ2PICOS(6500),
 861                 .left_margin    = 68 - 34,
 862                 .hsync_len      = 34,
 863                 .right_margin   = 20,
 864                 .upper_margin   = 18 - 3,
 865                 .vsync_len      = 3,
 866                 .lower_margin   = 4,
 867                 .sync           = FB_SYNC_CLK_LAT_FALL,
 868         },
 869         {
 870                 /* Emerging ET0430G0DH6 480 x 272 display.
 871                  * 95.04 mm x 53.856 mm display area.
 872                  */
 873                 .name           = "ET0430",
 874                 .refresh        = 60,
 875                 .xres           = 480,
 876                 .yres           = 272,
 877                 .pixclock       = KHZ2PICOS(9000),
 878                 .left_margin    = 2,
 879                 .hsync_len      = 41,
 880                 .right_margin   = 2,
 881                 .upper_margin   = 2,
 882                 .vsync_len      = 10,
 883                 .lower_margin   = 2,
 884         },
 885         {
 886                 /* Emerging ET0500G0DH6 800 x 480 display.
 887                  * 109.6 mm x 66.4 mm display area.
 888                  */
 889                 .name           = "ET0500",
 890                 .refresh        = 60,
 891                 .xres           = 800,
 892                 .yres           = 480,
 893                 .pixclock       = KHZ2PICOS(33260),
 894                 .left_margin    = 216 - 128,
 895                 .hsync_len      = 128,
 896                 .right_margin   = 1056 - 800 - 216,
 897                 .upper_margin   = 35 - 2,
 898                 .vsync_len      = 2,
 899                 .lower_margin   = 525 - 480 - 35,
 900                 .sync           = FB_SYNC_CLK_LAT_FALL,
 901         },
 902         {
 903                 /* Emerging ETQ570G0DH6 320 x 240 display.
 904                  * 115.2 mm x 86.4 mm display area.
 905                  */
 906                 .name           = "ETQ570",
 907                 .refresh        = 60,
 908                 .xres           = 320,
 909                 .yres           = 240,
 910                 .pixclock       = KHZ2PICOS(6400),
 911                 .left_margin    = 38,
 912                 .hsync_len      = 30,
 913                 .right_margin   = 30,
 914                 .upper_margin   = 16, /* 15 according to datasheet */
 915                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 916                 .lower_margin   = 4, /* 4.5 according to datasheet */
 917                 .sync           = FB_SYNC_CLK_LAT_FALL,
 918         },
 919         {
 920                 /* Emerging ET0700G0DH6 800 x 480 display.
 921                  * 152.4 mm x 91.44 mm display area.
 922                  */
 923                 .name           = "ET0700",
 924                 .refresh        = 60,
 925                 .xres           = 800,
 926                 .yres           = 480,
 927                 .pixclock       = KHZ2PICOS(33260),
 928                 .left_margin    = 216 - 128,
 929                 .hsync_len      = 128,
 930                 .right_margin   = 1056 - 800 - 216,
 931                 .upper_margin   = 35 - 2,
 932                 .vsync_len      = 2,
 933                 .lower_margin   = 525 - 480 - 35,
 934                 .sync           = FB_SYNC_CLK_LAT_FALL,
 935         },
 936         {
 937                 /* Emerging ET070001DM6 800 x 480 display.
 938                  * 152.4 mm x 91.44 mm display area.
 939                  */
 940                 .name           = "ET070001DM6",
 941                 .refresh        = 60,
 942                 .xres           = 800,
 943                 .yres           = 480,
 944                 .pixclock       = KHZ2PICOS(33260),
 945                 .left_margin    = 216 - 128,
 946                 .hsync_len      = 128,
 947                 .right_margin   = 1056 - 800 - 216,
 948                 .upper_margin   = 35 - 2,
 949                 .vsync_len      = 2,
 950                 .lower_margin   = 525 - 480 - 35,
 951                 .sync           = 0,
 952         },
 953 #else
 954         {
 955                 /* HannStar HSD100PXN1
 956                  * 202.7m mm x 152.06 mm display area.
 957                  */
 958                 .name           = "HSD100PXN1",
 959                 .refresh        = 60,
 960                 .xres           = 1024,
 961                 .yres           = 768,
 962                 .pixclock       = KHZ2PICOS(65000),
 963                 .left_margin    = 0,
 964                 .hsync_len      = 0,
 965                 .right_margin   = 320,
 966                 .upper_margin   = 0,
 967                 .vsync_len      = 0,
 968                 .lower_margin   = 38,
 969                 .sync           = FB_SYNC_CLK_LAT_FALL,
 970         },
 971 #endif
 972         {
 973                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 974                 .refresh        = 60,
 975                 .left_margin    = 48,
 976                 .hsync_len      = 96,
 977                 .right_margin   = 16,
 978                 .upper_margin   = 31,
 979                 .vsync_len      = 2,
 980                 .lower_margin   = 12,
 981                 .sync           = FB_SYNC_CLK_LAT_FALL,
 982         },
 983 };
 984
 985 static int lcd_enabled = 1;
 986 static int lcd_bl_polarity;
 987
 988 static int lcd_backlight_polarity(void)
 989 {
 990         return lcd_bl_polarity;
 991 }
 992
 993 void lcd_enable(void)
 994 {
 995         /* HACK ALERT:
 996          * global variable from common/lcd.c
 997          * Set to 0 here to prevent messages from going to LCD
 998          * rather than serial console
 999          */
1000         lcd_is_enabled = 0;
1001
1002         if (lcd_enabled) {
1003                 karo_load_splashimage(1);
1004
1005                 debug("Switching LCD on\n");
1006                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1007                 udelay(100);
1008                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1009                 udelay(300000);
1010                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1011                         lcd_backlight_polarity());
1012         }
1013 }
1014
1015 void lcd_disable(void)
1016 {
1017         if (lcd_enabled) {
1018                 printf("Disabling LCD\n");
1019                 ipuv3_fb_shutdown();
1020         }
1021 }
1022
1023 void lcd_panel_disable(void)
1024 {
1025         if (lcd_enabled) {
1026                 debug("Switching LCD off\n");
1027                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1028                         !lcd_backlight_polarity());
1029                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1030                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1031         }
1032 }
1033
1034 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1035         /* LCD RESET */
1036         MX6_PAD_EIM_D29__GPIO3_IO29,
1037         /* LCD POWER_ENABLE */
1038         MX6_PAD_EIM_EB3__GPIO2_IO31,
1039         /* LCD Backlight (PWM) */
1040         MX6_PAD_GPIO_1__GPIO1_IO01,
1041
1042 #ifndef CONFIG_SYS_LVDS_IF
1043         /* Display */
1044         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
1045         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
1046         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
1047         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
1048         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
1049         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
1050         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
1051         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
1052         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
1053         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
1054         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
1055         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
1056         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
1057         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
1058         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
1059         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
1060         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
1061         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
1062         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
1063         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
1064         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
1065         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
1066         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
1067         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
1068         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
1069         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
1070         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
1071         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
1072 #endif
1073 };
1074
1075 static const struct gpio stk5_lcd_gpios[] = {
1076         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1077         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1078         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1079 };
1080
1081 void lcd_ctrl_init(void *lcdbase)
1082 {
1083         int color_depth = 24;
1084         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1085         const char *vm;
1086         unsigned long val;
1087         int refresh = 60;
1088         struct fb_videomode *p = &tx6_fb_modes[0];
1089         struct fb_videomode fb_mode;
1090         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1091         int pix_fmt;
1092         int lcd_bus_width;
1093         unsigned long di_clk_rate = 65000000;
1094
1095         if (!lcd_enabled) {
1096                 debug("LCD disabled\n");
1097                 goto disable;
1098                 return;
1099         }
1100
1101         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1102                 debug("Disabling LCD\n");
1103                 lcd_enabled = 0;
1104                 setenv("splashimage", NULL);
1105                 goto disable;
1106                 return;
1107         }
1108
1109         karo_fdt_move_fdt();
1110         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1111
1112         if (video_mode == NULL) {
1113                 debug("Disabling LCD\n");
1114                 lcd_enabled = 0;
1115                 goto disable;
1116                 return;
1117         }
1118         vm = video_mode;
1119         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1120                 p = &fb_mode;
1121                 debug("Using video mode from FDT\n");
1122                 vm += strlen(vm);
1123                 if (fb_mode.xres > panel_info.vl_col ||
1124                         fb_mode.yres > panel_info.vl_row) {
1125                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1126                                 fb_mode.xres, fb_mode.yres,
1127                                 panel_info.vl_col, panel_info.vl_row);
1128                         lcd_enabled = 0;
1129                         goto disable;
1130                         return;
1131                 }
1132         }
1133         if (p->name != NULL)
1134                 debug("Trying compiled-in video modes\n");
1135         while (p->name != NULL) {
1136                 if (strcmp(p->name, vm) == 0) {
1137                         debug("Using video mode: '%s'\n", p->name);
1138                         vm += strlen(vm);
1139                         break;
1140                 }
1141                 p++;
1142         }
1143         if (*vm != '\0')
1144                 debug("Trying to decode video_mode: '%s'\n", vm);
1145         while (*vm != '\0') {
1146                 if (*vm >= '0' && *vm <= '9') {
1147                         char *end;
1148
1149                         val = simple_strtoul(vm, &end, 0);
1150                         if (end > vm) {
1151                                 if (!xres_set) {
1152                                         if (val > panel_info.vl_col)
1153                                                 val = panel_info.vl_col;
1154                                         p->xres = val;
1155                                         panel_info.vl_col = val;
1156                                         xres_set = 1;
1157                                 } else if (!yres_set) {
1158                                         if (val > panel_info.vl_row)
1159                                                 val = panel_info.vl_row;
1160                                         p->yres = val;
1161                                         panel_info.vl_row = val;
1162                                         yres_set = 1;
1163                                 } else if (!bpp_set) {
1164                                         switch (val) {
1165                                         case 32:
1166                                         case 24:
1167                                                 if (is_lvds())
1168                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1169                                                 /* fallthru */
1170                                         case 16:
1171                                         case 8:
1172                                                 color_depth = val;
1173                                                 break;
1174
1175                                         case 18:
1176                                                 if (is_lvds()) {
1177                                                         color_depth = val;
1178                                                         break;
1179                                                 }
1180                                                 /* fallthru */
1181                                         default:
1182                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1183                                                         end - vm, vm, color_depth);
1184                                         }
1185                                         bpp_set = 1;
1186                                 } else if (!refresh_set) {
1187                                         refresh = val;
1188                                         refresh_set = 1;
1189                                 }
1190                         }
1191                         vm = end;
1192                 }
1193                 switch (*vm) {
1194                 case '@':
1195                         bpp_set = 1;
1196                         /* fallthru */
1197                 case '-':
1198                         yres_set = 1;
1199                         /* fallthru */
1200                 case 'x':
1201                         xres_set = 1;
1202                         /* fallthru */
1203                 case 'M':
1204                 case 'R':
1205                         vm++;
1206                         break;
1207
1208                 default:
1209                         if (*vm != '\0')
1210                                 vm++;
1211                 }
1212         }
1213         if (p->xres == 0 || p->yres == 0) {
1214                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1215                 lcd_enabled = 0;
1216                 printf("Supported video modes are:");
1217                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1218                         printf(" %s", p->name);
1219                 }
1220                 printf("\n");
1221                 goto disable;
1222                 return;
1223         }
1224         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1225                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1226                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1227                 lcd_enabled = 0;
1228                 goto disable;
1229                 return;
1230         }
1231         panel_info.vl_col = p->xres;
1232         panel_info.vl_row = p->yres;
1233
1234         switch (color_depth) {
1235         case 8:
1236                 panel_info.vl_bpix = LCD_COLOR8;
1237                 break;
1238         case 16:
1239                 panel_info.vl_bpix = LCD_COLOR16;
1240                 break;
1241         default:
1242                 panel_info.vl_bpix = LCD_COLOR32;
1243         }
1244
1245         p->pixclock = KHZ2PICOS(refresh *
1246                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1247                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1248                                 1000);
1249         debug("Pixel clock set to %lu.%03lu MHz\n",
1250                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1251
1252         if (p != &fb_mode) {
1253                 int ret;
1254
1255                 debug("Creating new display-timing node from '%s'\n",
1256                         video_mode);
1257                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1258                 if (ret)
1259                         printf("Failed to create new display-timing node from '%s': %d\n",
1260                                 video_mode, ret);
1261         }
1262
1263         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1264         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1265                                         ARRAY_SIZE(stk5_lcd_pads));
1266
1267         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1268         switch (lcd_bus_width) {
1269         case 24:
1270                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1271                 break;
1272
1273         case 18:
1274                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1275                 break;
1276
1277         case 16:
1278                 if (!is_lvds()) {
1279                         pix_fmt = IPU_PIX_FMT_RGB565;
1280                         break;
1281                 }
1282                 /* fallthru */
1283         default:
1284                 lcd_enabled = 0;
1285                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1286                         lcd_bus_width);
1287                 goto disable;
1288                 return;
1289         }
1290         if (is_lvds()) {
1291                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1292                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1293                 uint32_t gpr2;
1294                 uint32_t gpr3;
1295
1296                 if (lvds_chan_mask == 0) {
1297                         printf("No LVDS channel active\n");
1298                         lcd_enabled = 0;
1299                         goto disable;
1300                         return;
1301                 }
1302
1303                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1304                 if (lcd_bus_width == 24)
1305                         gpr2 |= (1 << 5) | (1 << 7);
1306                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1307                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1308                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1309                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1310
1311                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1312                 gpr3 &= ~((3 << 8) | (3 << 6));
1313                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1314         }
1315         if (karo_load_splashimage(0) == 0) {
1316                 int ret;
1317
1318                 debug("Initializing LCD controller\n");
1319                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1320                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1321                                 di_clk_rate, -1);
1322                 if (ret) {
1323                         printf("Failed to initialize FB driver: %d\n", ret);
1324                         lcd_enabled = 0;
1325                 }
1326         } else {
1327                 debug("Skipping initialization of LCD controller\n");
1328         }
1329         return;
1330
1331 disable:
1332         lcd_enabled = 0;
1333         panel_info.vl_col = 0;
1334         panel_info.vl_row = 0;
1335
1336 }
1337 #else
1338 #define lcd_enabled 0
1339 #endif /* CONFIG_LCD */
1340
1341 static void stk5_board_init(void)
1342 {
1343         int ret;
1344
1345         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1346         if (ret < 0) {
1347                 printf("Failed to request stk5_gpios: %d\n", ret);
1348                 return;
1349         }
1350         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1351 }
1352
1353 static void stk5v3_board_init(void)
1354 {
1355         stk5_board_init();
1356 }
1357
1358 static void stk5v5_board_init(void)
1359 {
1360         int ret;
1361
1362         stk5_board_init();
1363
1364         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1365                         "Flexcan Transceiver");
1366         if (ret) {
1367                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1368                 return;
1369         }
1370
1371         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1372 }
1373
1374 static void tx6qdl_set_cpu_clock(void)
1375 {
1376         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1377
1378         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1379                 return;
1380
1381         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1382                 printf("%s detected; skipping cpu clock change\n",
1383                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1384                 return;
1385         }
1386         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1387                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1388                 printf("CPU clock set to %lu.%03lu MHz\n",
1389                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1390         } else {
1391                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1392         }
1393 }
1394
1395 int board_late_init(void)
1396 {
1397         const char *baseboard;
1398
1399         debug("%s@%d: \n", __func__, __LINE__);
1400
1401         env_cleanup();
1402
1403         if (tx6_temp_check_enabled)
1404                 check_cpu_temperature(1);
1405
1406         tx6qdl_set_cpu_clock();
1407
1408         if (had_ctrlc())
1409                 setenv_ulong("safeboot", 1);
1410         else if (wrsr & WRSR_TOUT)
1411                 setenv_ulong("wdreset", 1);
1412         else
1413                 karo_fdt_move_fdt();
1414
1415         baseboard = getenv("baseboard");
1416         if (!baseboard)
1417                 goto exit;
1418
1419         printf("Baseboard: %s\n", baseboard);
1420
1421         if (strncmp(baseboard, "stk5", 4) == 0) {
1422                 if ((strlen(baseboard) == 4) ||
1423                         strcmp(baseboard, "stk5-v3") == 0) {
1424                         stk5v3_board_init();
1425                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1426                         const char *otg_mode = getenv("otg_mode");
1427
1428                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1429                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1430                                         otg_mode, baseboard);
1431                                 setenv("otg_mode", "none");
1432                         }
1433                         stk5v5_board_init();
1434                 } else {
1435                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1436                                 baseboard + 4);
1437                 }
1438         } else {
1439                 printf("WARNING: Unsupported baseboard: '%s'\n",
1440                         baseboard);
1441                 if (!had_ctrlc())
1442                         return -EINVAL;
1443         }
1444
1445 exit:
1446         tx6_init_mac();
1447
1448         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1449         clear_ctrlc();
1450         return 0;
1451 }
1452
1453 #ifdef CONFIG_SERIAL_TAG
1454 void get_board_serial(struct tag_serialnr *serialnr)
1455 {
1456         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1457         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1458
1459         serialnr->low = readl(&fuse->cfg0);
1460         serialnr->high = readl(&fuse->cfg1);
1461 }
1462 #endif
1463
1464 #if defined(CONFIG_OF_BOARD_SETUP)
1465 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1466 #include <jffs2/jffs2.h>
1467 #include <mtd_node.h>
1468 static struct node_info nodes[] = {
1469         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1470 };
1471 #else
1472 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1473 #endif
1474
1475 static const char *tx6_touchpanels[] = {
1476         "ti,tsc2007",
1477         "edt,edt-ft5x06",
1478         "eeti,egalax_ts",
1479 };
1480
1481 int ft_board_setup(void *blob, bd_t *bd)
1482 {
1483         const char *baseboard = getenv("baseboard");
1484         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1485         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1486         int ret;
1487
1488         ret = fdt_increase_size(blob, 4096);
1489         if (ret) {
1490                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1491                 return ret;
1492         }
1493         if (stk5_v5)
1494                 karo_fdt_enable_node(blob, "stk5led", 0);
1495
1496         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1497
1498         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1499                                 ARRAY_SIZE(tx6_touchpanels));
1500         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1501         karo_fdt_fixup_flexcan(blob, stk5_v5);
1502
1503         karo_fdt_update_fb_mode(blob, video_mode);
1504
1505         return 0;
1506 }
1507 #endif /* CONFIG_OF_BOARD_SETUP */