board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17 #include <common.h>
  18 #include <errno.h>
  19 #include <libfdt.h>
  20 #include <fdt_support.h>
  21 #include <lcd.h>
  22 #include <netdev.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <video_fb.h>
  26 #include <ipu.h>
  27 #include <mxcfb.h>
  28 #include <i2c.h>
  29 #include <linux/fb.h>
  30 #include <asm/io.h>
  31 #include <asm/gpio.h>
  32 #include <asm/arch/mx6-pins.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/hab.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40 #include "pmic.h"
  41
  42 #define __data __attribute__((section(".data")))
  43
  44 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  45 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  46 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  47 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  48
  49 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  50 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  51 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  52
  53 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  54
  55 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  56 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  57 #else
  58 #define TEMPERATURE_MIN                 (-40)
  59 #endif
  60 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  61 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  62 #else
  63 #define TEMPERATURE_HOT                 80
  64 #endif
  65
  66 DECLARE_GLOBAL_DATA_PTR;
  67
  68 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  69
  70 enum {
  71         MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
  72 };
  73
  74 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  75 #ifdef CONFIG_SECURE_BOOT
  76 char __csf_data[0] __attribute__((section(".__csf_data")));
  77 #endif
  78
  79 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  80         /* RESET_OUT */
  81         MX6_PAD_GPIO_17__GPIO7_IO12,
  82
  83         /* UART pads */
  84 #if CONFIG_MXC_UART_BASE == UART1_BASE
  85         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
  86         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
  87         MX6_PAD_SD3_DAT1__UART1_RTS_B,
  88         MX6_PAD_SD3_DAT0__UART1_CTS_B,
  89 #endif
  90 #if CONFIG_MXC_UART_BASE == UART2_BASE
  91         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
  92         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
  93         MX6_PAD_SD4_DAT5__UART2_RTS_B,
  94         MX6_PAD_SD4_DAT6__UART2_CTS_B,
  95 #endif
  96 #if CONFIG_MXC_UART_BASE == UART3_BASE
  97         MX6_PAD_EIM_D24__UART3_TX_DATA,
  98         MX6_PAD_EIM_D25__UART3_RX_DATA,
  99         MX6_PAD_SD3_RST__UART3_RTS_B,
 100         MX6_PAD_SD3_DAT3__UART3_CTS_B,
 101 #endif
 102         /* internal I2C */
 103         MX6_PAD_EIM_D28__I2C1_SDA,
 104         MX6_PAD_EIM_D21__I2C1_SCL,
 105
 106         /* FEC PHY GPIO functions */
 107         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
 108         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
 109         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
 110 };
 111
 112 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 113         /* FEC functions */
 114         MX6_PAD_ENET_MDC__ENET_MDC,
 115         MX6_PAD_ENET_MDIO__ENET_MDIO,
 116         MX6_PAD_GPIO_16__ENET_REF_CLK,
 117         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 118         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 119         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
 120         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
 121         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 122         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
 123         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 124 };
 125
 126 static const struct gpio const tx6qdl_gpios[] = {
 127         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 128         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 129         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 130         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 131 };
 132
 133 /*
 134  * Functions
 135  */
 136 /* placed in section '.data' to prevent overwriting relocation info
 137  * overlayed with bss
 138  */
 139 static u32 wrsr __attribute__((section(".data")));
 140
 141 #define WRSR_POR                        (1 << 4)
 142 #define WRSR_TOUT                       (1 << 1)
 143 #define WRSR_SFTW                       (1 << 0)
 144
 145 static void print_reset_cause(void)
 146 {
 147         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 148         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 149         u32 srsr;
 150         char *dlm = "";
 151
 152         printf("Reset cause: ");
 153
 154         srsr = readl(&src_regs->srsr);
 155         wrsr = readw(wdt_base + 4);
 156
 157         if (wrsr & WRSR_POR) {
 158                 printf("%sPOR", dlm);
 159                 dlm = " | ";
 160         }
 161         if (srsr & 0x00004) {
 162                 printf("%sCSU", dlm);
 163                 dlm = " | ";
 164         }
 165         if (srsr & 0x00008) {
 166                 printf("%sIPP USER", dlm);
 167                 dlm = " | ";
 168         }
 169         if (srsr & 0x00010) {
 170                 if (wrsr & WRSR_SFTW) {
 171                         printf("%sSOFT", dlm);
 172                         dlm = " | ";
 173                 }
 174                 if (wrsr & WRSR_TOUT) {
 175                         printf("%sWDOG", dlm);
 176                         dlm = " | ";
 177                 }
 178         }
 179         if (srsr & 0x00020) {
 180                 printf("%sJTAG HIGH-Z", dlm);
 181                 dlm = " | ";
 182         }
 183         if (srsr & 0x00040) {
 184                 printf("%sJTAG SW", dlm);
 185                 dlm = " | ";
 186         }
 187         if (srsr & 0x10000) {
 188                 printf("%sWARM BOOT", dlm);
 189                 dlm = " | ";
 190         }
 191         if (dlm[0] == '\0')
 192                 printf("unknown");
 193
 194         printf("\n");
 195 }
 196
 197 static const char __data *tx6_mod_suffix;
 198
 199 static void tx6qdl_print_cpuinfo(void)
 200 {
 201         u32 cpurev = get_cpu_rev();
 202         char *cpu_str = "?";
 203
 204         switch ((cpurev >> 12) & 0xff) {
 205         case MXC_CPU_MX6SL:
 206                 cpu_str = "SL";
 207                 tx6_mod_suffix = "?";
 208                 break;
 209         case MXC_CPU_MX6DL:
 210                 cpu_str = "DL";
 211                 tx6_mod_suffix = "U";
 212                 break;
 213         case MXC_CPU_MX6SOLO:
 214                 cpu_str = "SOLO";
 215                 tx6_mod_suffix = "S";
 216                 break;
 217         case MXC_CPU_MX6Q:
 218                 cpu_str = "Q";
 219                 tx6_mod_suffix = "Q";
 220                 break;
 221         }
 222
 223         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 224                 cpu_str,
 225                 (cpurev & 0x000F0) >> 4,
 226                 (cpurev & 0x0000F) >> 0,
 227                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 228
 229         print_reset_cause();
 230 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 231         check_cpu_temperature(1);
 232 #endif
 233 }
 234
 235 int board_early_init_f(void)
 236 {
 237         return 0;
 238 }
 239
 240 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 241 static bool tx6_temp_check_enabled = true;
 242 #else
 243 #define tx6_temp_check_enabled  0
 244 #endif
 245 static int pmic_addr __data;
 246
 247 int board_init(void)
 248 {
 249         int ret;
 250
 251         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 252         if (ret < 0) {
 253                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
 254         }
 255         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 256
 257         /* Address of boot parameters */
 258         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 259         gd->bd->bi_arch_number = -1;
 260
 261         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 262                 if (wrsr & WRSR_TOUT)
 263                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 264                 else
 265                         printf("<CTRL-C> detected; safeboot enabled\n");
 266 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 267                 tx6_temp_check_enabled = false;
 268 #endif
 269                 return 0;
 270         }
 271
 272         ret = tx6_pmic_init(pmic_addr);
 273         if (ret) {
 274                 printf("Failed to setup PMIC voltages: %d\n", ret);
 275                 hang();
 276         }
 277         return 0;
 278 }
 279
 280 int dram_init(void)
 281 {
 282         /* dram_init must store complete ramsize in gd->ram_size */
 283         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 284                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 285         return 0;
 286 }
 287
 288 void dram_init_banksize(void)
 289 {
 290         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 291         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 292                         PHYS_SDRAM_1_SIZE);
 293 #if CONFIG_NR_DRAM_BANKS > 1
 294         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 295         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 296                         PHYS_SDRAM_2_SIZE);
 297 #endif
 298 }
 299
 300 #ifdef  CONFIG_FSL_ESDHC
 301 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
 302         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
 303         PAD_CTL_SRE_FAST)
 304
 305 static const iomux_v3_cfg_t mmc0_pads[] = {
 306         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 307         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 308         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 309         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 310         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 311         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 312         /* SD1 CD */
 313         MX6_PAD_SD3_CMD__GPIO7_IO02,
 314 };
 315
 316 static const iomux_v3_cfg_t mmc1_pads[] = {
 317         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 318         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 319         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 320         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 321         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 322         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 323         /* SD2 CD */
 324         MX6_PAD_SD3_CLK__GPIO7_IO03,
 325 };
 326
 327 #ifdef CONFIG_TX6_EMMC
 328 static const iomux_v3_cfg_t mmc3_pads[] = {
 329         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 330         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 331         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 332         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 333         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 334         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 335         /* eMMC RESET */
 336         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 337                                                 PAD_CTL_DSE_40ohm),
 338 };
 339 #endif
 340
 341 static struct tx6_esdhc_cfg {
 342         const iomux_v3_cfg_t *pads;
 343         int num_pads;
 344         enum mxc_clock clkid;
 345         struct fsl_esdhc_cfg cfg;
 346         int cd_gpio;
 347 } tx6qdl_esdhc_cfg[] = {
 348 #ifdef CONFIG_TX6_EMMC
 349         {
 350                 .pads = mmc3_pads,
 351                 .num_pads = ARRAY_SIZE(mmc3_pads),
 352                 .clkid = MXC_ESDHC4_CLK,
 353                 .cfg = {
 354                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 355                         .max_bus_width = 4,
 356                 },
 357                 .cd_gpio = -EINVAL,
 358         },
 359 #endif
 360         {
 361                 .pads = mmc0_pads,
 362                 .num_pads = ARRAY_SIZE(mmc0_pads),
 363                 .clkid = MXC_ESDHC_CLK,
 364                 .cfg = {
 365                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 366                         .max_bus_width = 4,
 367                 },
 368                 .cd_gpio = IMX_GPIO_NR(7, 2),
 369         },
 370         {
 371                 .pads = mmc1_pads,
 372                 .num_pads = ARRAY_SIZE(mmc1_pads),
 373                 .clkid = MXC_ESDHC2_CLK,
 374                 .cfg = {
 375                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 376                         .max_bus_width = 4,
 377                 },
 378                 .cd_gpio = IMX_GPIO_NR(7, 3),
 379         },
 380 };
 381
 382 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 383 {
 384         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 385 }
 386
 387 int board_mmc_getcd(struct mmc *mmc)
 388 {
 389         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 390
 391         if (cfg->cd_gpio < 0)
 392                 return 1;
 393
 394         debug("SD card %d is %spresent (GPIO %d)\n",
 395                 cfg - tx6qdl_esdhc_cfg,
 396                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 397                 cfg->cd_gpio);
 398         return !gpio_get_value(cfg->cd_gpio);
 399 }
 400
 401 int board_mmc_init(bd_t *bis)
 402 {
 403         int i;
 404
 405         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 406                 struct mmc *mmc;
 407                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 408                 int ret;
 409
 410                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 411                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 412
 413                 if (cfg->cd_gpio >= 0) {
 414                         ret = gpio_request_one(cfg->cd_gpio,
 415                                         GPIOFLAG_INPUT, "MMC CD");
 416                         if (ret) {
 417                                 printf("Error %d requesting GPIO%d_%d\n",
 418                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 419                                 continue;
 420                         }
 421                 }
 422
 423                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 424                 fsl_esdhc_initialize(bis, &cfg->cfg);
 425
 426                 mmc = find_mmc_device(i);
 427                 if (mmc == NULL)
 428                         continue;
 429                 if (board_mmc_getcd(mmc))
 430                         mmc_init(mmc);
 431         }
 432         return 0;
 433 }
 434 #endif /* CONFIG_CMD_MMC */
 435
 436 #ifdef CONFIG_FEC_MXC
 437
 438 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 439                         PAD_CTL_SRE_FAST)
 440 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 441 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 442
 443 #ifndef ETH_ALEN
 444 #define ETH_ALEN 6
 445 #endif
 446
 447 int board_eth_init(bd_t *bis)
 448 {
 449         int ret;
 450
 451         /* delay at least 21ms for the PHY internal POR signal to deassert */
 452         udelay(22000);
 453
 454         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 455                                         ARRAY_SIZE(tx6qdl_fec_pads));
 456
 457         /* Deassert RESET to the external phy */
 458         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 459
 460         ret = cpu_eth_init(bis);
 461         if (ret)
 462                 printf("cpu_eth_init() failed: %d\n", ret);
 463
 464         return ret;
 465 }
 466
 467 static void tx6_init_mac(void)
 468 {
 469         u8 mac[ETH_ALEN];
 470
 471         imx_get_mac_from_fuse(-1, mac);
 472         if (!is_valid_ether_addr(mac)) {
 473                 printf("No valid MAC address programmed\n");
 474                 return;
 475         }
 476
 477         printf("MAC addr from fuse: %pM\n", mac);
 478         eth_setenv_enetaddr("ethaddr", mac);
 479 }
 480 #else
 481 static inline void tx6_init_mac(void)
 482 {
 483 }
 484 #endif /* CONFIG_FEC_MXC */
 485
 486 enum {
 487         LED_STATE_INIT = -1,
 488         LED_STATE_OFF,
 489         LED_STATE_ON,
 490 };
 491
 492 static inline int calc_blink_rate(void)
 493 {
 494         if (!tx6_temp_check_enabled)
 495                 return CONFIG_SYS_HZ;
 496
 497         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 498                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 499                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 500 }
 501
 502 void show_activity(int arg)
 503 {
 504         static int led_state = LED_STATE_INIT;
 505         static int blink_rate;
 506         static ulong last;
 507
 508         if (led_state == LED_STATE_INIT) {
 509                 last = get_timer(0);
 510                 gpio_set_value(TX6_LED_GPIO, 1);
 511                 led_state = LED_STATE_ON;
 512                 blink_rate = calc_blink_rate();
 513         } else {
 514                 if (get_timer(last) > blink_rate) {
 515                         blink_rate = calc_blink_rate();
 516                         last = get_timer_masked();
 517                         if (led_state == LED_STATE_ON) {
 518                                 gpio_set_value(TX6_LED_GPIO, 0);
 519                         } else {
 520                                 gpio_set_value(TX6_LED_GPIO, 1);
 521                         }
 522                         led_state = 1 - led_state;
 523                 }
 524         }
 525 }
 526
 527 static const iomux_v3_cfg_t stk5_pads[] = {
 528         /* SW controlled LED on STK5 baseboard */
 529         MX6_PAD_EIM_A18__GPIO2_IO20,
 530
 531         /* I2C bus on DIMM pins 40/41 */
 532         MX6_PAD_GPIO_6__I2C3_SDA,
 533         MX6_PAD_GPIO_3__I2C3_SCL,
 534
 535         /* TSC200x PEN IRQ */
 536         MX6_PAD_EIM_D26__GPIO3_IO26,
 537
 538         /* EDT-FT5x06 Polytouch panel */
 539         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
 540         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
 541         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
 542
 543         /* USBH1 */
 544         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
 545         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
 546         /* USBOTG */
 547         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
 548         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
 549         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
 550 };
 551
 552 static const struct gpio stk5_gpios[] = {
 553         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 554
 555         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 556         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 557         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 558         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 559         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 560 };
 561
 562 #ifdef CONFIG_LCD
 563 static u16 tx6_cmap[256];
 564 vidinfo_t panel_info = {
 565         /* set to max. size supported by SoC */
 566         .vl_col = 1920,
 567         .vl_row = 1080,
 568
 569         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 570         .cmap = tx6_cmap,
 571 };
 572
 573 static struct fb_videomode tx6_fb_modes[] = {
 574 #ifndef CONFIG_SYS_LVDS_IF
 575         {
 576                 /* Standard VGA timing */
 577                 .name           = "VGA",
 578                 .refresh        = 60,
 579                 .xres           = 640,
 580                 .yres           = 480,
 581                 .pixclock       = KHZ2PICOS(25175),
 582                 .left_margin    = 48,
 583                 .hsync_len      = 96,
 584                 .right_margin   = 16,
 585                 .upper_margin   = 31,
 586                 .vsync_len      = 2,
 587                 .lower_margin   = 12,
 588                 .sync           = FB_SYNC_CLK_LAT_FALL,
 589         },
 590         {
 591                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 592                  * DE high active, 115.2 mm x 86.4 mm display area
 593                  * VGA compatible timing
 594                  */
 595                 .name           = "ETV570",
 596                 .refresh        = 60,
 597                 .xres           = 640,
 598                 .yres           = 480,
 599                 .pixclock       = KHZ2PICOS(25175),
 600                 .left_margin    = 114,
 601                 .hsync_len      = 30,
 602                 .right_margin   = 16,
 603                 .upper_margin   = 32,
 604                 .vsync_len      = 3,
 605                 .lower_margin   = 10,
 606                 .sync           = FB_SYNC_CLK_LAT_FALL,
 607         },
 608         {
 609                 /* Emerging ET0350G0DH6 320 x 240 display.
 610                  * 70.08 mm x 52.56 mm display area.
 611                  */
 612                 .name           = "ET0350",
 613                 .refresh        = 60,
 614                 .xres           = 320,
 615                 .yres           = 240,
 616                 .pixclock       = KHZ2PICOS(6500),
 617                 .left_margin    = 68 - 34,
 618                 .hsync_len      = 34,
 619                 .right_margin   = 20,
 620                 .upper_margin   = 18 - 3,
 621                 .vsync_len      = 3,
 622                 .lower_margin   = 4,
 623                 .sync           = FB_SYNC_CLK_LAT_FALL,
 624         },
 625         {
 626                 /* Emerging ET0430G0DH6 480 x 272 display.
 627                  * 95.04 mm x 53.856 mm display area.
 628                  */
 629                 .name           = "ET0430",
 630                 .refresh        = 60,
 631                 .xres           = 480,
 632                 .yres           = 272,
 633                 .pixclock       = KHZ2PICOS(9000),
 634                 .left_margin    = 2,
 635                 .hsync_len      = 41,
 636                 .right_margin   = 2,
 637                 .upper_margin   = 2,
 638                 .vsync_len      = 10,
 639                 .lower_margin   = 2,
 640         },
 641         {
 642                 /* Emerging ET0500G0DH6 800 x 480 display.
 643                  * 109.6 mm x 66.4 mm display area.
 644                  */
 645                 .name           = "ET0500",
 646                 .refresh        = 60,
 647                 .xres           = 800,
 648                 .yres           = 480,
 649                 .pixclock       = KHZ2PICOS(33260),
 650                 .left_margin    = 216 - 128,
 651                 .hsync_len      = 128,
 652                 .right_margin   = 1056 - 800 - 216,
 653                 .upper_margin   = 35 - 2,
 654                 .vsync_len      = 2,
 655                 .lower_margin   = 525 - 480 - 35,
 656                 .sync           = FB_SYNC_CLK_LAT_FALL,
 657         },
 658         {
 659                 /* Emerging ETQ570G0DH6 320 x 240 display.
 660                  * 115.2 mm x 86.4 mm display area.
 661                  */
 662                 .name           = "ETQ570",
 663                 .refresh        = 60,
 664                 .xres           = 320,
 665                 .yres           = 240,
 666                 .pixclock       = KHZ2PICOS(6400),
 667                 .left_margin    = 38,
 668                 .hsync_len      = 30,
 669                 .right_margin   = 30,
 670                 .upper_margin   = 16, /* 15 according to datasheet */
 671                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 672                 .lower_margin   = 4, /* 4.5 according to datasheet */
 673                 .sync           = FB_SYNC_CLK_LAT_FALL,
 674         },
 675         {
 676                 /* Emerging ET0700G0DH6 800 x 480 display.
 677                  * 152.4 mm x 91.44 mm display area.
 678                  */
 679                 .name           = "ET0700",
 680                 .refresh        = 60,
 681                 .xres           = 800,
 682                 .yres           = 480,
 683                 .pixclock       = KHZ2PICOS(33260),
 684                 .left_margin    = 216 - 128,
 685                 .hsync_len      = 128,
 686                 .right_margin   = 1056 - 800 - 216,
 687                 .upper_margin   = 35 - 2,
 688                 .vsync_len      = 2,
 689                 .lower_margin   = 525 - 480 - 35,
 690                 .sync           = FB_SYNC_CLK_LAT_FALL,
 691         },
 692         {
 693                 /* Emerging ET070001DM6 800 x 480 display.
 694                  * 152.4 mm x 91.44 mm display area.
 695                  */
 696                 .name           = "ET070001DM6",
 697                 .refresh        = 60,
 698                 .xres           = 800,
 699                 .yres           = 480,
 700                 .pixclock       = KHZ2PICOS(33260),
 701                 .left_margin    = 216 - 128,
 702                 .hsync_len      = 128,
 703                 .right_margin   = 1056 - 800 - 216,
 704                 .upper_margin   = 35 - 2,
 705                 .vsync_len      = 2,
 706                 .lower_margin   = 525 - 480 - 35,
 707                 .sync           = 0,
 708         },
 709 #else
 710         {
 711                 /* HannStar HSD100PXN1
 712                  * 202.7m mm x 152.06 mm display area.
 713                  */
 714                 .name           = "HSD100PXN1",
 715                 .refresh        = 60,
 716                 .xres           = 1024,
 717                 .yres           = 768,
 718                 .pixclock       = KHZ2PICOS(65000),
 719                 .left_margin    = 0,
 720                 .hsync_len      = 0,
 721                 .right_margin   = 320,
 722                 .upper_margin   = 0,
 723                 .vsync_len      = 0,
 724                 .lower_margin   = 38,
 725                 .sync           = FB_SYNC_CLK_LAT_FALL,
 726         },
 727 #endif
 728         {
 729                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 730                 .refresh        = 60,
 731                 .left_margin    = 48,
 732                 .hsync_len      = 96,
 733                 .right_margin   = 16,
 734                 .upper_margin   = 31,
 735                 .vsync_len      = 2,
 736                 .lower_margin   = 12,
 737                 .sync           = FB_SYNC_CLK_LAT_FALL,
 738         },
 739 };
 740
 741 static int lcd_enabled = 1;
 742 static int lcd_bl_polarity;
 743
 744 static int lcd_backlight_polarity(void)
 745 {
 746         return lcd_bl_polarity;
 747 }
 748
 749 void lcd_enable(void)
 750 {
 751         /* HACK ALERT:
 752          * global variable from common/lcd.c
 753          * Set to 0 here to prevent messages from going to LCD
 754          * rather than serial console
 755          */
 756         lcd_is_enabled = 0;
 757
 758         if (lcd_enabled) {
 759                 karo_load_splashimage(1);
 760
 761                 debug("Switching LCD on\n");
 762                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 763                 udelay(100);
 764                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 765                 udelay(300000);
 766                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 767                         lcd_backlight_polarity());
 768         }
 769 }
 770
 771 void lcd_disable(void)
 772 {
 773         if (lcd_enabled) {
 774                 printf("Disabling LCD\n");
 775                 ipuv3_fb_shutdown();
 776         }
 777 }
 778
 779 void lcd_panel_disable(void)
 780 {
 781         if (lcd_enabled) {
 782                 debug("Switching LCD off\n");
 783                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 784                         !lcd_backlight_polarity());
 785                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 786                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 787         }
 788 }
 789
 790 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 791         /* LCD RESET */
 792         MX6_PAD_EIM_D29__GPIO3_IO29,
 793         /* LCD POWER_ENABLE */
 794         MX6_PAD_EIM_EB3__GPIO2_IO31,
 795         /* LCD Backlight (PWM) */
 796         MX6_PAD_GPIO_1__GPIO1_IO01,
 797
 798 #ifndef CONFIG_SYS_LVDS_IF
 799         /* Display */
 800         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 801         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 802         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 803         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 804         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 805         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 806         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 807         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 808         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 809         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 810         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 811         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 812         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 813         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 814         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 815         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 816         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 817         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 818         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 819         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 820         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 821         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 822         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 823         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 824         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
 825         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
 826         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 827         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 828 #endif
 829 };
 830
 831 static const struct gpio stk5_lcd_gpios[] = {
 832         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
 833         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
 834         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 835 };
 836
 837 void lcd_ctrl_init(void *lcdbase)
 838 {
 839         int color_depth = 24;
 840         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 841         const char *vm;
 842         unsigned long val;
 843         int refresh = 60;
 844         struct fb_videomode *p = &tx6_fb_modes[0];
 845         struct fb_videomode fb_mode;
 846         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 847         int pix_fmt;
 848         int lcd_bus_width;
 849         unsigned long di_clk_rate = 65000000;
 850
 851         if (!lcd_enabled) {
 852                 debug("LCD disabled\n");
 853                 return;
 854         }
 855
 856         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 857                 debug("Disabling LCD\n");
 858                 lcd_enabled = 0;
 859                 setenv("splashimage", NULL);
 860                 return;
 861         }
 862
 863         karo_fdt_move_fdt();
 864         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 865
 866         if (video_mode == NULL) {
 867                 debug("Disabling LCD\n");
 868                 lcd_enabled = 0;
 869                 return;
 870         }
 871         vm = video_mode;
 872         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 873                 p = &fb_mode;
 874                 debug("Using video mode from FDT\n");
 875                 vm += strlen(vm);
 876                 if (fb_mode.xres > panel_info.vl_col ||
 877                         fb_mode.yres > panel_info.vl_row) {
 878                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 879                                 fb_mode.xres, fb_mode.yres,
 880                                 panel_info.vl_col, panel_info.vl_row);
 881                         lcd_enabled = 0;
 882                         return;
 883                 }
 884         }
 885         if (p->name != NULL)
 886                 debug("Trying compiled-in video modes\n");
 887         while (p->name != NULL) {
 888                 if (strcmp(p->name, vm) == 0) {
 889                         debug("Using video mode: '%s'\n", p->name);
 890                         vm += strlen(vm);
 891                         break;
 892                 }
 893                 p++;
 894         }
 895         if (*vm != '\0')
 896                 debug("Trying to decode video_mode: '%s'\n", vm);
 897         while (*vm != '\0') {
 898                 if (*vm >= '0' && *vm <= '9') {
 899                         char *end;
 900
 901                         val = simple_strtoul(vm, &end, 0);
 902                         if (end > vm) {
 903                                 if (!xres_set) {
 904                                         if (val > panel_info.vl_col)
 905                                                 val = panel_info.vl_col;
 906                                         p->xres = val;
 907                                         panel_info.vl_col = val;
 908                                         xres_set = 1;
 909                                 } else if (!yres_set) {
 910                                         if (val > panel_info.vl_row)
 911                                                 val = panel_info.vl_row;
 912                                         p->yres = val;
 913                                         panel_info.vl_row = val;
 914                                         yres_set = 1;
 915                                 } else if (!bpp_set) {
 916                                         switch (val) {
 917                                         case 32:
 918                                         case 24:
 919                                                 if (is_lvds())
 920                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 921                                                 /* fallthru */
 922                                         case 16:
 923                                         case 8:
 924                                                 color_depth = val;
 925                                                 break;
 926
 927                                         case 18:
 928                                                 if (is_lvds()) {
 929                                                         color_depth = val;
 930                                                         break;
 931                                                 }
 932                                                 /* fallthru */
 933                                         default:
 934                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 935                                                         end - vm, vm, color_depth);
 936                                         }
 937                                         bpp_set = 1;
 938                                 } else if (!refresh_set) {
 939                                         refresh = val;
 940                                         refresh_set = 1;
 941                                 }
 942                         }
 943                         vm = end;
 944                 }
 945                 switch (*vm) {
 946                 case '@':
 947                         bpp_set = 1;
 948                         /* fallthru */
 949                 case '-':
 950                         yres_set = 1;
 951                         /* fallthru */
 952                 case 'x':
 953                         xres_set = 1;
 954                         /* fallthru */
 955                 case 'M':
 956                 case 'R':
 957                         vm++;
 958                         break;
 959
 960                 default:
 961                         if (*vm != '\0')
 962                                 vm++;
 963                 }
 964         }
 965         if (p->xres == 0 || p->yres == 0) {
 966                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 967                 lcd_enabled = 0;
 968                 printf("Supported video modes are:");
 969                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 970                         printf(" %s", p->name);
 971                 }
 972                 printf("\n");
 973                 return;
 974         }
 975         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 976                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 977                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 978                 lcd_enabled = 0;
 979                 return;
 980         }
 981         panel_info.vl_col = p->xres;
 982         panel_info.vl_row = p->yres;
 983
 984         switch (color_depth) {
 985         case 8:
 986                 panel_info.vl_bpix = LCD_COLOR8;
 987                 break;
 988         case 16:
 989                 panel_info.vl_bpix = LCD_COLOR16;
 990                 break;
 991         default:
 992                 panel_info.vl_bpix = LCD_COLOR32;
 993         }
 994
 995         p->pixclock = KHZ2PICOS(refresh *
 996                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 997                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 998                                 1000);
 999         debug("Pixel clock set to %lu.%03lu MHz\n",
1000                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1001
1002         if (p != &fb_mode) {
1003                 int ret;
1004
1005                 debug("Creating new display-timing node from '%s'\n",
1006                         video_mode);
1007                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1008                 if (ret)
1009                         printf("Failed to create new display-timing node from '%s': %d\n",
1010                                 video_mode, ret);
1011         }
1012
1013         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1014         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1015                                         ARRAY_SIZE(stk5_lcd_pads));
1016
1017         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1018         switch (lcd_bus_width) {
1019         case 24:
1020                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1021                 break;
1022
1023         case 18:
1024                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1025                 break;
1026
1027         case 16:
1028                 if (!is_lvds()) {
1029                         pix_fmt = IPU_PIX_FMT_RGB565;
1030                         break;
1031                 }
1032                 /* fallthru */
1033         default:
1034                 lcd_enabled = 0;
1035                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1036                         lcd_bus_width);
1037                 return;
1038         }
1039         if (is_lvds()) {
1040                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1041                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1042                 uint32_t gpr2;
1043                 uint32_t gpr3;
1044
1045                 if (lvds_chan_mask == 0) {
1046                         printf("No LVDS channel active\n");
1047                         lcd_enabled = 0;
1048                         return;
1049                 }
1050
1051                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1052                 if (lcd_bus_width == 24)
1053                         gpr2 |= (1 << 5) | (1 << 7);
1054                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1055                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1056                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1057                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1058
1059                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1060                 gpr3 &= ~((3 << 8) | (3 << 6));
1061                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1062         }
1063         if (karo_load_splashimage(0) == 0) {
1064                 int ret;
1065
1066                 debug("Initializing LCD controller\n");
1067                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1068                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1069                                 di_clk_rate, -1);
1070                 if (ret) {
1071                         printf("Failed to initialize FB driver: %d\n", ret);
1072                         lcd_enabled = 0;
1073                 }
1074         } else {
1075                 debug("Skipping initialization of LCD controller\n");
1076         }
1077 }
1078 #else
1079 #define lcd_enabled 0
1080 #endif /* CONFIG_LCD */
1081
1082 static void stk5_board_init(void)
1083 {
1084         int ret;
1085
1086         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1087         if (ret < 0) {
1088                 printf("Failed to request stk5_gpios: %d\n", ret);
1089                 return;
1090         }
1091         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1092 }
1093
1094 static void stk5v3_board_init(void)
1095 {
1096         stk5_board_init();
1097 }
1098
1099 static void stk5v5_board_init(void)
1100 {
1101         int ret;
1102
1103         stk5_board_init();
1104
1105         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1106                         "Flexcan Transceiver");
1107         if (ret) {
1108                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1109                 return;
1110         }
1111
1112         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1113 }
1114
1115 static void tx6qdl_set_cpu_clock(void)
1116 {
1117         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1118
1119         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1120                 return;
1121
1122         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1123                 printf("%s detected; skipping cpu clock change\n",
1124                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1125                 return;
1126         }
1127         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1128                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1129                 printf("CPU clock set to %lu.%03lu MHz\n",
1130                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1131         } else {
1132                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1133         }
1134 }
1135
1136 int board_late_init(void)
1137 {
1138         int ret = 0;
1139         const char *baseboard;
1140 #if 1
1141         /* override secure_boot fuse */
1142         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1143         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1144
1145         writel(0x12, &fuse->cfg5);
1146 #endif
1147
1148         env_cleanup();
1149
1150         if (tx6_temp_check_enabled)
1151                 check_cpu_temperature(1);
1152
1153         tx6qdl_set_cpu_clock();
1154
1155         if (had_ctrlc())
1156                 setenv_ulong("safeboot", 1);
1157         else if (wrsr & WRSR_TOUT)
1158                 setenv_ulong("wdreset", 1);
1159         else
1160                 karo_fdt_move_fdt();
1161
1162         baseboard = getenv("baseboard");
1163         if (!baseboard)
1164                 goto exit;
1165
1166         printf("Baseboard: %s\n", baseboard);
1167
1168         if (strncmp(baseboard, "stk5", 4) == 0) {
1169                 if ((strlen(baseboard) == 4) ||
1170                         strcmp(baseboard, "stk5-v3") == 0) {
1171                         stk5v3_board_init();
1172                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1173                         const char *otg_mode = getenv("otg_mode");
1174
1175                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1176                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1177                                         otg_mode, baseboard);
1178                                 setenv("otg_mode", "none");
1179                         }
1180                         stk5v5_board_init();
1181                 } else {
1182                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1183                                 baseboard + 4);
1184                 }
1185         } else {
1186                 printf("WARNING: Unsupported baseboard: '%s'\n",
1187                         baseboard);
1188                 ret = -EINVAL;
1189         }
1190
1191 exit:
1192         tx6_init_mac();
1193
1194         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1195         clear_ctrlc();
1196         return ret;
1197 }
1198
1199 #ifdef CONFIG_TX6_NAND
1200 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1201 #else
1202 #ifdef CONFIG_MMC_BOOT_SIZE
1203 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
1204 #else
1205 #define TX6_FLASH_SZ    2
1206 #endif
1207 #endif /* CONFIG_TX6_NAND */
1208
1209 #define TX6_DDR_SZ      (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
1210
1211 static char tx6_mem_table[] = {
1212         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
1213         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
1214         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
1215         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
1216         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
1217         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
1218         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
1219         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
1220         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
1221         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
1222         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
1223         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
1224 };
1225
1226 static inline char tx6_mem_suffix(void)
1227 {
1228         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1229
1230         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1231                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1232
1233         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1234                 return '?';
1235
1236         return tx6_mem_table[mem_idx];
1237 };
1238
1239 static struct {
1240         uchar addr;
1241         uchar rev;
1242 } tx6_mod_revs[] = {
1243         { 0x3c, 1, },
1244         { 0x32, 2, },
1245         { 0x33, 3, },
1246 };
1247
1248 static int tx6_get_mod_rev(unsigned int pmic_id)
1249 {
1250         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
1251                 return tx6_mod_revs[pmic_id].rev;
1252
1253         return 0;
1254 }
1255
1256 static int tx6_pmic_probe(void)
1257 {
1258         int i;
1259
1260         i2c_init_all();
1261
1262         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
1263                 u8 i2c_addr = tx6_mod_revs[i].addr;
1264                 int ret = i2c_probe(i2c_addr);
1265
1266                 if (ret == 0) {
1267                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
1268                         return i;
1269                 }
1270                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
1271         }
1272         return -EINVAL;
1273 }
1274
1275 int checkboard(void)
1276 {
1277         u32 cpurev = get_cpu_rev();
1278         int cpu_variant = (cpurev >> 12) & 0xff;
1279         int pmic_id;
1280
1281         tx6qdl_print_cpuinfo();
1282
1283         pmic_id = tx6_pmic_probe();
1284         if (pmic_id >= 0)
1285                 pmic_addr = tx6_mod_revs[pmic_id].addr;
1286
1287         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1288                 tx6_mod_suffix,
1289                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1290                 is_lvds(), tx6_get_mod_rev(pmic_id),
1291                 tx6_mem_suffix());
1292
1293         get_hab_status();
1294
1295         return 0;
1296 }
1297
1298 #ifdef CONFIG_SERIAL_TAG
1299 void get_board_serial(struct tag_serialnr *serialnr)
1300 {
1301         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1302         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1303
1304         serialnr->low = readl(&fuse->cfg0);
1305         serialnr->high = readl(&fuse->cfg1);
1306 }
1307 #endif
1308
1309 #if defined(CONFIG_OF_BOARD_SETUP)
1310 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1311 #include <jffs2/jffs2.h>
1312 #include <mtd_node.h>
1313 static struct node_info nodes[] = {
1314         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1315 };
1316 #else
1317 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1318 #endif
1319
1320 static const char *tx6_touchpanels[] = {
1321         "ti,tsc2007",
1322         "edt,edt-ft5x06",
1323         "eeti,egalax_ts",
1324 };
1325
1326 int ft_board_setup(void *blob, bd_t *bd)
1327 {
1328         const char *baseboard = getenv("baseboard");
1329         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1330         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1331         int ret;
1332
1333         ret = fdt_increase_size(blob, 4096);
1334         if (ret) {
1335                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1336                 return ret;
1337         }
1338         if (stk5_v5)
1339                 karo_fdt_enable_node(blob, "stk5led", 0);
1340
1341         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1342         fdt_fixup_ethernet(blob);
1343
1344         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1345                                 ARRAY_SIZE(tx6_touchpanels));
1346         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1347         karo_fdt_fixup_flexcan(blob, stk5_v5);
1348
1349         karo_fdt_update_fb_mode(blob, video_mode);
1350
1351         return 0;
1352 }
1353 #endif /* CONFIG_OF_BOARD_SETUP */