board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012,2013 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <common.h>
  19 #include <errno.h>
  20 #include <libfdt.h>
  21 #include <fdt_support.h>
  22 #include <lcd.h>
  23 #include <netdev.h>
  24 #include <mmc.h>
  25 #include <fsl_esdhc.h>
  26 #include <video_fb.h>
  27 #include <ipu.h>
  28 #include <mxcfb.h>
  29 #include <i2c.h>
  30 #include <linux/fb.h>
  31 #include <asm/io.h>
  32 #include <asm/gpio.h>
  33 #include <asm/arch/mx6-pins.h>
  34 #include <asm/arch/clock.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40
  41 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  42 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  43 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(2, 4)
  44 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  45
  46 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  47 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  48 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  49
  50 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  51
  52 #define TEMPERATURE_MIN                 -40
  53 #define TEMPERATURE_HOT                 80
  54 #define TEMPERATURE_MAX                 125
  55
  56 DECLARE_GLOBAL_DATA_PTR;
  57
  58 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  59
  60 static const iomux_v3_cfg_t tx6qdl_pads[] = {
  61         /* NAND flash pads */
  62         MX6_PAD_NANDF_CLE__RAWNAND_CLE,
  63         MX6_PAD_NANDF_ALE__RAWNAND_ALE,
  64         MX6_PAD_NANDF_WP_B__RAWNAND_RESETN,
  65         MX6_PAD_NANDF_RB0__RAWNAND_READY0,
  66         MX6_PAD_NANDF_CS0__RAWNAND_CE0N,
  67         MX6_PAD_SD4_CMD__RAWNAND_RDN,
  68         MX6_PAD_SD4_CLK__RAWNAND_WRN,
  69         MX6_PAD_NANDF_D0__RAWNAND_D0,
  70         MX6_PAD_NANDF_D1__RAWNAND_D1,
  71         MX6_PAD_NANDF_D2__RAWNAND_D2,
  72         MX6_PAD_NANDF_D3__RAWNAND_D3,
  73         MX6_PAD_NANDF_D4__RAWNAND_D4,
  74         MX6_PAD_NANDF_D5__RAWNAND_D5,
  75         MX6_PAD_NANDF_D6__RAWNAND_D6,
  76         MX6_PAD_NANDF_D7__RAWNAND_D7,
  77
  78         /* RESET_OUT */
  79         MX6_PAD_GPIO_17__GPIO_7_12,
  80
  81         /* UART pads */
  82 #if CONFIG_MXC_UART_BASE == UART1_BASE
  83         MX6_PAD_SD3_DAT7__UART1_TXD,
  84         MX6_PAD_SD3_DAT6__UART1_RXD,
  85         MX6_PAD_SD3_DAT1__UART1_RTS,
  86         MX6_PAD_SD3_DAT0__UART1_CTS,
  87 #endif
  88 #if CONFIG_MXC_UART_BASE == UART2_BASE
  89         MX6_PAD_SD4_DAT4__UART2_RXD,
  90         MX6_PAD_SD4_DAT7__UART2_TXD,
  91         MX6_PAD_SD4_DAT5__UART2_RTS,
  92         MX6_PAD_SD4_DAT6__UART2_CTS,
  93 #endif
  94 #if CONFIG_MXC_UART_BASE == UART3_BASE
  95         MX6_PAD_EIM_D24__UART3_TXD,
  96         MX6_PAD_EIM_D25__UART3_RXD,
  97         MX6_PAD_SD3_RST__UART3_RTS,
  98         MX6_PAD_SD3_DAT3__UART3_CTS,
  99 #endif
 100         /* internal I2C */
 101         MX6_PAD_EIM_D28__I2C1_SDA,
 102         MX6_PAD_EIM_D21__I2C1_SCL,
 103
 104         /* FEC PHY GPIO functions */
 105         MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */
 106         MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */
 107         MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */
 108 };
 109
 110 static const iomux_v3_cfg_t tx6qdl_fec_pads[] = {
 111         /* FEC functions */
 112         MX6_PAD_ENET_MDC__ENET_MDC,
 113         MX6_PAD_ENET_MDIO__ENET_MDIO,
 114         MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT,
 115         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 116         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 117         MX6_PAD_ENET_RXD1__ENET_RDATA_1,
 118         MX6_PAD_ENET_RXD0__ENET_RDATA_0,
 119         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 120         MX6_PAD_ENET_TXD1__ENET_TDATA_1,
 121         MX6_PAD_ENET_TXD0__ENET_TDATA_0,
 122 };
 123
 124 static const struct gpio tx6qdl_gpios[] = {
 125         { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 126         { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 127         { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 128         { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
 129 };
 130
 131 /*
 132  * Functions
 133  */
 134 /* placed in section '.data' to prevent overwriting relocation info
 135  * overlayed with bss
 136  */
 137 static u32 wrsr __attribute__((section(".data")));
 138
 139 #define WRSR_POR                        (1 << 4)
 140 #define WRSR_TOUT                       (1 << 1)
 141 #define WRSR_SFTW                       (1 << 0)
 142
 143 static void print_reset_cause(void)
 144 {
 145         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 146         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 147         u32 srsr;
 148         char *dlm = "";
 149
 150         printf("Reset cause: ");
 151
 152         srsr = readl(&src_regs->srsr);
 153         wrsr = readw(wdt_base + 4);
 154
 155         if (wrsr & WRSR_POR) {
 156                 printf("%sPOR", dlm);
 157                 dlm = " | ";
 158         }
 159         if (srsr & 0x00004) {
 160                 printf("%sCSU", dlm);
 161                 dlm = " | ";
 162         }
 163         if (srsr & 0x00008) {
 164                 printf("%sIPP USER", dlm);
 165                 dlm = " | ";
 166         }
 167         if (srsr & 0x00010) {
 168                 if (wrsr & WRSR_SFTW) {
 169                         printf("%sSOFT", dlm);
 170                         dlm = " | ";
 171                 }
 172                 if (wrsr & WRSR_TOUT) {
 173                         printf("%sWDOG", dlm);
 174                         dlm = " | ";
 175                 }
 176         }
 177         if (srsr & 0x00020) {
 178                 printf("%sJTAG HIGH-Z", dlm);
 179                 dlm = " | ";
 180         }
 181         if (srsr & 0x00040) {
 182                 printf("%sJTAG SW", dlm);
 183                 dlm = " | ";
 184         }
 185         if (srsr & 0x10000) {
 186                 printf("%sWARM BOOT", dlm);
 187                 dlm = " | ";
 188         }
 189         if (dlm[0] == '\0')
 190                 printf("unknown");
 191
 192         printf("\n");
 193 }
 194
 195 int read_cpu_temperature(void);
 196 int check_cpu_temperature(int boot);
 197
 198 static void tx6qdl_print_cpuinfo(void)
 199 {
 200         u32 cpurev = get_cpu_rev();
 201         char *cpu_str = "?";
 202
 203         switch ((cpurev >> 12) & 0xff) {
 204         case MXC_CPU_MX6SL:
 205                 cpu_str = "SL";
 206                 break;
 207         case MXC_CPU_MX6DL:
 208                 cpu_str = "DL";
 209                 break;
 210         case MXC_CPU_MX6SOLO:
 211                 cpu_str = "SOLO";
 212                 break;
 213         case MXC_CPU_MX6Q:
 214                 cpu_str = "Q";
 215                 break;
 216         }
 217
 218         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 219                 cpu_str,
 220                 (cpurev & 0x000F0) >> 4,
 221                 (cpurev & 0x0000F) >> 0,
 222                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 223
 224         print_reset_cause();
 225         check_cpu_temperature(1);
 226 }
 227
 228 #define LTC3676_BUCK1           0x01
 229 #define LTC3676_BUCK2           0x02
 230 #define LTC3676_BUCK3           0x03
 231 #define LTC3676_BUCK4           0x04
 232 #define LTC3676_DVB1A           0x0A
 233 #define LTC3676_DVB1B           0x0B
 234 #define LTC3676_DVB2A           0x0C
 235 #define LTC3676_DVB2B           0x0D
 236 #define LTC3676_DVB3A           0x0E
 237 #define LTC3676_DVB3B           0x0F
 238 #define LTC3676_DVB4A           0x10
 239 #define LTC3676_DVB4B           0x11
 240 #define LTC3676_MSKPG           0x13
 241 #define LTC3676_CLIRQ           0x1f
 242
 243 #define LTC3676_BUCK_DVDT_FAST  (1 << 0)
 244 #define LTC3676_BUCK_KEEP_ALIVE (1 << 1)
 245 #define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
 246 #define LTC3676_BUCK_PHASE_SEL  (1 << 3)
 247 #define LTC3676_BUCK_ENABLE_300 (1 << 4)
 248 #define LTC3676_BUCK_PULSE_SKIP (0 << 5)
 249 #define LTC3676_BUCK_BURST_MODE (1 << 5)
 250 #define LTC3676_BUCK_CONTINUOUS (2 << 5)
 251 #define LTC3676_BUCK_ENABLE     (1 << 7)
 252
 253 #define LTC3676_PGOOD_MASK      (1 << 5)
 254
 255 #define LTC3676_MSKPG_BUCK1     (1 << 0)
 256 #define LTC3676_MSKPG_BUCK2     (1 << 1)
 257 #define LTC3676_MSKPG_BUCK3     (1 << 2)
 258 #define LTC3676_MSKPG_BUCK4     (1 << 3)
 259 #define LTC3676_MSKPG_LDO2      (1 << 5)
 260 #define LTC3676_MSKPG_LDO3      (1 << 6)
 261 #define LTC3676_MSKPG_LDO4      (1 << 7)
 262
 263 #define VDD_IO_VAL              mV_to_regval(vout_to_vref(3300 * 10, 5))
 264 #define VDD_IO_VAL_LP           mV_to_regval(vout_to_vref(3100 * 10, 5))
 265 #define VDD_IO_VAL_2            mV_to_regval(vout_to_vref(3300 * 10, 5_2))
 266 #define VDD_IO_VAL_2_LP         mV_to_regval(vout_to_vref(3100 * 10, 5_2))
 267 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1425 * 10, 6))
 268 #define VDD_SOC_VAL_LP          mV_to_regval(vout_to_vref(900 * 10, 6))
 269 #define VDD_DDR_VAL             mV_to_regval(vout_to_vref(1500 * 10, 7))
 270 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1425 * 10, 8))
 271 #define VDD_CORE_VAL_LP         mV_to_regval(vout_to_vref(900 * 10, 8))
 272
 273 /* LDO1 */
 274 #define R1_1                    470
 275 #define R2_1                    150
 276 /* LDO4 */
 277 #define R1_4                    470
 278 #define R2_4                    150
 279 /* Buck1 */
 280 #define R1_5                    390
 281 #define R2_5                    110
 282 #define R1_5_2                  470
 283 #define R2_5_2                  150
 284 /* Buck2 */
 285 #define R1_6                    150
 286 #define R2_6                    180
 287 /* Buck3 */
 288 #define R1_7                    150
 289 #define R2_7                    140
 290 /* Buck4 */
 291 #define R1_8                    150
 292 #define R2_8                    180
 293
 294 /* calculate voltages in 10mV */
 295 #define R1(idx)                 R1_##idx
 296 #define R2(idx)                 R2_##idx
 297
 298 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
 299 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
 300
 301 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
 302 #define regval_to_mV(v)         (((v) * 125 + 4125))
 303
 304 static struct ltc3673_regs {
 305         u8 addr;
 306         u8 val;
 307         u8 mask;
 308 } ltc3676_regs[] = {
 309         { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
 310         { LTC3676_DVB2B, VDD_SOC_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
 311         { LTC3676_DVB3B, VDD_DDR_VAL, ~0x3f, },
 312         { LTC3676_DVB4B, VDD_CORE_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
 313         { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
 314         { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
 315         { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
 316         { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
 317         { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
 318         { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
 319         { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
 320         { LTC3676_CLIRQ, 0, }, /* clear interrupt status */
 321 };
 322
 323 static struct ltc3673_regs ltc3676_regs_1[] = {
 324         { LTC3676_DVB1B, VDD_IO_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
 325         { LTC3676_DVB1A, VDD_IO_VAL, ~0x3f, },
 326 };
 327
 328 static struct ltc3673_regs ltc3676_regs_2[] = {
 329         { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
 330         { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
 331 };
 332
 333 static int tx6_rev_2(void)
 334 {
 335         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 336         struct fuse_bank5_regs *fuse = (void *)ocotp->bank[5].fuse_regs;
 337         u32 pad_settings = readl(&fuse->pad_settings);
 338
 339         debug("Fuse pad_settings @ %p = %08x\n",
 340                 &fuse->pad_settings, pad_settings);
 341         return pad_settings & 1;
 342 }
 343
 344 static int tx6_ltc3676_setup_regs(struct ltc3673_regs *r, size_t count)
 345 {
 346         int ret;
 347         int i;
 348
 349         for (i = 0; i < count; i++, r++) {
 350 #ifdef DEBUG
 351                 unsigned char value;
 352
 353                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
 354                 if ((value & ~r->mask) != r->val) {
 355                         printf("Changing PMIC reg %02x from %02x to %02x\n",
 356                                 r->addr, value, r->val);
 357                 }
 358                 if (ret) {
 359                         printf("%s: failed to read PMIC register %02x: %d\n",
 360                                 __func__, r->addr, ret);
 361                         return ret;
 362                 }
 363 #endif
 364                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
 365                                 r->addr, 1, &r->val, 1);
 366                 if (ret) {
 367                         printf("%s: failed to write PMIC register %02x: %d\n",
 368                                 __func__, r->addr, ret);
 369                         return ret;
 370                 }
 371         }
 372         return 0;
 373 }
 374
 375 static int setup_pmic_voltages(void)
 376 {
 377         int ret;
 378         unsigned char value;
 379
 380         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
 381         if (ret != 0) {
 382                 printf("Failed to initialize I2C\n");
 383                 return ret;
 384         }
 385
 386         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
 387         if (ret) {
 388                 printf("%s: i2c_read error: %d\n", __func__, ret);
 389                 return ret;
 390         }
 391
 392         ret = tx6_ltc3676_setup_regs(ltc3676_regs, ARRAY_SIZE(ltc3676_regs));
 393         if (ret)
 394                 return ret;
 395
 396         printf("VDDCORE set to %umV\n",
 397                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 8), 10));
 398         printf("VDDSOC  set to %umV\n",
 399                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 6), 10));
 400
 401         if (tx6_rev_2()) {
 402                 ret = tx6_ltc3676_setup_regs(ltc3676_regs_2,
 403                                 ARRAY_SIZE(ltc3676_regs_2));
 404                 printf("VDDIO   set to %umV\n",
 405                         DIV_ROUND(vref_to_vout(
 406                                         regval_to_mV(VDD_IO_VAL_2), 5_2), 10));
 407         } else {
 408                 ret = tx6_ltc3676_setup_regs(ltc3676_regs_1,
 409                                 ARRAY_SIZE(ltc3676_regs_1));
 410         }
 411         return ret;
 412 }
 413
 414 int board_early_init_f(void)
 415 {
 416         gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 417         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 418
 419         return 0;
 420 }
 421
 422 int board_init(void)
 423 {
 424         int ret;
 425
 426         /* Address of boot parameters */
 427         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 428 #ifdef CONFIG_OF_LIBFDT
 429         gd->bd->bi_arch_number = -1;
 430 #else
 431         gd->bd->bi_arch_number = 4429;
 432 #endif
 433         if (ctrlc()) {
 434                 printf("CTRL-C detected; Skipping PMIC setup\n");
 435                 return 1;
 436         }
 437         ret = setup_pmic_voltages();
 438         if (ret) {
 439                 printf("Failed to setup PMIC voltages\n");
 440                 hang();
 441         }
 442         return 0;
 443 }
 444
 445 int dram_init(void)
 446 {
 447         /* dram_init must store complete ramsize in gd->ram_size */
 448         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 449                                 PHYS_SDRAM_1_SIZE);
 450         return 0;
 451 }
 452
 453 void dram_init_banksize(void)
 454 {
 455         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 456         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 457                         PHYS_SDRAM_1_SIZE);
 458 #if CONFIG_NR_DRAM_BANKS > 1
 459         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 460         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 461                         PHYS_SDRAM_2_SIZE);
 462 #endif
 463 }
 464
 465 #ifdef  CONFIG_CMD_MMC
 466 static const iomux_v3_cfg_t mmc0_pads[] = {
 467         MX6_PAD_SD1_CMD__USDHC1_CMD,
 468         MX6_PAD_SD1_CLK__USDHC1_CLK,
 469         MX6_PAD_SD1_DAT0__USDHC1_DAT0,
 470         MX6_PAD_SD1_DAT1__USDHC1_DAT1,
 471         MX6_PAD_SD1_DAT2__USDHC1_DAT2,
 472         MX6_PAD_SD1_DAT3__USDHC1_DAT3,
 473         /* SD1 CD */
 474         MX6_PAD_SD3_CMD__GPIO_7_2,
 475 };
 476
 477 static const iomux_v3_cfg_t mmc1_pads[] = {
 478         MX6_PAD_SD2_CMD__USDHC2_CMD,
 479         MX6_PAD_SD2_CLK__USDHC2_CLK,
 480         MX6_PAD_SD2_DAT0__USDHC2_DAT0,
 481         MX6_PAD_SD2_DAT1__USDHC2_DAT1,
 482         MX6_PAD_SD2_DAT2__USDHC2_DAT2,
 483         MX6_PAD_SD2_DAT3__USDHC2_DAT3,
 484         /* SD2 CD */
 485         MX6_PAD_SD3_CLK__GPIO_7_3,
 486 };
 487
 488 static struct tx6_esdhc_cfg {
 489         const iomux_v3_cfg_t *pads;
 490         int num_pads;
 491         enum mxc_clock clkid;
 492         struct fsl_esdhc_cfg cfg;
 493         int cd_gpio;
 494 } tx6qdl_esdhc_cfg[] = {
 495         {
 496                 .pads = mmc0_pads,
 497                 .num_pads = ARRAY_SIZE(mmc0_pads),
 498                 .clkid = MXC_ESDHC_CLK,
 499                 .cfg = {
 500                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 501                         .max_bus_width = 4,
 502                 },
 503                 .cd_gpio = IMX_GPIO_NR(7, 2),
 504         },
 505         {
 506                 .pads = mmc1_pads,
 507                 .num_pads = ARRAY_SIZE(mmc1_pads),
 508                 .clkid = MXC_ESDHC2_CLK,
 509                 .cfg = {
 510                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 511                         .max_bus_width = 4,
 512                 },
 513                 .cd_gpio = IMX_GPIO_NR(7, 3),
 514         },
 515 };
 516
 517 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 518 {
 519         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 520 }
 521
 522 int board_mmc_getcd(struct mmc *mmc)
 523 {
 524         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 525
 526         if (cfg->cd_gpio < 0)
 527                 return cfg->cd_gpio;
 528
 529         debug("SD card %d is %spresent\n",
 530                 cfg - tx6qdl_esdhc_cfg,
 531                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
 532         return !gpio_get_value(cfg->cd_gpio);
 533 }
 534
 535 int board_mmc_init(bd_t *bis)
 536 {
 537         int i;
 538
 539         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 540                 struct mmc *mmc;
 541                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 542                 int ret;
 543
 544                 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
 545                         break;
 546
 547                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 548                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 549
 550                 ret = gpio_request_one(cfg->cd_gpio,
 551                                 GPIOF_INPUT, "MMC CD");
 552                 if (ret) {
 553                         printf("Error %d requesting GPIO%d_%d\n",
 554                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 555                         continue;
 556                 }
 557
 558                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 559                 fsl_esdhc_initialize(bis, &cfg->cfg);
 560
 561                 mmc = find_mmc_device(i);
 562                 if (mmc == NULL)
 563                         continue;
 564                 if (board_mmc_getcd(mmc) > 0)
 565                         mmc_init(mmc);
 566         }
 567         return 0;
 568 }
 569 #endif /* CONFIG_CMD_MMC */
 570
 571 #ifdef CONFIG_FEC_MXC
 572
 573 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 574                         PAD_CTL_SRE_FAST)
 575 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 576 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 577
 578 #ifndef ETH_ALEN
 579 #define ETH_ALEN 6
 580 #endif
 581
 582 int board_eth_init(bd_t *bis)
 583 {
 584         int ret;
 585
 586         /* delay at least 21ms for the PHY internal POR signal to deassert */
 587         udelay(22000);
 588
 589         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads));
 590
 591         /* Deassert RESET to the external phy */
 592         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 593
 594         ret = cpu_eth_init(bis);
 595         if (ret)
 596                 printf("cpu_eth_init() failed: %d\n", ret);
 597
 598         return ret;
 599 }
 600 #endif /* CONFIG_FEC_MXC */
 601
 602 enum {
 603         LED_STATE_INIT = -1,
 604         LED_STATE_OFF,
 605         LED_STATE_ON,
 606 };
 607
 608 static inline int calc_blink_rate(int tmp)
 609 {
 610         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 611                 (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 612                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 613 }
 614
 615 void show_activity(int arg)
 616 {
 617         static int led_state = LED_STATE_INIT;
 618         static int blink_rate;
 619         static ulong last;
 620
 621         if (led_state == LED_STATE_INIT) {
 622                 last = get_timer(0);
 623                 gpio_set_value(TX6_LED_GPIO, 1);
 624                 led_state = LED_STATE_ON;
 625                 blink_rate = calc_blink_rate(check_cpu_temperature(0));
 626         } else {
 627                 if (get_timer(last) > blink_rate) {
 628                         blink_rate = calc_blink_rate(check_cpu_temperature(0));
 629                         last = get_timer_masked();
 630                         if (led_state == LED_STATE_ON) {
 631                                 gpio_set_value(TX6_LED_GPIO, 0);
 632                         } else {
 633                                 gpio_set_value(TX6_LED_GPIO, 1);
 634                         }
 635                         led_state = 1 - led_state;
 636                 }
 637         }
 638 }
 639
 640 static const iomux_v3_cfg_t stk5_pads[] = {
 641         /* SW controlled LED on STK5 baseboard */
 642         MX6_PAD_EIM_A18__GPIO_2_20,
 643
 644         /* LCD data pins */
 645         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 646         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 647         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 648         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 649         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 650         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 651         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 652         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 653         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 654         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 655         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 656         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 657         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 658         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 659         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 660         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 661         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 662         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 663         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 664         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 665         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 666         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 667         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 668         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 669         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */
 670         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */
 671         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 672         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 673
 674         /* I2C bus on DIMM pins 40/41 */
 675         MX6_PAD_GPIO_6__I2C3_SDA,
 676         MX6_PAD_GPIO_3__I2C3_SCL,
 677
 678         /* TSC200x PEN IRQ */
 679         MX6_PAD_EIM_D26__GPIO_3_26,
 680
 681         /* EDT-FT5x06 Polytouch panel */
 682         MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */
 683         MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */
 684         MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */
 685
 686         /* USBH1 */
 687         MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */
 688         MX6_PAD_EIM_D30__GPIO_3_30, /* OC */
 689         /* USBOTG */
 690         MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */
 691         MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */
 692         MX6_PAD_GPIO_8__GPIO_1_8, /* OC */
 693 };
 694
 695 static const struct gpio stk5_gpios[] = {
 696         { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 697
 698         { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", },
 699         { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
 700         { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 701         { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
 702         { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 703 };
 704
 705 #ifdef CONFIG_LCD
 706 vidinfo_t panel_info = {
 707         /* set to max. size supported by SoC */
 708         .vl_col = 1920,
 709         .vl_row = 1080,
 710
 711         .vl_bpix = LCD_COLOR24,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 712 };
 713
 714 static struct fb_videomode tx6_fb_modes[] = {
 715         {
 716                 /* Standard VGA timing */
 717                 .name           = "VGA",
 718                 .refresh        = 60,
 719                 .xres           = 640,
 720                 .yres           = 480,
 721                 .pixclock       = KHZ2PICOS(25175),
 722                 .left_margin    = 48,
 723                 .hsync_len      = 96,
 724                 .right_margin   = 16,
 725                 .upper_margin   = 31,
 726                 .vsync_len      = 2,
 727                 .lower_margin   = 12,
 728                 .sync           = FB_SYNC_CLK_LAT_FALL,
 729         },
 730         {
 731                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 732                  * DE high active, 115.2 mm x 86.4 mm display area
 733                  * VGA compatible timing
 734                  */
 735                 .name           = "ETV570",
 736                 .refresh        = 60,
 737                 .xres           = 640,
 738                 .yres           = 480,
 739                 .pixclock       = KHZ2PICOS(25175),
 740                 .left_margin    = 114,
 741                 .hsync_len      = 30,
 742                 .right_margin   = 16,
 743                 .upper_margin   = 32,
 744                 .vsync_len      = 3,
 745                 .lower_margin   = 10,
 746                 .sync           = FB_SYNC_CLK_LAT_FALL,
 747         },
 748         {
 749                 /* Emerging ET0350G0DH6 320 x 240 display.
 750                  * 70.08 mm x 52.56 mm display area.
 751                  */
 752                 .name           = "ET0350",
 753                 .refresh        = 60,
 754                 .xres           = 320,
 755                 .yres           = 240,
 756                 .pixclock       = KHZ2PICOS(6500),
 757                 .left_margin    = 68 - 34,
 758                 .hsync_len      = 34,
 759                 .right_margin   = 20,
 760                 .upper_margin   = 18 - 3,
 761                 .vsync_len      = 3,
 762                 .lower_margin   = 4,
 763                 .sync           = FB_SYNC_CLK_LAT_FALL,
 764         },
 765         {
 766                 /* Emerging ET0430G0DH6 480 x 272 display.
 767                  * 95.04 mm x 53.856 mm display area.
 768                  */
 769                 .name           = "ET0430",
 770                 .refresh        = 60,
 771                 .xres           = 480,
 772                 .yres           = 272,
 773                 .pixclock       = KHZ2PICOS(9000),
 774                 .left_margin    = 2,
 775                 .hsync_len      = 41,
 776                 .right_margin   = 2,
 777                 .upper_margin   = 2,
 778                 .vsync_len      = 10,
 779                 .lower_margin   = 2,
 780                 .sync           = FB_SYNC_CLK_LAT_FALL,
 781         },
 782         {
 783                 /* Emerging ET0500G0DH6 800 x 480 display.
 784                  * 109.6 mm x 66.4 mm display area.
 785                  */
 786                 .name           = "ET0500",
 787                 .refresh        = 60,
 788                 .xres           = 800,
 789                 .yres           = 480,
 790                 .pixclock       = KHZ2PICOS(33260),
 791                 .left_margin    = 216 - 128,
 792                 .hsync_len      = 128,
 793                 .right_margin   = 1056 - 800 - 216,
 794                 .upper_margin   = 35 - 2,
 795                 .vsync_len      = 2,
 796                 .lower_margin   = 525 - 480 - 35,
 797                 .sync           = FB_SYNC_CLK_LAT_FALL,
 798         },
 799         {
 800                 /* Emerging ETQ570G0DH6 320 x 240 display.
 801                  * 115.2 mm x 86.4 mm display area.
 802                  */
 803                 .name           = "ETQ570",
 804                 .refresh        = 60,
 805                 .xres           = 320,
 806                 .yres           = 240,
 807                 .pixclock       = KHZ2PICOS(6400),
 808                 .left_margin    = 38,
 809                 .hsync_len      = 30,
 810                 .right_margin   = 30,
 811                 .upper_margin   = 16, /* 15 according to datasheet */
 812                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 813                 .lower_margin   = 4, /* 4.5 according to datasheet */
 814                 .sync           = FB_SYNC_CLK_LAT_FALL,
 815         },
 816         {
 817                 /* Emerging ET0700G0DH6 800 x 480 display.
 818                  * 152.4 mm x 91.44 mm display area.
 819                  */
 820                 .name           = "ET0700",
 821                 .refresh        = 60,
 822                 .xres           = 800,
 823                 .yres           = 480,
 824                 .pixclock       = KHZ2PICOS(33260),
 825                 .left_margin    = 216 - 128,
 826                 .hsync_len      = 128,
 827                 .right_margin   = 1056 - 800 - 216,
 828                 .upper_margin   = 35 - 2,
 829                 .vsync_len      = 2,
 830                 .lower_margin   = 525 - 480 - 35,
 831                 .sync           = FB_SYNC_CLK_LAT_FALL,
 832         },
 833         {
 834                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 835                 .refresh        = 60,
 836                 .left_margin    = 48,
 837                 .hsync_len      = 96,
 838                 .right_margin   = 16,
 839                 .upper_margin   = 31,
 840                 .vsync_len      = 2,
 841                 .lower_margin   = 12,
 842                 .sync           = FB_SYNC_CLK_LAT_FALL,
 843         },
 844 };
 845
 846 static int lcd_enabled = 1;
 847
 848 void lcd_enable(void)
 849 {
 850         /* HACK ALERT:
 851          * global variable from common/lcd.c
 852          * Set to 0 here to prevent messages from going to LCD
 853          * rather than serial console
 854          */
 855         lcd_is_enabled = 0;
 856
 857         karo_load_splashimage(1);
 858
 859         if (lcd_enabled) {
 860                 debug("Switching LCD on\n");
 861                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 862                 udelay(100);
 863                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 864                 udelay(300000);
 865                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
 866         }
 867 }
 868
 869 void lcd_disable(void)
 870 {
 871         if (lcd_enabled) {
 872                 printf("Disabling LCD\n");
 873                 ipuv3_fb_shutdown();
 874         }
 875 }
 876
 877 void lcd_panel_disable(void)
 878 {
 879         if (lcd_enabled) {
 880                 debug("Switching LCD off\n");
 881                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1);
 882                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 883                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 884         }
 885 }
 886
 887 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 888         /* LCD RESET */
 889         MX6_PAD_EIM_D29__GPIO_3_29,
 890         /* LCD POWER_ENABLE */
 891         MX6_PAD_EIM_EB3__GPIO_2_31,
 892         /* LCD Backlight (PWM) */
 893         MX6_PAD_GPIO_1__GPIO_1_1,
 894
 895         /* Display */
 896         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 897         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 898         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 899         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 900         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 901         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 902         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 903         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 904         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 905         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 906         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 907         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 908         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 909         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 910         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 911         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 912         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 913         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 914         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 915         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 916         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 917         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 918         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 919         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 920         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 921         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 922         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 923         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 924 };
 925
 926 static const struct gpio stk5_lcd_gpios[] = {
 927         { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
 928         { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
 929         { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 930 };
 931
 932 void lcd_ctrl_init(void *lcdbase)
 933 {
 934         int color_depth = 24;
 935         const char *video_mode = getenv("video_mode");
 936         const char *vm;
 937         unsigned long val;
 938         int refresh = 60;
 939         struct fb_videomode *p = &tx6_fb_modes[0];
 940         struct fb_videomode fb_mode;
 941         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 942         int pix_fmt = 0;
 943         ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
 944         unsigned long di_clk_rate = 65000000;
 945
 946         if (!lcd_enabled) {
 947                 debug("LCD disabled\n");
 948                 return;
 949         }
 950
 951         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 952                 debug("Disabling LCD\n");
 953                 lcd_enabled = 0;
 954                 setenv("splashimage", NULL);
 955                 return;
 956         }
 957
 958         karo_fdt_move_fdt();
 959
 960         vm = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
 961         if (vm == NULL) {
 962                 debug("Disabling LCD\n");
 963                 lcd_enabled = 0;
 964                 return;
 965         }
 966         video_mode = vm;
 967         if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
 968                 p = &fb_mode;
 969                 debug("Using video mode from FDT\n");
 970                 vm += strlen(vm);
 971                 if (fb_mode.xres > panel_info.vl_col ||
 972                         fb_mode.yres > panel_info.vl_row) {
 973                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 974                                 fb_mode.xres, fb_mode.yres,
 975                                 panel_info.vl_col, panel_info.vl_row);
 976                         lcd_enabled = 0;
 977                         return;
 978                 }
 979         }
 980         if (p->name != NULL)
 981                 debug("Trying compiled-in video modes\n");
 982         while (p->name != NULL) {
 983                 if (strcmp(p->name, vm) == 0) {
 984                         debug("Using video mode: '%s'\n", p->name);
 985                         vm += strlen(vm);
 986                         break;
 987                 }
 988                 p++;
 989         }
 990         if (*vm != '\0')
 991                 debug("Trying to decode video_mode: '%s'\n", vm);
 992         while (*vm != '\0') {
 993                 if (*vm >= '0' && *vm <= '9') {
 994                         char *end;
 995
 996                         val = simple_strtoul(vm, &end, 0);
 997                         if (end > vm) {
 998                                 if (!xres_set) {
 999                                         if (val > panel_info.vl_col)
1000                                                 val = panel_info.vl_col;
1001                                         p->xres = val;
1002                                         panel_info.vl_col = val;
1003                                         xres_set = 1;
1004                                 } else if (!yres_set) {
1005                                         if (val > panel_info.vl_row)
1006                                                 val = panel_info.vl_row;
1007                                         p->yres = val;
1008                                         panel_info.vl_row = val;
1009                                         yres_set = 1;
1010                                 } else if (!bpp_set) {
1011                                         switch (val) {
1012                                         case 32:
1013                                         case 24:
1014                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666)
1015                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1016                                                 /* fallthru */
1017                                         case 16:
1018                                         case 8:
1019                                                 color_depth = val;
1020                                                 break;
1021
1022                                         case 18:
1023                                                 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1024                                                         color_depth = val;
1025                                                         break;
1026                                                 }
1027                                                 /* fallthru */
1028                                         default:
1029                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1030                                                         end - vm, vm, color_depth);
1031                                         }
1032                                         bpp_set = 1;
1033                                 } else if (!refresh_set) {
1034                                         refresh = val;
1035                                         refresh_set = 1;
1036                                 }
1037                         }
1038                         vm = end;
1039                 }
1040                 switch (*vm) {
1041                 case '@':
1042                         bpp_set = 1;
1043                         /* fallthru */
1044                 case '-':
1045                         yres_set = 1;
1046                         /* fallthru */
1047                 case 'x':
1048                         xres_set = 1;
1049                         /* fallthru */
1050                 case 'M':
1051                 case 'R':
1052                         vm++;
1053                         break;
1054
1055                 default:
1056                         if (!pix_fmt) {
1057                                 char *tmp;
1058
1059                                 if (strncmp(vm, "LVDS", 4) == 0) {
1060                                         pix_fmt = IPU_PIX_FMT_LVDS666;
1061                                         di_clk_parent = DI_PCLK_LDB;
1062                                 } else {
1063                                         pix_fmt = IPU_PIX_FMT_RGB24;
1064                                 }
1065                                 tmp = strchr(vm, ':');
1066                                 if (tmp)
1067                                         vm = tmp;
1068                         }
1069                         if (*vm != '\0')
1070                                 vm++;
1071                 }
1072         }
1073         if (p->xres == 0 || p->yres == 0) {
1074                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1075                 lcd_enabled = 0;
1076                 printf("Supported video modes are:");
1077                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1078                         printf(" %s", p->name);
1079                 }
1080                 printf("\n");
1081                 return;
1082         }
1083         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1084                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1085                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1086                 lcd_enabled = 0;
1087                 return;
1088         }
1089         panel_info.vl_col = p->xres;
1090         panel_info.vl_row = p->yres;
1091
1092         switch (color_depth) {
1093         case 8:
1094                 panel_info.vl_bpix = LCD_COLOR8;
1095                 break;
1096         case 16:
1097                 panel_info.vl_bpix = LCD_COLOR16;
1098                 break;
1099         default:
1100                 panel_info.vl_bpix = LCD_COLOR24;
1101         }
1102
1103         p->pixclock = KHZ2PICOS(refresh *
1104                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1105                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
1106                 / 1000);
1107         debug("Pixel clock set to %lu.%03lu MHz\n",
1108                 PICOS2KHZ(p->pixclock) / 1000,
1109                 PICOS2KHZ(p->pixclock) % 1000);
1110
1111         if (p != &fb_mode) {
1112                 int ret;
1113
1114                 debug("Creating new display-timing node from '%s'\n",
1115                         video_mode);
1116                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1117                 if (ret)
1118                         printf("Failed to create new display-timing node from '%s': %d\n",
1119                                 video_mode, ret);
1120         }
1121
1122         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1123         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1124                                         ARRAY_SIZE(stk5_lcd_pads));
1125
1126         debug("Initializing FB driver\n");
1127         if (!pix_fmt)
1128                 pix_fmt = IPU_PIX_FMT_RGB24;
1129         else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
1130                 writel(0x01, IOMUXC_BASE_ADDR + 8);
1131         } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
1132                 writel(0x21, IOMUXC_BASE_ADDR + 8);
1133         }
1134         if (pix_fmt != IPU_PIX_FMT_RGB24) {
1135                 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1136                 /* enable LDB & DI0 clock */
1137                 writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
1138                         MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
1139                         &ccm_regs->CCGR3);
1140         }
1141
1142         if (karo_load_splashimage(0) == 0) {
1143                 debug("Initializing LCD controller\n");
1144                 ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1145         } else {
1146                 debug("Skipping initialization of LCD controller\n");
1147         }
1148 }
1149 #else
1150 #define lcd_enabled 0
1151 #endif /* CONFIG_LCD */
1152
1153 static void stk5_board_init(void)
1154 {
1155         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1156         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1157 }
1158
1159 static void stk5v3_board_init(void)
1160 {
1161         stk5_board_init();
1162 }
1163
1164 static void stk5v5_board_init(void)
1165 {
1166         stk5_board_init();
1167
1168         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
1169                         "Flexcan Transceiver");
1170         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21);
1171 }
1172
1173 static void tx6qdl_set_cpu_clock(void)
1174 {
1175         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1176
1177         if (had_ctrlc() || (wrsr & WRSR_TOUT))
1178                 return;
1179
1180         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1181                 return;
1182
1183         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1184                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1185                 printf("CPU clock set to %lu.%03lu MHz\n",
1186                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1187         } else {
1188                 printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
1189         }
1190 }
1191
1192 static void tx6_init_mac(void)
1193 {
1194         u8 mac[ETH_ALEN];
1195
1196         imx_get_mac_from_fuse(-1, mac);
1197         if (!is_valid_ether_addr(mac)) {
1198                 printf("No valid MAC address programmed\n");
1199                 return;
1200         }
1201
1202         eth_setenv_enetaddr("ethaddr", mac);
1203         printf("MAC addr from fuse: %pM\n", mac);
1204 }
1205
1206 int board_late_init(void)
1207 {
1208         int ret = 0;
1209         const char *baseboard;
1210
1211         tx6qdl_set_cpu_clock();
1212         karo_fdt_move_fdt();
1213
1214         baseboard = getenv("baseboard");
1215         if (!baseboard)
1216                 goto exit;
1217
1218         printf("Baseboard: %s\n", baseboard);
1219
1220         if (strncmp(baseboard, "stk5", 4) == 0) {
1221                 if ((strlen(baseboard) == 4) ||
1222                         strcmp(baseboard, "stk5-v3") == 0) {
1223                         stk5v3_board_init();
1224                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1225                         const char *otg_mode = getenv("otg_mode");
1226
1227                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1228                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1229                                         otg_mode, baseboard);
1230                                 setenv("otg_mode", "none");
1231                         }
1232                         stk5v5_board_init();
1233                 } else {
1234                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1235                                 baseboard + 4);
1236                 }
1237         } else {
1238                 printf("WARNING: Unsupported baseboard: '%s'\n",
1239                         baseboard);
1240                 ret = -EINVAL;
1241         }
1242
1243 exit:
1244         tx6_init_mac();
1245
1246         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1247         clear_ctrlc();
1248         return ret;
1249 }
1250
1251 int checkboard(void)
1252 {
1253         u32 cpurev = get_cpu_rev();
1254         int cpu_variant = (cpurev >> 12) & 0xff;
1255
1256         tx6qdl_print_cpuinfo();
1257
1258         printf("Board: Ka-Ro TX6%c-%dx1%d\n",
1259                 cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
1260                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1261                 1 - PHYS_SDRAM_1_WIDTH / 64);
1262
1263         return 0;
1264 }
1265
1266 #ifdef CONFIG_SERIAL_TAG
1267 void get_board_serial(struct tag_serialnr *serialnr)
1268 {
1269         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1270         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1271
1272         serialnr->low = readl(&fuse->cfg0);
1273         serialnr->high = readl(&fuse->cfg1);
1274 }
1275 #endif
1276
1277 #if defined(CONFIG_OF_BOARD_SETUP)
1278 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1279 #include <jffs2/jffs2.h>
1280 #include <mtd_node.h>
1281 static struct node_info nodes[] = {
1282         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1283 };
1284
1285 #else
1286 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1287 #endif
1288
1289 void ft_board_setup(void *blob, bd_t *bd)
1290 {
1291         const char *baseboard = getenv("baseboard");
1292         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1293         const char *video_mode = getenv("video_mode");
1294
1295         karo_fdt_enable_node(blob, "stk5led", !stk5_v5);
1296
1297         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1298         fdt_fixup_ethernet(blob);
1299
1300         karo_fdt_fixup_touchpanel(blob);
1301         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
1302         karo_fdt_fixup_flexcan(blob, stk5_v5);
1303
1304         video_mode = karo_fdt_set_display(video_mode, "", "/soc/aips-bus/ldb");
1305         karo_fdt_update_fb_mode(blob, video_mode);
1306 }
1307 #endif /* CONFIG_OF_BOARD_SETUP */