board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17 #include <common.h>
  18 #include <errno.h>
  19 #include <libfdt.h>
  20 #include <fdt_support.h>
  21 #include <lcd.h>
  22 #include <netdev.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <video_fb.h>
  26 #include <ipu.h>
  27 #include <mxcfb.h>
  28 #include <i2c.h>
  29 #include <linux/fb.h>
  30 #include <asm/io.h>
  31 #include <asm/gpio.h>
  32 #include <asm/arch/mx6-pins.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/imx-regs.h>
  35 #include <asm/arch/crm_regs.h>
  36 #include <asm/arch/sys_proto.h>
  37
  38 #include "../common/karo.h"
  39 #include "pmic.h"
  40
  41 #define __data __attribute__((section(".data")))
  42
  43 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  44 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  45 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  46 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  47
  48 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  49 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  50 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  51
  52 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 enum {
  70         MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
  71 };
  72
  73 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  74         /* RESET_OUT */
  75         MX6_PAD_GPIO_17__GPIO7_IO12,
  76
  77         /* UART pads */
  78 #if CONFIG_MXC_UART_BASE == UART1_BASE
  79         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
  80         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
  81         MX6_PAD_SD3_DAT1__UART1_RTS_B,
  82         MX6_PAD_SD3_DAT0__UART1_CTS_B,
  83 #endif
  84 #if CONFIG_MXC_UART_BASE == UART2_BASE
  85         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
  86         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
  87         MX6_PAD_SD4_DAT5__UART2_RTS_B,
  88         MX6_PAD_SD4_DAT6__UART2_CTS_B,
  89 #endif
  90 #if CONFIG_MXC_UART_BASE == UART3_BASE
  91         MX6_PAD_EIM_D24__UART3_TX_DATA,
  92         MX6_PAD_EIM_D25__UART3_RX_DATA,
  93         MX6_PAD_SD3_RST__UART3_RTS_B,
  94         MX6_PAD_SD3_DAT3__UART3_CTS_B,
  95 #endif
  96         /* internal I2C */
  97         MX6_PAD_EIM_D28__I2C1_SDA,
  98         MX6_PAD_EIM_D21__I2C1_SCL,
  99
 100         /* FEC PHY GPIO functions */
 101         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
 102         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
 103         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
 104 };
 105
 106 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 107         /* FEC functions */
 108         MX6_PAD_ENET_MDC__ENET_MDC,
 109         MX6_PAD_ENET_MDIO__ENET_MDIO,
 110         MX6_PAD_GPIO_16__ENET_REF_CLK,
 111         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 112         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 113         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
 114         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
 115         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 116         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
 117         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 118 };
 119
 120 static const struct gpio const tx6qdl_gpios[] = {
 121         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 122         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 123         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 124         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 125 };
 126
 127 /*
 128  * Functions
 129  */
 130 /* placed in section '.data' to prevent overwriting relocation info
 131  * overlayed with bss
 132  */
 133 static u32 wrsr __attribute__((section(".data")));
 134
 135 #define WRSR_POR                        (1 << 4)
 136 #define WRSR_TOUT                       (1 << 1)
 137 #define WRSR_SFTW                       (1 << 0)
 138
 139 static void print_reset_cause(void)
 140 {
 141         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 142         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 143         u32 srsr;
 144         char *dlm = "";
 145
 146         printf("Reset cause: ");
 147
 148         srsr = readl(&src_regs->srsr);
 149         wrsr = readw(wdt_base + 4);
 150
 151         if (wrsr & WRSR_POR) {
 152                 printf("%sPOR", dlm);
 153                 dlm = " | ";
 154         }
 155         if (srsr & 0x00004) {
 156                 printf("%sCSU", dlm);
 157                 dlm = " | ";
 158         }
 159         if (srsr & 0x00008) {
 160                 printf("%sIPP USER", dlm);
 161                 dlm = " | ";
 162         }
 163         if (srsr & 0x00010) {
 164                 if (wrsr & WRSR_SFTW) {
 165                         printf("%sSOFT", dlm);
 166                         dlm = " | ";
 167                 }
 168                 if (wrsr & WRSR_TOUT) {
 169                         printf("%sWDOG", dlm);
 170                         dlm = " | ";
 171                 }
 172         }
 173         if (srsr & 0x00020) {
 174                 printf("%sJTAG HIGH-Z", dlm);
 175                 dlm = " | ";
 176         }
 177         if (srsr & 0x00040) {
 178                 printf("%sJTAG SW", dlm);
 179                 dlm = " | ";
 180         }
 181         if (srsr & 0x10000) {
 182                 printf("%sWARM BOOT", dlm);
 183                 dlm = " | ";
 184         }
 185         if (dlm[0] == '\0')
 186                 printf("unknown");
 187
 188         printf("\n");
 189 }
 190
 191 static const char __data *tx6_mod_suffix;
 192
 193 static void tx6qdl_print_cpuinfo(void)
 194 {
 195         u32 cpurev = get_cpu_rev();
 196         char *cpu_str = "?";
 197
 198         switch ((cpurev >> 12) & 0xff) {
 199         case MXC_CPU_MX6SL:
 200                 cpu_str = "SL";
 201                 tx6_mod_suffix = "?";
 202                 break;
 203         case MXC_CPU_MX6DL:
 204                 cpu_str = "DL";
 205                 tx6_mod_suffix = "U";
 206                 break;
 207         case MXC_CPU_MX6SOLO:
 208                 cpu_str = "SOLO";
 209                 tx6_mod_suffix = "S";
 210                 break;
 211         case MXC_CPU_MX6Q:
 212                 cpu_str = "Q";
 213                 tx6_mod_suffix = "Q";
 214                 break;
 215         }
 216
 217         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 218                 cpu_str,
 219                 (cpurev & 0x000F0) >> 4,
 220                 (cpurev & 0x0000F) >> 0,
 221                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 222
 223         print_reset_cause();
 224 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 225         check_cpu_temperature(1);
 226 #endif
 227 }
 228
 229 int board_early_init_f(void)
 230 {
 231         return 0;
 232 }
 233
 234 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 235 static bool tx6_temp_check_enabled = true;
 236 #else
 237 #define tx6_temp_check_enabled  0
 238 #endif
 239
 240 int board_init(void)
 241 {
 242         int ret;
 243
 244         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 245         if (ret < 0) {
 246                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
 247         }
 248         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 249
 250         /* Address of boot parameters */
 251         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 252         gd->bd->bi_arch_number = -1;
 253
 254         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 255                 if (wrsr & WRSR_TOUT)
 256                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 257                 else
 258                         printf("<CTRL-C> detected; safeboot enabled\n");
 259 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 260                 tx6_temp_check_enabled = false;
 261 #endif
 262                 return 0;
 263         }
 264
 265         ret = tx6_pmic_init();
 266         if (ret) {
 267                 printf("Failed to setup PMIC voltages: %d\n", ret);
 268                 hang();
 269         }
 270         return 0;
 271 }
 272
 273 int dram_init(void)
 274 {
 275         /* dram_init must store complete ramsize in gd->ram_size */
 276         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 277                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 278         return 0;
 279 }
 280
 281 void dram_init_banksize(void)
 282 {
 283         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 284         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 285                         PHYS_SDRAM_1_SIZE);
 286 #if CONFIG_NR_DRAM_BANKS > 1
 287         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 288         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 289                         PHYS_SDRAM_2_SIZE);
 290 #endif
 291 }
 292
 293 #ifdef  CONFIG_FSL_ESDHC
 294 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
 295         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
 296         PAD_CTL_SRE_FAST)
 297
 298 static const iomux_v3_cfg_t mmc0_pads[] = {
 299         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 300         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 301         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 302         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 303         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 304         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 305         /* SD1 CD */
 306         MX6_PAD_SD3_CMD__GPIO7_IO02,
 307 };
 308
 309 static const iomux_v3_cfg_t mmc1_pads[] = {
 310         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 311         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 312         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 313         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 314         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 315         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 316         /* SD2 CD */
 317         MX6_PAD_SD3_CLK__GPIO7_IO03,
 318 };
 319
 320 #ifdef CONFIG_TX6_EMMC
 321 static const iomux_v3_cfg_t mmc3_pads[] = {
 322         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 323         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 324         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 325         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 326         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 327         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 328         /* eMMC RESET */
 329         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 330                                                 PAD_CTL_DSE_40ohm),
 331 };
 332 #endif
 333
 334 static struct tx6_esdhc_cfg {
 335         const iomux_v3_cfg_t *pads;
 336         int num_pads;
 337         enum mxc_clock clkid;
 338         struct fsl_esdhc_cfg cfg;
 339         int cd_gpio;
 340 } tx6qdl_esdhc_cfg[] = {
 341 #ifdef CONFIG_TX6_EMMC
 342         {
 343                 .pads = mmc3_pads,
 344                 .num_pads = ARRAY_SIZE(mmc3_pads),
 345                 .clkid = MXC_ESDHC4_CLK,
 346                 .cfg = {
 347                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 348                         .max_bus_width = 4,
 349                 },
 350                 .cd_gpio = -EINVAL,
 351         },
 352 #endif
 353         {
 354                 .pads = mmc0_pads,
 355                 .num_pads = ARRAY_SIZE(mmc0_pads),
 356                 .clkid = MXC_ESDHC_CLK,
 357                 .cfg = {
 358                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 359                         .max_bus_width = 4,
 360                 },
 361                 .cd_gpio = IMX_GPIO_NR(7, 2),
 362         },
 363         {
 364                 .pads = mmc1_pads,
 365                 .num_pads = ARRAY_SIZE(mmc1_pads),
 366                 .clkid = MXC_ESDHC2_CLK,
 367                 .cfg = {
 368                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 369                         .max_bus_width = 4,
 370                 },
 371                 .cd_gpio = IMX_GPIO_NR(7, 3),
 372         },
 373 };
 374
 375 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 376 {
 377         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 378 }
 379
 380 int board_mmc_getcd(struct mmc *mmc)
 381 {
 382         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 383
 384         if (cfg->cd_gpio < 0)
 385                 return 1;
 386
 387         debug("SD card %d is %spresent (GPIO %d)\n",
 388                 cfg - tx6qdl_esdhc_cfg,
 389                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 390                 cfg->cd_gpio);
 391         return !gpio_get_value(cfg->cd_gpio);
 392 }
 393
 394 int board_mmc_init(bd_t *bis)
 395 {
 396         int i;
 397
 398         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 399                 struct mmc *mmc;
 400                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 401                 int ret;
 402
 403                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 404                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 405
 406                 if (cfg->cd_gpio >= 0) {
 407                         ret = gpio_request_one(cfg->cd_gpio,
 408                                         GPIOFLAG_INPUT, "MMC CD");
 409                         if (ret) {
 410                                 printf("Error %d requesting GPIO%d_%d\n",
 411                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 412                                 continue;
 413                         }
 414                 }
 415
 416                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 417                 fsl_esdhc_initialize(bis, &cfg->cfg);
 418
 419                 mmc = find_mmc_device(i);
 420                 if (mmc == NULL)
 421                         continue;
 422                 if (board_mmc_getcd(mmc))
 423                         mmc_init(mmc);
 424         }
 425         return 0;
 426 }
 427 #endif /* CONFIG_CMD_MMC */
 428
 429 #ifdef CONFIG_FEC_MXC
 430
 431 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 432                         PAD_CTL_SRE_FAST)
 433 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 434 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 435
 436 #ifndef ETH_ALEN
 437 #define ETH_ALEN 6
 438 #endif
 439
 440 int board_eth_init(bd_t *bis)
 441 {
 442         int ret;
 443
 444         /* delay at least 21ms for the PHY internal POR signal to deassert */
 445         udelay(22000);
 446
 447         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 448                                         ARRAY_SIZE(tx6qdl_fec_pads));
 449
 450         /* Deassert RESET to the external phy */
 451         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 452
 453         ret = cpu_eth_init(bis);
 454         if (ret)
 455                 printf("cpu_eth_init() failed: %d\n", ret);
 456
 457         return ret;
 458 }
 459
 460 static void tx6_init_mac(void)
 461 {
 462         u8 mac[ETH_ALEN];
 463
 464         imx_get_mac_from_fuse(-1, mac);
 465         if (!is_valid_ether_addr(mac)) {
 466                 printf("No valid MAC address programmed\n");
 467                 return;
 468         }
 469
 470         printf("MAC addr from fuse: %pM\n", mac);
 471         eth_setenv_enetaddr("ethaddr", mac);
 472 }
 473 #else
 474 static inline void tx6_init_mac(void)
 475 {
 476 }
 477 #endif /* CONFIG_FEC_MXC */
 478
 479 enum {
 480         LED_STATE_INIT = -1,
 481         LED_STATE_OFF,
 482         LED_STATE_ON,
 483 };
 484
 485 static inline int calc_blink_rate(void)
 486 {
 487         if (!tx6_temp_check_enabled)
 488                 return CONFIG_SYS_HZ;
 489
 490         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 491                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 492                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 493 }
 494
 495 void show_activity(int arg)
 496 {
 497         static int led_state = LED_STATE_INIT;
 498         static int blink_rate;
 499         static ulong last;
 500
 501         if (led_state == LED_STATE_INIT) {
 502                 last = get_timer(0);
 503                 gpio_set_value(TX6_LED_GPIO, 1);
 504                 led_state = LED_STATE_ON;
 505                 blink_rate = calc_blink_rate();
 506         } else {
 507                 if (get_timer(last) > blink_rate) {
 508                         blink_rate = calc_blink_rate();
 509                         last = get_timer_masked();
 510                         if (led_state == LED_STATE_ON) {
 511                                 gpio_set_value(TX6_LED_GPIO, 0);
 512                         } else {
 513                                 gpio_set_value(TX6_LED_GPIO, 1);
 514                         }
 515                         led_state = 1 - led_state;
 516                 }
 517         }
 518 }
 519
 520 static const iomux_v3_cfg_t stk5_pads[] = {
 521         /* SW controlled LED on STK5 baseboard */
 522         MX6_PAD_EIM_A18__GPIO2_IO20,
 523
 524         /* I2C bus on DIMM pins 40/41 */
 525         MX6_PAD_GPIO_6__I2C3_SDA,
 526         MX6_PAD_GPIO_3__I2C3_SCL,
 527
 528         /* TSC200x PEN IRQ */
 529         MX6_PAD_EIM_D26__GPIO3_IO26,
 530
 531         /* EDT-FT5x06 Polytouch panel */
 532         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
 533         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
 534         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
 535
 536         /* USBH1 */
 537         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
 538         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
 539         /* USBOTG */
 540         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
 541         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
 542         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
 543 };
 544
 545 static const struct gpio stk5_gpios[] = {
 546         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 547
 548         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 549         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 550         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 551         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 552         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 553 };
 554
 555 #ifdef CONFIG_LCD
 556 static u16 tx6_cmap[256];
 557 vidinfo_t panel_info = {
 558         /* set to max. size supported by SoC */
 559         .vl_col = 1920,
 560         .vl_row = 1080,
 561
 562         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 563         .cmap = tx6_cmap,
 564 };
 565
 566 static struct fb_videomode tx6_fb_modes[] = {
 567 #ifndef CONFIG_SYS_LVDS_IF
 568         {
 569                 /* Standard VGA timing */
 570                 .name           = "VGA",
 571                 .refresh        = 60,
 572                 .xres           = 640,
 573                 .yres           = 480,
 574                 .pixclock       = KHZ2PICOS(25175),
 575                 .left_margin    = 48,
 576                 .hsync_len      = 96,
 577                 .right_margin   = 16,
 578                 .upper_margin   = 31,
 579                 .vsync_len      = 2,
 580                 .lower_margin   = 12,
 581                 .sync           = FB_SYNC_CLK_LAT_FALL,
 582         },
 583         {
 584                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 585                  * DE high active, 115.2 mm x 86.4 mm display area
 586                  * VGA compatible timing
 587                  */
 588                 .name           = "ETV570",
 589                 .refresh        = 60,
 590                 .xres           = 640,
 591                 .yres           = 480,
 592                 .pixclock       = KHZ2PICOS(25175),
 593                 .left_margin    = 114,
 594                 .hsync_len      = 30,
 595                 .right_margin   = 16,
 596                 .upper_margin   = 32,
 597                 .vsync_len      = 3,
 598                 .lower_margin   = 10,
 599                 .sync           = FB_SYNC_CLK_LAT_FALL,
 600         },
 601         {
 602                 /* Emerging ET0350G0DH6 320 x 240 display.
 603                  * 70.08 mm x 52.56 mm display area.
 604                  */
 605                 .name           = "ET0350",
 606                 .refresh        = 60,
 607                 .xres           = 320,
 608                 .yres           = 240,
 609                 .pixclock       = KHZ2PICOS(6500),
 610                 .left_margin    = 68 - 34,
 611                 .hsync_len      = 34,
 612                 .right_margin   = 20,
 613                 .upper_margin   = 18 - 3,
 614                 .vsync_len      = 3,
 615                 .lower_margin   = 4,
 616                 .sync           = FB_SYNC_CLK_LAT_FALL,
 617         },
 618         {
 619                 /* Emerging ET0430G0DH6 480 x 272 display.
 620                  * 95.04 mm x 53.856 mm display area.
 621                  */
 622                 .name           = "ET0430",
 623                 .refresh        = 60,
 624                 .xres           = 480,
 625                 .yres           = 272,
 626                 .pixclock       = KHZ2PICOS(9000),
 627                 .left_margin    = 2,
 628                 .hsync_len      = 41,
 629                 .right_margin   = 2,
 630                 .upper_margin   = 2,
 631                 .vsync_len      = 10,
 632                 .lower_margin   = 2,
 633         },
 634         {
 635                 /* Emerging ET0500G0DH6 800 x 480 display.
 636                  * 109.6 mm x 66.4 mm display area.
 637                  */
 638                 .name           = "ET0500",
 639                 .refresh        = 60,
 640                 .xres           = 800,
 641                 .yres           = 480,
 642                 .pixclock       = KHZ2PICOS(33260),
 643                 .left_margin    = 216 - 128,
 644                 .hsync_len      = 128,
 645                 .right_margin   = 1056 - 800 - 216,
 646                 .upper_margin   = 35 - 2,
 647                 .vsync_len      = 2,
 648                 .lower_margin   = 525 - 480 - 35,
 649                 .sync           = FB_SYNC_CLK_LAT_FALL,
 650         },
 651         {
 652                 /* Emerging ETQ570G0DH6 320 x 240 display.
 653                  * 115.2 mm x 86.4 mm display area.
 654                  */
 655                 .name           = "ETQ570",
 656                 .refresh        = 60,
 657                 .xres           = 320,
 658                 .yres           = 240,
 659                 .pixclock       = KHZ2PICOS(6400),
 660                 .left_margin    = 38,
 661                 .hsync_len      = 30,
 662                 .right_margin   = 30,
 663                 .upper_margin   = 16, /* 15 according to datasheet */
 664                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 665                 .lower_margin   = 4, /* 4.5 according to datasheet */
 666                 .sync           = FB_SYNC_CLK_LAT_FALL,
 667         },
 668         {
 669                 /* Emerging ET0700G0DH6 800 x 480 display.
 670                  * 152.4 mm x 91.44 mm display area.
 671                  */
 672                 .name           = "ET0700",
 673                 .refresh        = 60,
 674                 .xres           = 800,
 675                 .yres           = 480,
 676                 .pixclock       = KHZ2PICOS(33260),
 677                 .left_margin    = 216 - 128,
 678                 .hsync_len      = 128,
 679                 .right_margin   = 1056 - 800 - 216,
 680                 .upper_margin   = 35 - 2,
 681                 .vsync_len      = 2,
 682                 .lower_margin   = 525 - 480 - 35,
 683                 .sync           = FB_SYNC_CLK_LAT_FALL,
 684         },
 685         {
 686                 /* Emerging ET070001DM6 800 x 480 display.
 687                  * 152.4 mm x 91.44 mm display area.
 688                  */
 689                 .name           = "ET070001DM6",
 690                 .refresh        = 60,
 691                 .xres           = 800,
 692                 .yres           = 480,
 693                 .pixclock       = KHZ2PICOS(33260),
 694                 .left_margin    = 216 - 128,
 695                 .hsync_len      = 128,
 696                 .right_margin   = 1056 - 800 - 216,
 697                 .upper_margin   = 35 - 2,
 698                 .vsync_len      = 2,
 699                 .lower_margin   = 525 - 480 - 35,
 700                 .sync           = 0,
 701         },
 702 #else
 703         {
 704                 /* HannStar HSD100PXN1
 705                  * 202.7m mm x 152.06 mm display area.
 706                  */
 707                 .name           = "HSD100PXN1",
 708                 .refresh        = 60,
 709                 .xres           = 1024,
 710                 .yres           = 768,
 711                 .pixclock       = KHZ2PICOS(65000),
 712                 .left_margin    = 0,
 713                 .hsync_len      = 0,
 714                 .right_margin   = 320,
 715                 .upper_margin   = 0,
 716                 .vsync_len      = 0,
 717                 .lower_margin   = 38,
 718                 .sync           = FB_SYNC_CLK_LAT_FALL,
 719         },
 720 #endif
 721         {
 722                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 723                 .refresh        = 60,
 724                 .left_margin    = 48,
 725                 .hsync_len      = 96,
 726                 .right_margin   = 16,
 727                 .upper_margin   = 31,
 728                 .vsync_len      = 2,
 729                 .lower_margin   = 12,
 730                 .sync           = FB_SYNC_CLK_LAT_FALL,
 731         },
 732 };
 733
 734 static int lcd_enabled = 1;
 735 static int lcd_bl_polarity;
 736
 737 static int lcd_backlight_polarity(void)
 738 {
 739         return lcd_bl_polarity;
 740 }
 741
 742 void lcd_enable(void)
 743 {
 744         /* HACK ALERT:
 745          * global variable from common/lcd.c
 746          * Set to 0 here to prevent messages from going to LCD
 747          * rather than serial console
 748          */
 749         lcd_is_enabled = 0;
 750
 751         if (lcd_enabled) {
 752                 karo_load_splashimage(1);
 753
 754                 debug("Switching LCD on\n");
 755                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 756                 udelay(100);
 757                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 758                 udelay(300000);
 759                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 760                         lcd_backlight_polarity());
 761         }
 762 }
 763
 764 void lcd_disable(void)
 765 {
 766         if (lcd_enabled) {
 767                 printf("Disabling LCD\n");
 768                 ipuv3_fb_shutdown();
 769         }
 770 }
 771
 772 void lcd_panel_disable(void)
 773 {
 774         if (lcd_enabled) {
 775                 debug("Switching LCD off\n");
 776                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 777                         !lcd_backlight_polarity());
 778                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 779                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 780         }
 781 }
 782
 783 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 784         /* LCD RESET */
 785         MX6_PAD_EIM_D29__GPIO3_IO29,
 786         /* LCD POWER_ENABLE */
 787         MX6_PAD_EIM_EB3__GPIO2_IO31,
 788         /* LCD Backlight (PWM) */
 789         MX6_PAD_GPIO_1__GPIO1_IO01,
 790
 791 #ifndef CONFIG_SYS_LVDS_IF
 792         /* Display */
 793         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 794         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 795         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 796         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 797         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 798         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 799         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 800         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 801         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 802         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 803         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 804         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 805         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 806         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 807         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 808         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 809         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 810         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 811         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 812         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 813         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 814         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 815         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 816         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 817         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
 818         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
 819         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 820         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 821 #endif
 822 };
 823
 824 static const struct gpio stk5_lcd_gpios[] = {
 825         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
 826         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
 827         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 828 };
 829
 830 void lcd_ctrl_init(void *lcdbase)
 831 {
 832         int color_depth = 24;
 833         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 834         const char *vm;
 835         unsigned long val;
 836         int refresh = 60;
 837         struct fb_videomode *p = &tx6_fb_modes[0];
 838         struct fb_videomode fb_mode;
 839         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
 840         int pix_fmt;
 841         int lcd_bus_width;
 842         unsigned long di_clk_rate = 65000000;
 843
 844         if (!lcd_enabled) {
 845                 debug("LCD disabled\n");
 846                 return;
 847         }
 848
 849         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
 850                 debug("Disabling LCD\n");
 851                 lcd_enabled = 0;
 852                 setenv("splashimage", NULL);
 853                 return;
 854         }
 855
 856         karo_fdt_move_fdt();
 857         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
 858
 859         if (video_mode == NULL) {
 860                 debug("Disabling LCD\n");
 861                 lcd_enabled = 0;
 862                 return;
 863         }
 864         vm = video_mode;
 865         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
 866                 p = &fb_mode;
 867                 debug("Using video mode from FDT\n");
 868                 vm += strlen(vm);
 869                 if (fb_mode.xres > panel_info.vl_col ||
 870                         fb_mode.yres > panel_info.vl_row) {
 871                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
 872                                 fb_mode.xres, fb_mode.yres,
 873                                 panel_info.vl_col, panel_info.vl_row);
 874                         lcd_enabled = 0;
 875                         return;
 876                 }
 877         }
 878         if (p->name != NULL)
 879                 debug("Trying compiled-in video modes\n");
 880         while (p->name != NULL) {
 881                 if (strcmp(p->name, vm) == 0) {
 882                         debug("Using video mode: '%s'\n", p->name);
 883                         vm += strlen(vm);
 884                         break;
 885                 }
 886                 p++;
 887         }
 888         if (*vm != '\0')
 889                 debug("Trying to decode video_mode: '%s'\n", vm);
 890         while (*vm != '\0') {
 891                 if (*vm >= '0' && *vm <= '9') {
 892                         char *end;
 893
 894                         val = simple_strtoul(vm, &end, 0);
 895                         if (end > vm) {
 896                                 if (!xres_set) {
 897                                         if (val > panel_info.vl_col)
 898                                                 val = panel_info.vl_col;
 899                                         p->xres = val;
 900                                         panel_info.vl_col = val;
 901                                         xres_set = 1;
 902                                 } else if (!yres_set) {
 903                                         if (val > panel_info.vl_row)
 904                                                 val = panel_info.vl_row;
 905                                         p->yres = val;
 906                                         panel_info.vl_row = val;
 907                                         yres_set = 1;
 908                                 } else if (!bpp_set) {
 909                                         switch (val) {
 910                                         case 32:
 911                                         case 24:
 912                                                 if (is_lvds())
 913                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
 914                                                 /* fallthru */
 915                                         case 16:
 916                                         case 8:
 917                                                 color_depth = val;
 918                                                 break;
 919
 920                                         case 18:
 921                                                 if (is_lvds()) {
 922                                                         color_depth = val;
 923                                                         break;
 924                                                 }
 925                                                 /* fallthru */
 926                                         default:
 927                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
 928                                                         end - vm, vm, color_depth);
 929                                         }
 930                                         bpp_set = 1;
 931                                 } else if (!refresh_set) {
 932                                         refresh = val;
 933                                         refresh_set = 1;
 934                                 }
 935                         }
 936                         vm = end;
 937                 }
 938                 switch (*vm) {
 939                 case '@':
 940                         bpp_set = 1;
 941                         /* fallthru */
 942                 case '-':
 943                         yres_set = 1;
 944                         /* fallthru */
 945                 case 'x':
 946                         xres_set = 1;
 947                         /* fallthru */
 948                 case 'M':
 949                 case 'R':
 950                         vm++;
 951                         break;
 952
 953                 default:
 954                         if (*vm != '\0')
 955                                 vm++;
 956                 }
 957         }
 958         if (p->xres == 0 || p->yres == 0) {
 959                 printf("Invalid video mode: %s\n", getenv("video_mode"));
 960                 lcd_enabled = 0;
 961                 printf("Supported video modes are:");
 962                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
 963                         printf(" %s", p->name);
 964                 }
 965                 printf("\n");
 966                 return;
 967         }
 968         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
 969                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
 970                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
 971                 lcd_enabled = 0;
 972                 return;
 973         }
 974         panel_info.vl_col = p->xres;
 975         panel_info.vl_row = p->yres;
 976
 977         switch (color_depth) {
 978         case 8:
 979                 panel_info.vl_bpix = LCD_COLOR8;
 980                 break;
 981         case 16:
 982                 panel_info.vl_bpix = LCD_COLOR16;
 983                 break;
 984         default:
 985                 panel_info.vl_bpix = LCD_COLOR32;
 986         }
 987
 988         p->pixclock = KHZ2PICOS(refresh *
 989                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
 990                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
 991                                 1000);
 992         debug("Pixel clock set to %lu.%03lu MHz\n",
 993                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
 994
 995         if (p != &fb_mode) {
 996                 int ret;
 997
 998                 debug("Creating new display-timing node from '%s'\n",
 999                         video_mode);
1000                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1001                 if (ret)
1002                         printf("Failed to create new display-timing node from '%s': %d\n",
1003                                 video_mode, ret);
1004         }
1005
1006         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1007         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1008                                         ARRAY_SIZE(stk5_lcd_pads));
1009
1010         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1011         switch (lcd_bus_width) {
1012         case 24:
1013                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1014                 break;
1015
1016         case 18:
1017                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1018                 break;
1019
1020         case 16:
1021                 if (!is_lvds()) {
1022                         pix_fmt = IPU_PIX_FMT_RGB565;
1023                         break;
1024                 }
1025                 /* fallthru */
1026         default:
1027                 lcd_enabled = 0;
1028                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1029                         lcd_bus_width);
1030                 return;
1031         }
1032         if (is_lvds()) {
1033                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1034                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1035                 uint32_t gpr2;
1036                 uint32_t gpr3;
1037
1038                 if (lvds_chan_mask == 0) {
1039                         printf("No LVDS channel active\n");
1040                         lcd_enabled = 0;
1041                         return;
1042                 }
1043
1044                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1045                 if (lcd_bus_width == 24)
1046                         gpr2 |= (1 << 5) | (1 << 7);
1047                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1048                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1049                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1050                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1051
1052                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1053                 gpr3 &= ~((3 << 8) | (3 << 6));
1054                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1055         }
1056         if (karo_load_splashimage(0) == 0) {
1057                 int ret;
1058
1059                 debug("Initializing LCD controller\n");
1060                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1061                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1062                                 di_clk_rate, -1);
1063                 if (ret) {
1064                         printf("Failed to initialize FB driver: %d\n", ret);
1065                         lcd_enabled = 0;
1066                 }
1067         } else {
1068                 debug("Skipping initialization of LCD controller\n");
1069         }
1070 }
1071 #else
1072 #define lcd_enabled 0
1073 #endif /* CONFIG_LCD */
1074
1075 static void stk5_board_init(void)
1076 {
1077         int ret;
1078
1079         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1080         if (ret < 0) {
1081                 printf("Failed to request stk5_gpios: %d\n", ret);
1082                 return;
1083         }
1084         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1085 }
1086
1087 static void stk5v3_board_init(void)
1088 {
1089         stk5_board_init();
1090 }
1091
1092 static void stk5v5_board_init(void)
1093 {
1094         int ret;
1095
1096         stk5_board_init();
1097
1098         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1099                         "Flexcan Transceiver");
1100         if (ret) {
1101                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1102                 return;
1103         }
1104
1105         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1106 }
1107
1108 static void tx6qdl_set_cpu_clock(void)
1109 {
1110         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1111
1112         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1113                 return;
1114
1115         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1116                 printf("%s detected; skipping cpu clock change\n",
1117                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1118                 return;
1119         }
1120         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1121                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1122                 printf("CPU clock set to %lu.%03lu MHz\n",
1123                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1124         } else {
1125                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1126         }
1127 }
1128
1129 int board_late_init(void)
1130 {
1131         int ret = 0;
1132         const char *baseboard;
1133
1134         env_cleanup();
1135
1136         if (tx6_temp_check_enabled)
1137                 check_cpu_temperature(1);
1138
1139         tx6qdl_set_cpu_clock();
1140
1141         if (had_ctrlc())
1142                 setenv_ulong("safeboot", 1);
1143         else if (wrsr & WRSR_TOUT)
1144                 setenv_ulong("wdreset", 1);
1145         else
1146                 karo_fdt_move_fdt();
1147
1148         baseboard = getenv("baseboard");
1149         if (!baseboard)
1150                 goto exit;
1151
1152         printf("Baseboard: %s\n", baseboard);
1153
1154         if (strncmp(baseboard, "stk5", 4) == 0) {
1155                 if ((strlen(baseboard) == 4) ||
1156                         strcmp(baseboard, "stk5-v3") == 0) {
1157                         stk5v3_board_init();
1158                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1159                         const char *otg_mode = getenv("otg_mode");
1160
1161                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1162                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1163                                         otg_mode, baseboard);
1164                                 setenv("otg_mode", "none");
1165                         }
1166                         stk5v5_board_init();
1167                 } else {
1168                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1169                                 baseboard + 4);
1170                 }
1171         } else {
1172                 printf("WARNING: Unsupported baseboard: '%s'\n",
1173                         baseboard);
1174                 ret = -EINVAL;
1175         }
1176
1177 exit:
1178         tx6_init_mac();
1179
1180         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1181         clear_ctrlc();
1182         return ret;
1183 }
1184
1185 #ifdef CONFIG_TX6_NAND
1186 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1187 #else
1188 #ifdef CONFIG_MMC_BOOT_SIZE
1189 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
1190 #else
1191 #define TX6_FLASH_SZ    2
1192 #endif
1193 #endif /* CONFIG_TX6_NAND */
1194
1195 #define TX6_DDR_SZ      (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
1196
1197 static char tx6_mem_table[] = {
1198         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
1199         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
1200         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
1201         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
1202         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
1203         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
1204         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
1205         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
1206         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
1207         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
1208         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
1209         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
1210 };
1211
1212 static inline char tx6_mem_suffix(void)
1213 {
1214         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1215
1216         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1217                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1218
1219         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1220                 return '?';
1221
1222         return tx6_mem_table[mem_idx];
1223 };
1224
1225 static struct {
1226         uchar addr;
1227         uchar rev;
1228 } tx6_mod_revs[] = {
1229         { 0x3c, 1, },
1230         { 0x32, 2, },
1231         { 0x33, 3, },
1232 };
1233
1234 static int tx6_get_mod_rev(void)
1235 {
1236         int i;
1237
1238         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
1239                 int ret = i2c_probe(tx6_mod_revs[i].addr);
1240                 if (ret == 0) {
1241                         debug("I2C probe succeeded for addr %02x\n", tx6_mod_revs[i].addr);
1242                         return tx6_mod_revs[i].rev;
1243                 }
1244                 debug("I2C probe returned %d for addr %02x\n", ret,
1245                         tx6_mod_revs[i].addr);
1246         }
1247         return 0;
1248 }
1249
1250 int checkboard(void)
1251 {
1252         u32 cpurev = get_cpu_rev();
1253         int cpu_variant = (cpurev >> 12) & 0xff;
1254
1255         tx6qdl_print_cpuinfo();
1256
1257         i2c_init(CONFIG_SYS_I2C_SPEED, 0 /* unused */);
1258
1259         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1260                 tx6_mod_suffix,
1261                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1262                 is_lvds(), tx6_get_mod_rev(),
1263                 tx6_mem_suffix());
1264
1265         return 0;
1266 }
1267
1268 #ifdef CONFIG_SERIAL_TAG
1269 void get_board_serial(struct tag_serialnr *serialnr)
1270 {
1271         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1272         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1273
1274         serialnr->low = readl(&fuse->cfg0);
1275         serialnr->high = readl(&fuse->cfg1);
1276 }
1277 #endif
1278
1279 #if defined(CONFIG_OF_BOARD_SETUP)
1280 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1281 #include <jffs2/jffs2.h>
1282 #include <mtd_node.h>
1283 static struct node_info nodes[] = {
1284         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1285 };
1286 #else
1287 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1288 #endif
1289
1290 static const char *tx6_touchpanels[] = {
1291         "ti,tsc2007",
1292         "edt,edt-ft5x06",
1293         "eeti,egalax_ts",
1294 };
1295
1296 int ft_board_setup(void *blob, bd_t *bd)
1297 {
1298         const char *baseboard = getenv("baseboard");
1299         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1300         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1301         int ret;
1302
1303         ret = fdt_increase_size(blob, 4096);
1304         if (ret) {
1305                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1306                 return ret;
1307         }
1308         if (stk5_v5)
1309                 karo_fdt_enable_node(blob, "stk5led", 0);
1310
1311         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1312         fdt_fixup_ethernet(blob);
1313
1314         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1315                                 ARRAY_SIZE(tx6_touchpanels));
1316         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1317         karo_fdt_fixup_flexcan(blob, stk5_v5);
1318
1319         karo_fdt_update_fb_mode(blob, video_mode);
1320
1321         return 0;
1322 }
1323 #endif /* CONFIG_OF_BOARD_SETUP */