board/karo/tx6/tx6qdl.c

   1 /*
   2  * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17 #include <common.h>
  18 #include <errno.h>
  19 #include <libfdt.h>
  20 #include <fdt_support.h>
  21 #include <lcd.h>
  22 #include <netdev.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <video_fb.h>
  26 #include <ipu.h>
  27 #include <mxcfb.h>
  28 #include <i2c.h>
  29 #include <linux/fb.h>
  30 #include <asm/io.h>
  31 #include <asm/gpio.h>
  32 #include <asm/arch/mx6-pins.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/hab.h>
  35 #include <asm/arch/imx-regs.h>
  36 #include <asm/arch/crm_regs.h>
  37 #include <asm/arch/sys_proto.h>
  38
  39 #include "../common/karo.h"
  40 #include "pmic.h"
  41
  42 #define __data __attribute__((section(".data")))
  43
  44 #define TX6_FEC_RST_GPIO                IMX_GPIO_NR(7, 6)
  45 #define TX6_FEC_PWR_GPIO                IMX_GPIO_NR(3, 20)
  46 #define TX6_FEC_INT_GPIO                IMX_GPIO_NR(7, 1)
  47 #define TX6_LED_GPIO                    IMX_GPIO_NR(2, 20)
  48
  49 #define TX6_LCD_PWR_GPIO                IMX_GPIO_NR(2, 31)
  50 #define TX6_LCD_RST_GPIO                IMX_GPIO_NR(3, 29)
  51 #define TX6_LCD_BACKLIGHT_GPIO          IMX_GPIO_NR(1, 1)
  52
  53 #define TX6_RESET_OUT_GPIO              IMX_GPIO_NR(7, 12)
  54 #define TX6_I2C1_SCL_GPIO               IMX_GPIO_NR(3, 21)
  55 #define TX6_I2C1_SDA_GPIO               IMX_GPIO_NR(3, 28)
  56
  57 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  58 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  59 #else
  60 #define TEMPERATURE_MIN                 (-40)
  61 #endif
  62 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  63 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  64 #else
  65 #define TEMPERATURE_HOT                 80
  66 #endif
  67
  68 DECLARE_GLOBAL_DATA_PTR;
  69
  70 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  71
  72 enum {
  73         MX6_PAD_DECL(GARBAGE, 0, 0, 0, 0, 0, 0)
  74 };
  75
  76 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  77 #ifdef CONFIG_SECURE_BOOT
  78 char __csf_data[0] __attribute__((section(".__csf_data")));
  79 #endif
  80
  81 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
  82         /* RESET_OUT */
  83         MX6_PAD_GPIO_17__GPIO7_IO12,
  84
  85         /* UART pads */
  86 #if CONFIG_MXC_UART_BASE == UART1_BASE
  87         MX6_PAD_SD3_DAT7__UART1_TX_DATA,
  88         MX6_PAD_SD3_DAT6__UART1_RX_DATA,
  89         MX6_PAD_SD3_DAT1__UART1_RTS_B,
  90         MX6_PAD_SD3_DAT0__UART1_CTS_B,
  91 #endif
  92 #if CONFIG_MXC_UART_BASE == UART2_BASE
  93         MX6_PAD_SD4_DAT4__UART2_RX_DATA,
  94         MX6_PAD_SD4_DAT7__UART2_TX_DATA,
  95         MX6_PAD_SD4_DAT5__UART2_RTS_B,
  96         MX6_PAD_SD4_DAT6__UART2_CTS_B,
  97 #endif
  98 #if CONFIG_MXC_UART_BASE == UART3_BASE
  99         MX6_PAD_EIM_D24__UART3_TX_DATA,
 100         MX6_PAD_EIM_D25__UART3_RX_DATA,
 101         MX6_PAD_SD3_RST__UART3_RTS_B,
 102         MX6_PAD_SD3_DAT3__UART3_CTS_B,
 103 #endif
 104         /* internal I2C */
 105         MX6_PAD_EIM_D28__I2C1_SDA,
 106         MX6_PAD_EIM_D21__I2C1_SCL,
 107
 108         /* FEC PHY GPIO functions */
 109         MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
 110         MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
 111         MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
 112 };
 113
 114 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
 115         /* FEC functions */
 116         MX6_PAD_ENET_MDC__ENET_MDC,
 117         MX6_PAD_ENET_MDIO__ENET_MDIO,
 118         MX6_PAD_GPIO_16__ENET_REF_CLK,
 119         MX6_PAD_ENET_RX_ER__ENET_RX_ER,
 120         MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
 121         MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
 122         MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
 123         MX6_PAD_ENET_TX_EN__ENET_TX_EN,
 124         MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
 125         MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
 126 };
 127
 128 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
 129         /* internal I2C */
 130         MX6_PAD_EIM_D28__I2C1_SDA,
 131         MX6_PAD_EIM_D21__I2C1_SCL,
 132 };
 133
 134 static const struct gpio const tx6qdl_gpios[] = {
 135         /* These two entries are used to forcefully reinitialize the I2C bus */
 136         { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 137         { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 138
 139         { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
 140         { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 141         { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 142         { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 143 };
 144
 145 /*
 146  * Functions
 147  */
 148 /* placed in section '.data' to prevent overwriting relocation info
 149  * overlayed with bss
 150  */
 151 static u32 wrsr __attribute__((section(".data")));
 152
 153 #define WRSR_POR                        (1 << 4)
 154 #define WRSR_TOUT                       (1 << 1)
 155 #define WRSR_SFTW                       (1 << 0)
 156
 157 static void print_reset_cause(void)
 158 {
 159         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 160         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 161         u32 srsr;
 162         char *dlm = "";
 163
 164         printf("Reset cause: ");
 165
 166         srsr = readl(&src_regs->srsr);
 167         wrsr = readw(wdt_base + 4);
 168
 169         if (wrsr & WRSR_POR) {
 170                 printf("%sPOR", dlm);
 171                 dlm = " | ";
 172         }
 173         if (srsr & 0x00004) {
 174                 printf("%sCSU", dlm);
 175                 dlm = " | ";
 176         }
 177         if (srsr & 0x00008) {
 178                 printf("%sIPP USER", dlm);
 179                 dlm = " | ";
 180         }
 181         if (srsr & 0x00010) {
 182                 if (wrsr & WRSR_SFTW) {
 183                         printf("%sSOFT", dlm);
 184                         dlm = " | ";
 185                 }
 186                 if (wrsr & WRSR_TOUT) {
 187                         printf("%sWDOG", dlm);
 188                         dlm = " | ";
 189                 }
 190         }
 191         if (srsr & 0x00020) {
 192                 printf("%sJTAG HIGH-Z", dlm);
 193                 dlm = " | ";
 194         }
 195         if (srsr & 0x00040) {
 196                 printf("%sJTAG SW", dlm);
 197                 dlm = " | ";
 198         }
 199         if (srsr & 0x10000) {
 200                 printf("%sWARM BOOT", dlm);
 201                 dlm = " | ";
 202         }
 203         if (dlm[0] == '\0')
 204                 printf("unknown");
 205
 206         printf("\n");
 207 }
 208
 209 static const char __data *tx6_mod_suffix;
 210
 211 static void tx6qdl_print_cpuinfo(void)
 212 {
 213         u32 cpurev = get_cpu_rev();
 214         char *cpu_str = "?";
 215
 216         switch ((cpurev >> 12) & 0xff) {
 217         case MXC_CPU_MX6SL:
 218                 cpu_str = "SL";
 219                 tx6_mod_suffix = "?";
 220                 break;
 221         case MXC_CPU_MX6DL:
 222                 cpu_str = "DL";
 223                 tx6_mod_suffix = "U";
 224                 break;
 225         case MXC_CPU_MX6SOLO:
 226                 cpu_str = "SOLO";
 227                 tx6_mod_suffix = "S";
 228                 break;
 229         case MXC_CPU_MX6Q:
 230                 cpu_str = "Q";
 231                 tx6_mod_suffix = "Q";
 232                 break;
 233         }
 234
 235         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 236                 cpu_str,
 237                 (cpurev & 0x000F0) >> 4,
 238                 (cpurev & 0x0000F) >> 0,
 239                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 240
 241         print_reset_cause();
 242 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 243         check_cpu_temperature(1);
 244 #endif
 245 }
 246
 247 int board_early_init_f(void)
 248 {
 249         return 0;
 250 }
 251
 252 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 253 static bool tx6_temp_check_enabled = true;
 254 #else
 255 #define tx6_temp_check_enabled  0
 256 #endif
 257 static int pmic_addr __data;
 258
 259 #if defined(CONFIG_SOC_MX6Q)
 260 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e00a4
 261 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e00c4
 262 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e03b8
 263 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e03d8
 264 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0898
 265 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e089c
 266 #define I2C1_SEL_INPUT_VAL                      0
 267 #endif
 268 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 269 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21        0x020e0158
 270 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28        0x020e0174
 271 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21        0x020e0528
 272 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28        0x020e0544
 273 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21      0x020e0868
 274 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28      0x020e086c
 275 #define I2C1_SEL_INPUT_VAL                      1
 276 #endif
 277
 278 #define GPIO_DR 0
 279 #define GPIO_DIR 4
 280 #define GPIO_PSR 8
 281
 282 static const struct i2c_gpio_regs {
 283         const char *label;
 284         u32 gpio;
 285         unsigned long gpio_base;
 286         unsigned long muxctl;
 287         unsigned long padctl;
 288         unsigned long sel_input;
 289 } tx6_i2c_iomux_regs[] = {
 290         {
 291                 .label = "PMIC SCL",
 292                 .gpio = TX6_I2C1_SCL_GPIO,
 293                 .gpio_base = GPIO3_BASE_ADDR,
 294                 .muxctl = IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21,
 295                 .padctl = IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21,
 296                 .sel_input = IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21,
 297         }, {
 298                 .label = "PMIC SDA",
 299                 .gpio = TX6_I2C1_SDA_GPIO,
 300                 .gpio_base = GPIO3_BASE_ADDR,
 301                 .muxctl = IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28,
 302                 .padctl = IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28,
 303                 .sel_input = IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28,
 304         },
 305 };
 306
 307 static inline u32 __tx6_readl(void *addr,
 308                         const char *fn, int ln)
 309 {
 310         u32 val = readl(addr);
 311         debug("%s@%d: read %08x from %p\n", fn, ln, val, addr);
 312         return val;
 313 }
 314 #undef readl
 315 #define readl(a)        __tx6_readl((void *)(a), __func__, __LINE__)
 316
 317 static inline void __tx6_writel(u32 val, void *addr,
 318                                 const char *fn, int ln)
 319 {
 320         debug("%s@%d: writing %08x to %p\n", fn, ln, val, addr);
 321         writel(val, addr);
 322 }
 323 #undef writel
 324 #define writel(v, a)    __tx6_writel(v, (void *)(a), __func__, __LINE__)
 325
 326 static void tx6_i2c_recover(void)
 327 {
 328         int i;
 329         int bad = 0;
 330         int failed = 0;
 331 #define MAX_TRIES 100
 332
 333         debug("Clearing I2C bus\n");
 334
 335         for (i = 0; i < ARRAY_SIZE(tx6_i2c_iomux_regs); i++) {
 336                 int gpio = tx6_i2c_iomux_regs[i].gpio;
 337                 u32 gpio_mask = 1 << (gpio % 32);
 338
 339                 void *gpio_base = (void *)tx6_i2c_iomux_regs[i].gpio_base;
 340
 341                 if ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0) {
 342                         int retries = MAX_TRIES;
 343
 344                         bad++;
 345                         printf("%s (GPIO%u_%u) is not HIGH\n",
 346                                 tx6_i2c_iomux_regs[i].label,
 347                                 gpio / 32 + 1, gpio % 32);
 348                         writel(readl(gpio_base + GPIO_DR) | gpio_mask,
 349                                 gpio_base + GPIO_DR);
 350                         writel(readl(gpio_base + GPIO_DIR) | gpio_mask,
 351                                 gpio_base + GPIO_DIR);
 352                         writel(0x15, tx6_i2c_iomux_regs[i].muxctl);
 353                         writel(0x0f079, tx6_i2c_iomux_regs[i].padctl);
 354                         writel(I2C1_SEL_INPUT_VAL, tx6_i2c_iomux_regs[i].sel_input);
 355                         if ((readl(gpio_base + GPIO_DR) & gpio_mask) == 0)
 356                                 hang();
 357                         if ((readl(gpio_base + GPIO_DIR) & gpio_mask) == 0)
 358                                 hang();
 359                         while ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0 &&
 360                                 retries-- > 0) {
 361                                 udelay(100);
 362                         }
 363                         writel(readl(gpio_base + GPIO_DIR) & ~gpio_mask,
 364                                 gpio_base + GPIO_DIR);
 365
 366                         if ((readl(gpio_base + GPIO_PSR) & gpio_mask) == 0) {
 367                                 printf("Failed to force %s (GPIO%u_%u) HIGH\n",
 368                                         tx6_i2c_iomux_regs[i].label,
 369                                         gpio / 32 + 1, gpio % 32);
 370                                 failed++;
 371                         } else if (retries < MAX_TRIES) {
 372                                 printf("%s (GPIO%u_%u) forced HIGH after %u loops\n",
 373                                         tx6_i2c_iomux_regs[i].label,
 374                                         gpio / 32 + 1, gpio % 32,
 375                                         MAX_TRIES - retries);
 376                         }
 377                 } else {
 378                         debug("%s (GPIO%u_%u) is HIGH\n",
 379                                 tx6_i2c_iomux_regs[i].label,
 380                                 gpio / 32 + 1, gpio % 32);
 381                 }
 382         }
 383         debug("Setting up I2C Pads\n");
 384         imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
 385                                         ARRAY_SIZE(tx6_i2c_pads));
 386         if (bad) {
 387                 if (failed)
 388                         printf("I2C bus recovery FAILED\n");
 389                 else
 390                         printf("I2C bus recovery succeeded\n");
 391         }
 392 }
 393
 394 #define pr_reg(b, n)    debug("%12s@%p=%08x\n", #n, (void *)(b) + (n), readl((b) + (n)))
 395
 396 static inline void dump_regs(void)
 397 {
 398         pr_reg(GPIO3_BASE_ADDR, GPIO_DR);
 399         pr_reg(GPIO3_BASE_ADDR, GPIO_DIR);
 400         pr_reg(GPIO3_BASE_ADDR, GPIO_PSR);
 401 }
 402
 403 int board_init(void)
 404 {
 405         int ret;
 406
 407         ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
 408         if (ret < 0) {
 409                 printf("Failed to request tx6qdl_gpios: %d\n", ret);
 410         }
 411         imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
 412
 413         /* Address of boot parameters */
 414         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 415         gd->bd->bi_arch_number = -1;
 416
 417         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 418                 if (wrsr & WRSR_TOUT)
 419                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 420                 else
 421                         printf("<CTRL-C> detected; safeboot enabled\n");
 422 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 423                 tx6_temp_check_enabled = false;
 424 #endif
 425                 return 0;
 426         }
 427
 428         ret = tx6_pmic_init(pmic_addr);
 429         if (ret) {
 430                 printf("Failed to setup PMIC voltages: %d\n", ret);
 431                 hang();
 432         }
 433         return 0;
 434 }
 435
 436 int dram_init(void)
 437 {
 438         /* dram_init must store complete ramsize in gd->ram_size */
 439         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 440                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 441         return 0;
 442 }
 443
 444 void dram_init_banksize(void)
 445 {
 446         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 447         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 448                         PHYS_SDRAM_1_SIZE);
 449 #if CONFIG_NR_DRAM_BANKS > 1
 450         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 451         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 452                         PHYS_SDRAM_2_SIZE);
 453 #endif
 454 }
 455
 456 #ifdef  CONFIG_FSL_ESDHC
 457 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP |               \
 458         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |         \
 459         PAD_CTL_SRE_FAST)
 460
 461 static const iomux_v3_cfg_t mmc0_pads[] = {
 462         MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 463         MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 464         MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 465         MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 466         MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 467         MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 468         /* SD1 CD */
 469         MX6_PAD_SD3_CMD__GPIO7_IO02,
 470 };
 471
 472 static const iomux_v3_cfg_t mmc1_pads[] = {
 473         MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 474         MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 475         MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 476         MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 477         MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 478         MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 479         /* SD2 CD */
 480         MX6_PAD_SD3_CLK__GPIO7_IO03,
 481 };
 482
 483 #ifdef CONFIG_TX6_EMMC
 484 static const iomux_v3_cfg_t mmc3_pads[] = {
 485         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
 486         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
 487         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
 488         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
 489         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
 490         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
 491         /* eMMC RESET */
 492         MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 493                                                 PAD_CTL_DSE_40ohm),
 494 };
 495 #endif
 496
 497 static struct tx6_esdhc_cfg {
 498         const iomux_v3_cfg_t *pads;
 499         int num_pads;
 500         enum mxc_clock clkid;
 501         struct fsl_esdhc_cfg cfg;
 502         int cd_gpio;
 503 } tx6qdl_esdhc_cfg[] = {
 504 #ifdef CONFIG_TX6_EMMC
 505         {
 506                 .pads = mmc3_pads,
 507                 .num_pads = ARRAY_SIZE(mmc3_pads),
 508                 .clkid = MXC_ESDHC4_CLK,
 509                 .cfg = {
 510                         .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
 511                         .max_bus_width = 4,
 512                 },
 513                 .cd_gpio = -EINVAL,
 514         },
 515 #endif
 516         {
 517                 .pads = mmc0_pads,
 518                 .num_pads = ARRAY_SIZE(mmc0_pads),
 519                 .clkid = MXC_ESDHC_CLK,
 520                 .cfg = {
 521                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 522                         .max_bus_width = 4,
 523                 },
 524                 .cd_gpio = IMX_GPIO_NR(7, 2),
 525         },
 526         {
 527                 .pads = mmc1_pads,
 528                 .num_pads = ARRAY_SIZE(mmc1_pads),
 529                 .clkid = MXC_ESDHC2_CLK,
 530                 .cfg = {
 531                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 532                         .max_bus_width = 4,
 533                 },
 534                 .cd_gpio = IMX_GPIO_NR(7, 3),
 535         },
 536 };
 537
 538 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 539 {
 540         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 541 }
 542
 543 int board_mmc_getcd(struct mmc *mmc)
 544 {
 545         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 546
 547         if (cfg->cd_gpio < 0)
 548                 return 1;
 549
 550         debug("SD card %d is %spresent (GPIO %d)\n",
 551                 cfg - tx6qdl_esdhc_cfg,
 552                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 553                 cfg->cd_gpio);
 554         return !gpio_get_value(cfg->cd_gpio);
 555 }
 556
 557 int board_mmc_init(bd_t *bis)
 558 {
 559         int i;
 560
 561         for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
 562                 struct mmc *mmc;
 563                 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
 564                 int ret;
 565
 566                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 567                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 568
 569                 if (cfg->cd_gpio >= 0) {
 570                         ret = gpio_request_one(cfg->cd_gpio,
 571                                         GPIOFLAG_INPUT, "MMC CD");
 572                         if (ret) {
 573                                 printf("Error %d requesting GPIO%d_%d\n",
 574                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 575                                 continue;
 576                         }
 577                 }
 578
 579                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 580                 fsl_esdhc_initialize(bis, &cfg->cfg);
 581
 582                 mmc = find_mmc_device(i);
 583                 if (mmc == NULL)
 584                         continue;
 585                 if (board_mmc_getcd(mmc))
 586                         mmc_init(mmc);
 587         }
 588         return 0;
 589 }
 590 #endif /* CONFIG_CMD_MMC */
 591
 592 #ifdef CONFIG_FEC_MXC
 593
 594 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
 595                         PAD_CTL_SRE_FAST)
 596 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
 597 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 598
 599 #ifndef ETH_ALEN
 600 #define ETH_ALEN 6
 601 #endif
 602
 603 int board_eth_init(bd_t *bis)
 604 {
 605         int ret;
 606
 607         /* delay at least 21ms for the PHY internal POR signal to deassert */
 608         udelay(22000);
 609
 610         imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
 611                                         ARRAY_SIZE(tx6qdl_fec_pads));
 612
 613         /* Deassert RESET to the external phy */
 614         gpio_set_value(TX6_FEC_RST_GPIO, 1);
 615
 616         ret = cpu_eth_init(bis);
 617         if (ret)
 618                 printf("cpu_eth_init() failed: %d\n", ret);
 619
 620         return ret;
 621 }
 622
 623 static void tx6_init_mac(void)
 624 {
 625         u8 mac[ETH_ALEN];
 626
 627         imx_get_mac_from_fuse(-1, mac);
 628         if (!is_valid_ether_addr(mac)) {
 629                 printf("No valid MAC address programmed\n");
 630                 return;
 631         }
 632
 633         printf("MAC addr from fuse: %pM\n", mac);
 634         eth_setenv_enetaddr("ethaddr", mac);
 635 }
 636 #else
 637 static inline void tx6_init_mac(void)
 638 {
 639 }
 640 #endif /* CONFIG_FEC_MXC */
 641
 642 enum {
 643         LED_STATE_INIT = -1,
 644         LED_STATE_OFF,
 645         LED_STATE_ON,
 646 };
 647
 648 static inline int calc_blink_rate(void)
 649 {
 650         if (!tx6_temp_check_enabled)
 651                 return CONFIG_SYS_HZ;
 652
 653         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 654                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 655                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 656 }
 657
 658 void show_activity(int arg)
 659 {
 660         static int led_state = LED_STATE_INIT;
 661         static int blink_rate;
 662         static ulong last;
 663
 664         if (led_state == LED_STATE_INIT) {
 665                 last = get_timer(0);
 666                 gpio_set_value(TX6_LED_GPIO, 1);
 667                 led_state = LED_STATE_ON;
 668                 blink_rate = calc_blink_rate();
 669         } else {
 670                 if (get_timer(last) > blink_rate) {
 671                         blink_rate = calc_blink_rate();
 672                         last = get_timer_masked();
 673                         if (led_state == LED_STATE_ON) {
 674                                 gpio_set_value(TX6_LED_GPIO, 0);
 675                         } else {
 676                                 gpio_set_value(TX6_LED_GPIO, 1);
 677                         }
 678                         led_state = 1 - led_state;
 679                 }
 680         }
 681 }
 682
 683 static const iomux_v3_cfg_t stk5_pads[] = {
 684         /* SW controlled LED on STK5 baseboard */
 685         MX6_PAD_EIM_A18__GPIO2_IO20,
 686
 687         /* I2C bus on DIMM pins 40/41 */
 688         MX6_PAD_GPIO_6__I2C3_SDA,
 689         MX6_PAD_GPIO_3__I2C3_SCL,
 690
 691         /* TSC200x PEN IRQ */
 692         MX6_PAD_EIM_D26__GPIO3_IO26,
 693
 694         /* EDT-FT5x06 Polytouch panel */
 695         MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
 696         MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
 697         MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
 698
 699         /* USBH1 */
 700         MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
 701         MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
 702         /* USBOTG */
 703         MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
 704         MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
 705         MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
 706 };
 707
 708 static const struct gpio stk5_gpios[] = {
 709         { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 710
 711         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 712         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 713         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 714         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 715         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 716 };
 717
 718 #ifdef CONFIG_LCD
 719 static u16 tx6_cmap[256];
 720 vidinfo_t panel_info = {
 721         /* set to max. size supported by SoC */
 722         .vl_col = 1920,
 723         .vl_row = 1080,
 724
 725         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 726         .cmap = tx6_cmap,
 727 };
 728
 729 static struct fb_videomode tx6_fb_modes[] = {
 730 #ifndef CONFIG_SYS_LVDS_IF
 731         {
 732                 /* Standard VGA timing */
 733                 .name           = "VGA",
 734                 .refresh        = 60,
 735                 .xres           = 640,
 736                 .yres           = 480,
 737                 .pixclock       = KHZ2PICOS(25175),
 738                 .left_margin    = 48,
 739                 .hsync_len      = 96,
 740                 .right_margin   = 16,
 741                 .upper_margin   = 31,
 742                 .vsync_len      = 2,
 743                 .lower_margin   = 12,
 744                 .sync           = FB_SYNC_CLK_LAT_FALL,
 745         },
 746         {
 747                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 748                  * DE high active, 115.2 mm x 86.4 mm display area
 749                  * VGA compatible timing
 750                  */
 751                 .name           = "ETV570",
 752                 .refresh        = 60,
 753                 .xres           = 640,
 754                 .yres           = 480,
 755                 .pixclock       = KHZ2PICOS(25175),
 756                 .left_margin    = 114,
 757                 .hsync_len      = 30,
 758                 .right_margin   = 16,
 759                 .upper_margin   = 32,
 760                 .vsync_len      = 3,
 761                 .lower_margin   = 10,
 762                 .sync           = FB_SYNC_CLK_LAT_FALL,
 763         },
 764         {
 765                 /* Emerging ET0350G0DH6 320 x 240 display.
 766                  * 70.08 mm x 52.56 mm display area.
 767                  */
 768                 .name           = "ET0350",
 769                 .refresh        = 60,
 770                 .xres           = 320,
 771                 .yres           = 240,
 772                 .pixclock       = KHZ2PICOS(6500),
 773                 .left_margin    = 68 - 34,
 774                 .hsync_len      = 34,
 775                 .right_margin   = 20,
 776                 .upper_margin   = 18 - 3,
 777                 .vsync_len      = 3,
 778                 .lower_margin   = 4,
 779                 .sync           = FB_SYNC_CLK_LAT_FALL,
 780         },
 781         {
 782                 /* Emerging ET0430G0DH6 480 x 272 display.
 783                  * 95.04 mm x 53.856 mm display area.
 784                  */
 785                 .name           = "ET0430",
 786                 .refresh        = 60,
 787                 .xres           = 480,
 788                 .yres           = 272,
 789                 .pixclock       = KHZ2PICOS(9000),
 790                 .left_margin    = 2,
 791                 .hsync_len      = 41,
 792                 .right_margin   = 2,
 793                 .upper_margin   = 2,
 794                 .vsync_len      = 10,
 795                 .lower_margin   = 2,
 796         },
 797         {
 798                 /* Emerging ET0500G0DH6 800 x 480 display.
 799                  * 109.6 mm x 66.4 mm display area.
 800                  */
 801                 .name           = "ET0500",
 802                 .refresh        = 60,
 803                 .xres           = 800,
 804                 .yres           = 480,
 805                 .pixclock       = KHZ2PICOS(33260),
 806                 .left_margin    = 216 - 128,
 807                 .hsync_len      = 128,
 808                 .right_margin   = 1056 - 800 - 216,
 809                 .upper_margin   = 35 - 2,
 810                 .vsync_len      = 2,
 811                 .lower_margin   = 525 - 480 - 35,
 812                 .sync           = FB_SYNC_CLK_LAT_FALL,
 813         },
 814         {
 815                 /* Emerging ETQ570G0DH6 320 x 240 display.
 816                  * 115.2 mm x 86.4 mm display area.
 817                  */
 818                 .name           = "ETQ570",
 819                 .refresh        = 60,
 820                 .xres           = 320,
 821                 .yres           = 240,
 822                 .pixclock       = KHZ2PICOS(6400),
 823                 .left_margin    = 38,
 824                 .hsync_len      = 30,
 825                 .right_margin   = 30,
 826                 .upper_margin   = 16, /* 15 according to datasheet */
 827                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 828                 .lower_margin   = 4, /* 4.5 according to datasheet */
 829                 .sync           = FB_SYNC_CLK_LAT_FALL,
 830         },
 831         {
 832                 /* Emerging ET0700G0DH6 800 x 480 display.
 833                  * 152.4 mm x 91.44 mm display area.
 834                  */
 835                 .name           = "ET0700",
 836                 .refresh        = 60,
 837                 .xres           = 800,
 838                 .yres           = 480,
 839                 .pixclock       = KHZ2PICOS(33260),
 840                 .left_margin    = 216 - 128,
 841                 .hsync_len      = 128,
 842                 .right_margin   = 1056 - 800 - 216,
 843                 .upper_margin   = 35 - 2,
 844                 .vsync_len      = 2,
 845                 .lower_margin   = 525 - 480 - 35,
 846                 .sync           = FB_SYNC_CLK_LAT_FALL,
 847         },
 848         {
 849                 /* Emerging ET070001DM6 800 x 480 display.
 850                  * 152.4 mm x 91.44 mm display area.
 851                  */
 852                 .name           = "ET070001DM6",
 853                 .refresh        = 60,
 854                 .xres           = 800,
 855                 .yres           = 480,
 856                 .pixclock       = KHZ2PICOS(33260),
 857                 .left_margin    = 216 - 128,
 858                 .hsync_len      = 128,
 859                 .right_margin   = 1056 - 800 - 216,
 860                 .upper_margin   = 35 - 2,
 861                 .vsync_len      = 2,
 862                 .lower_margin   = 525 - 480 - 35,
 863                 .sync           = 0,
 864         },
 865 #else
 866         {
 867                 /* HannStar HSD100PXN1
 868                  * 202.7m mm x 152.06 mm display area.
 869                  */
 870                 .name           = "HSD100PXN1",
 871                 .refresh        = 60,
 872                 .xres           = 1024,
 873                 .yres           = 768,
 874                 .pixclock       = KHZ2PICOS(65000),
 875                 .left_margin    = 0,
 876                 .hsync_len      = 0,
 877                 .right_margin   = 320,
 878                 .upper_margin   = 0,
 879                 .vsync_len      = 0,
 880                 .lower_margin   = 38,
 881                 .sync           = FB_SYNC_CLK_LAT_FALL,
 882         },
 883 #endif
 884         {
 885                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 886                 .refresh        = 60,
 887                 .left_margin    = 48,
 888                 .hsync_len      = 96,
 889                 .right_margin   = 16,
 890                 .upper_margin   = 31,
 891                 .vsync_len      = 2,
 892                 .lower_margin   = 12,
 893                 .sync           = FB_SYNC_CLK_LAT_FALL,
 894         },
 895 };
 896
 897 static int lcd_enabled = 1;
 898 static int lcd_bl_polarity;
 899
 900 static int lcd_backlight_polarity(void)
 901 {
 902         return lcd_bl_polarity;
 903 }
 904
 905 void lcd_enable(void)
 906 {
 907         /* HACK ALERT:
 908          * global variable from common/lcd.c
 909          * Set to 0 here to prevent messages from going to LCD
 910          * rather than serial console
 911          */
 912         lcd_is_enabled = 0;
 913
 914         if (lcd_enabled) {
 915                 karo_load_splashimage(1);
 916
 917                 debug("Switching LCD on\n");
 918                 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
 919                 udelay(100);
 920                 gpio_set_value(TX6_LCD_RST_GPIO, 1);
 921                 udelay(300000);
 922                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 923                         lcd_backlight_polarity());
 924         }
 925 }
 926
 927 void lcd_disable(void)
 928 {
 929         if (lcd_enabled) {
 930                 printf("Disabling LCD\n");
 931                 ipuv3_fb_shutdown();
 932         }
 933 }
 934
 935 void lcd_panel_disable(void)
 936 {
 937         if (lcd_enabled) {
 938                 debug("Switching LCD off\n");
 939                 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
 940                         !lcd_backlight_polarity());
 941                 gpio_set_value(TX6_LCD_RST_GPIO, 0);
 942                 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
 943         }
 944 }
 945
 946 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 947         /* LCD RESET */
 948         MX6_PAD_EIM_D29__GPIO3_IO29,
 949         /* LCD POWER_ENABLE */
 950         MX6_PAD_EIM_EB3__GPIO2_IO31,
 951         /* LCD Backlight (PWM) */
 952         MX6_PAD_GPIO_1__GPIO1_IO01,
 953
 954 #ifndef CONFIG_SYS_LVDS_IF
 955         /* Display */
 956         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 957         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 958         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 959         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 960         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 961         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 962         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 963         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 964         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 965         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 966         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 967         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 968         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 969         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 970         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 971         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 972         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 973         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 974         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 975         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 976         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 977         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 978         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 979         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 980         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
 981         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
 982         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
 983         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
 984 #endif
 985 };
 986
 987 static const struct gpio stk5_lcd_gpios[] = {
 988         { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
 989         { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
 990         { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 991 };
 992
 993 void lcd_ctrl_init(void *lcdbase)
 994 {
 995         int color_depth = 24;
 996         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 997         const char *vm;
 998         unsigned long val;
 999         int refresh = 60;
1000         struct fb_videomode *p = &tx6_fb_modes[0];
1001         struct fb_videomode fb_mode;
1002         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1003         int pix_fmt;
1004         int lcd_bus_width;
1005         unsigned long di_clk_rate = 65000000;
1006
1007         if (!lcd_enabled) {
1008                 debug("LCD disabled\n");
1009                 return;
1010         }
1011
1012         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1013                 debug("Disabling LCD\n");
1014                 lcd_enabled = 0;
1015                 setenv("splashimage", NULL);
1016                 return;
1017         }
1018
1019         karo_fdt_move_fdt();
1020         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1021
1022         if (video_mode == NULL) {
1023                 debug("Disabling LCD\n");
1024                 lcd_enabled = 0;
1025                 return;
1026         }
1027         vm = video_mode;
1028         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1029                 p = &fb_mode;
1030                 debug("Using video mode from FDT\n");
1031                 vm += strlen(vm);
1032                 if (fb_mode.xres > panel_info.vl_col ||
1033                         fb_mode.yres > panel_info.vl_row) {
1034                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1035                                 fb_mode.xres, fb_mode.yres,
1036                                 panel_info.vl_col, panel_info.vl_row);
1037                         lcd_enabled = 0;
1038                         return;
1039                 }
1040         }
1041         if (p->name != NULL)
1042                 debug("Trying compiled-in video modes\n");
1043         while (p->name != NULL) {
1044                 if (strcmp(p->name, vm) == 0) {
1045                         debug("Using video mode: '%s'\n", p->name);
1046                         vm += strlen(vm);
1047                         break;
1048                 }
1049                 p++;
1050         }
1051         if (*vm != '\0')
1052                 debug("Trying to decode video_mode: '%s'\n", vm);
1053         while (*vm != '\0') {
1054                 if (*vm >= '0' && *vm <= '9') {
1055                         char *end;
1056
1057                         val = simple_strtoul(vm, &end, 0);
1058                         if (end > vm) {
1059                                 if (!xres_set) {
1060                                         if (val > panel_info.vl_col)
1061                                                 val = panel_info.vl_col;
1062                                         p->xres = val;
1063                                         panel_info.vl_col = val;
1064                                         xres_set = 1;
1065                                 } else if (!yres_set) {
1066                                         if (val > panel_info.vl_row)
1067                                                 val = panel_info.vl_row;
1068                                         p->yres = val;
1069                                         panel_info.vl_row = val;
1070                                         yres_set = 1;
1071                                 } else if (!bpp_set) {
1072                                         switch (val) {
1073                                         case 32:
1074                                         case 24:
1075                                                 if (is_lvds())
1076                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1077                                                 /* fallthru */
1078                                         case 16:
1079                                         case 8:
1080                                                 color_depth = val;
1081                                                 break;
1082
1083                                         case 18:
1084                                                 if (is_lvds()) {
1085                                                         color_depth = val;
1086                                                         break;
1087                                                 }
1088                                                 /* fallthru */
1089                                         default:
1090                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1091                                                         end - vm, vm, color_depth);
1092                                         }
1093                                         bpp_set = 1;
1094                                 } else if (!refresh_set) {
1095                                         refresh = val;
1096                                         refresh_set = 1;
1097                                 }
1098                         }
1099                         vm = end;
1100                 }
1101                 switch (*vm) {
1102                 case '@':
1103                         bpp_set = 1;
1104                         /* fallthru */
1105                 case '-':
1106                         yres_set = 1;
1107                         /* fallthru */
1108                 case 'x':
1109                         xres_set = 1;
1110                         /* fallthru */
1111                 case 'M':
1112                 case 'R':
1113                         vm++;
1114                         break;
1115
1116                 default:
1117                         if (*vm != '\0')
1118                                 vm++;
1119                 }
1120         }
1121         if (p->xres == 0 || p->yres == 0) {
1122                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1123                 lcd_enabled = 0;
1124                 printf("Supported video modes are:");
1125                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1126                         printf(" %s", p->name);
1127                 }
1128                 printf("\n");
1129                 return;
1130         }
1131         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1132                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1133                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1134                 lcd_enabled = 0;
1135                 return;
1136         }
1137         panel_info.vl_col = p->xres;
1138         panel_info.vl_row = p->yres;
1139
1140         switch (color_depth) {
1141         case 8:
1142                 panel_info.vl_bpix = LCD_COLOR8;
1143                 break;
1144         case 16:
1145                 panel_info.vl_bpix = LCD_COLOR16;
1146                 break;
1147         default:
1148                 panel_info.vl_bpix = LCD_COLOR32;
1149         }
1150
1151         p->pixclock = KHZ2PICOS(refresh *
1152                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1153                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1154                                 1000);
1155         debug("Pixel clock set to %lu.%03lu MHz\n",
1156                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1157
1158         if (p != &fb_mode) {
1159                 int ret;
1160
1161                 debug("Creating new display-timing node from '%s'\n",
1162                         video_mode);
1163                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1164                 if (ret)
1165                         printf("Failed to create new display-timing node from '%s': %d\n",
1166                                 video_mode, ret);
1167         }
1168
1169         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1170         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1171                                         ARRAY_SIZE(stk5_lcd_pads));
1172
1173         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1174         switch (lcd_bus_width) {
1175         case 24:
1176                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1177                 break;
1178
1179         case 18:
1180                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1181                 break;
1182
1183         case 16:
1184                 if (!is_lvds()) {
1185                         pix_fmt = IPU_PIX_FMT_RGB565;
1186                         break;
1187                 }
1188                 /* fallthru */
1189         default:
1190                 lcd_enabled = 0;
1191                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1192                         lcd_bus_width);
1193                 return;
1194         }
1195         if (is_lvds()) {
1196                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1197                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1198                 uint32_t gpr2;
1199                 uint32_t gpr3;
1200
1201                 if (lvds_chan_mask == 0) {
1202                         printf("No LVDS channel active\n");
1203                         lcd_enabled = 0;
1204                         return;
1205                 }
1206
1207                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1208                 if (lcd_bus_width == 24)
1209                         gpr2 |= (1 << 5) | (1 << 7);
1210                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1211                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1212                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1213                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1214
1215                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1216                 gpr3 &= ~((3 << 8) | (3 << 6));
1217                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1218         }
1219         if (karo_load_splashimage(0) == 0) {
1220                 int ret;
1221
1222                 debug("Initializing LCD controller\n");
1223                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1224                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1225                                 di_clk_rate, -1);
1226                 if (ret) {
1227                         printf("Failed to initialize FB driver: %d\n", ret);
1228                         lcd_enabled = 0;
1229                 }
1230         } else {
1231                 debug("Skipping initialization of LCD controller\n");
1232         }
1233 }
1234 #else
1235 #define lcd_enabled 0
1236 #endif /* CONFIG_LCD */
1237
1238 static void stk5_board_init(void)
1239 {
1240         int ret;
1241
1242         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1243         if (ret < 0) {
1244                 printf("Failed to request stk5_gpios: %d\n", ret);
1245                 return;
1246         }
1247         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1248 }
1249
1250 static void stk5v3_board_init(void)
1251 {
1252         stk5_board_init();
1253 }
1254
1255 static void stk5v5_board_init(void)
1256 {
1257         int ret;
1258
1259         stk5_board_init();
1260
1261         ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1262                         "Flexcan Transceiver");
1263         if (ret) {
1264                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1265                 return;
1266         }
1267
1268         imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1269 }
1270
1271 static void tx6qdl_set_cpu_clock(void)
1272 {
1273         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1274
1275         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1276                 return;
1277
1278         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1279                 printf("%s detected; skipping cpu clock change\n",
1280                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1281                 return;
1282         }
1283         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1284                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1285                 printf("CPU clock set to %lu.%03lu MHz\n",
1286                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1287         } else {
1288                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1289         }
1290 }
1291
1292 int board_late_init(void)
1293 {
1294         int ret = 0;
1295         const char *baseboard;
1296 #if 1
1297         /* override secure_boot fuse */
1298         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1299         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1300
1301         writel(0x12, &fuse->cfg5);
1302 #endif
1303
1304         env_cleanup();
1305
1306         if (tx6_temp_check_enabled)
1307                 check_cpu_temperature(1);
1308
1309         tx6qdl_set_cpu_clock();
1310
1311         if (had_ctrlc())
1312                 setenv_ulong("safeboot", 1);
1313         else if (wrsr & WRSR_TOUT)
1314                 setenv_ulong("wdreset", 1);
1315         else
1316                 karo_fdt_move_fdt();
1317
1318         baseboard = getenv("baseboard");
1319         if (!baseboard)
1320                 goto exit;
1321
1322         printf("Baseboard: %s\n", baseboard);
1323
1324         if (strncmp(baseboard, "stk5", 4) == 0) {
1325                 if ((strlen(baseboard) == 4) ||
1326                         strcmp(baseboard, "stk5-v3") == 0) {
1327                         stk5v3_board_init();
1328                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1329                         const char *otg_mode = getenv("otg_mode");
1330
1331                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1332                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1333                                         otg_mode, baseboard);
1334                                 setenv("otg_mode", "none");
1335                         }
1336                         stk5v5_board_init();
1337                 } else {
1338                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1339                                 baseboard + 4);
1340                 }
1341         } else {
1342                 printf("WARNING: Unsupported baseboard: '%s'\n",
1343                         baseboard);
1344                 ret = -EINVAL;
1345         }
1346
1347 exit:
1348         tx6_init_mac();
1349
1350         gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1351         clear_ctrlc();
1352         return ret;
1353 }
1354
1355 #ifdef CONFIG_TX6_NAND
1356 #define TX6_FLASH_SZ    (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
1357 #else
1358 #ifdef CONFIG_MMC_BOOT_SIZE
1359 #define TX6_FLASH_SZ    (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
1360 #else
1361 #define TX6_FLASH_SZ    2
1362 #endif
1363 #endif /* CONFIG_TX6_NAND */
1364
1365 #define TX6_DDR_SZ      (ffs(PHYS_SDRAM_1_WIDTH / 16) - 1)
1366
1367 static char tx6_mem_table[] = {
1368         '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
1369         '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
1370         '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
1371         '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
1372         '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
1373         '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
1374         '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
1375         '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
1376         '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
1377         '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
1378         '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
1379         '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
1380 };
1381
1382 static inline char tx6_mem_suffix(void)
1383 {
1384         size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
1385
1386         debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
1387                 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
1388
1389         if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
1390                 return '?';
1391
1392         return tx6_mem_table[mem_idx];
1393 };
1394
1395 static struct {
1396         uchar addr;
1397         uchar rev;
1398 } tx6_mod_revs[] = {
1399         { 0x3c, 1, },
1400         { 0x32, 2, },
1401         { 0x33, 3, },
1402 };
1403
1404 static int tx6_get_mod_rev(unsigned int pmic_id)
1405 {
1406         if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
1407                 return tx6_mod_revs[pmic_id].rev;
1408
1409         return 0;
1410 }
1411
1412 static int tx6_pmic_probe(void)
1413 {
1414         int i;
1415
1416         tx6_i2c_recover();
1417         i2c_init_all();
1418
1419         for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
1420                 u8 i2c_addr = tx6_mod_revs[i].addr;
1421                 int ret = i2c_probe(i2c_addr);
1422
1423                 if (ret == 0) {
1424                         debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
1425                         return i;
1426                 }
1427                 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
1428         }
1429         return -EINVAL;
1430 }
1431
1432 int checkboard(void)
1433 {
1434         u32 cpurev = get_cpu_rev();
1435         int cpu_variant = (cpurev >> 12) & 0xff;
1436         int pmic_id;
1437
1438         tx6qdl_print_cpuinfo();
1439
1440         pmic_id = tx6_pmic_probe();
1441         if (pmic_id >= 0)
1442                 pmic_addr = tx6_mod_revs[pmic_id].addr;
1443
1444         printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
1445                 tx6_mod_suffix,
1446                 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
1447                 is_lvds(), tx6_get_mod_rev(pmic_id),
1448                 tx6_mem_suffix());
1449
1450         get_hab_status();
1451
1452         return 0;
1453 }
1454
1455 #ifdef CONFIG_SERIAL_TAG
1456 void get_board_serial(struct tag_serialnr *serialnr)
1457 {
1458         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1459         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1460
1461         serialnr->low = readl(&fuse->cfg0);
1462         serialnr->high = readl(&fuse->cfg1);
1463 }
1464 #endif
1465
1466 #if defined(CONFIG_OF_BOARD_SETUP)
1467 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1468 #include <jffs2/jffs2.h>
1469 #include <mtd_node.h>
1470 static struct node_info nodes[] = {
1471         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1472 };
1473 #else
1474 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1475 #endif
1476
1477 static const char *tx6_touchpanels[] = {
1478         "ti,tsc2007",
1479         "edt,edt-ft5x06",
1480         "eeti,egalax_ts",
1481 };
1482
1483 int ft_board_setup(void *blob, bd_t *bd)
1484 {
1485         const char *baseboard = getenv("baseboard");
1486         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1487         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1488         int ret;
1489
1490         ret = fdt_increase_size(blob, 4096);
1491         if (ret) {
1492                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1493                 return ret;
1494         }
1495         if (stk5_v5)
1496                 karo_fdt_enable_node(blob, "stk5led", 0);
1497
1498         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1499         fdt_fixup_ethernet(blob);
1500
1501         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1502                                 ARRAY_SIZE(tx6_touchpanels));
1503         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1504         karo_fdt_fixup_flexcan(blob, stk5_v5);
1505
1506         karo_fdt_update_fb_mode(blob, video_mode);
1507
1508         return 0;
1509 }
1510 #endif /* CONFIG_OF_BOARD_SETUP */