board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  38
  39 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  40 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  41 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  42
  43 #define TX6UL_I2C1_SCL_GPIO             IMX_GPIO_NR(5, 0)
  44 #define TX6UL_I2C1_SDA_GPIO             IMX_GPIO_NR(5, 1)
  45
  46 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  47
  48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  49 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  50 #else
  51 #define TEMPERATURE_MIN                 (-40)
  52 #endif
  53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  54 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  55 #else
  56 #define TEMPERATURE_HOT                 80
  57 #endif
  58
  59 DECLARE_GLOBAL_DATA_PTR;
  60
  61 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  62
  63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  64 #ifdef CONFIG_SECURE_BOOT
  65 char __csf_data[0] __attribute__((section(".__csf_data")));
  66 #endif
  67
  68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
  69         /* UART pads */
  70 #if CONFIG_MXC_UART_BASE == UART1_BASE
  71         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
  72         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
  73         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
  74         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
  75 #endif
  76 #if CONFIG_MXC_UART_BASE == UART2_BASE
  77         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
  78         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
  79         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
  80         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
  81 #endif
  82 #if CONFIG_MXC_UART_BASE == UART5_BASE
  83         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
  84         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
  85         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
  86         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
  87 #endif
  88         /* internal I2C */
  89         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION, /* I2C SCL */
  90         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION, /* I2C SDA */
  91
  92         /* FEC PHY GPIO functions */
  93         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
  94         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
  95         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
  96                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
  97 };
  98
  99 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
 100                                 PAD_CTL_DSE_48ohm |     \
 101                                 PAD_CTL_PUS_100K_UP |   \
 102                                 PAD_CTL_SRE_FAST)
 103 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
 104                                 PAD_CTL_DSE_60ohm |     \
 105                                 PAD_CTL_SRE_SLOW)
 106 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
 107                                 PAD_CTL_PUS_47K_UP)
 108
 109 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 110         /* FEC functions */
 111         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
 112                                 PAD_CTL_SPEED_MED),
 113         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 114                                 PAD_CTL_DSE_48ohm |
 115                                 PAD_CTL_SPEED_MED),
 116         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
 117                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
 118                                 PAD_CTL_DSE_40ohm |
 119                                 PAD_CTL_SRE_FAST),
 120         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 121         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 122         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 123         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 124         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 125         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 126         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 127
 128         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
 129                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
 130                                 PAD_CTL_DSE_48ohm |
 131                                 PAD_CTL_SRE_FAST),
 132         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 133         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 134         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 135         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 136         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 137         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 138         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 139 };
 140
 141 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
 142                                 PAD_CTL_SPEED_MED |     \
 143                                 PAD_CTL_DSE_34ohm |     \
 144                                 PAD_CTL_SRE_FAST)
 145
 146 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 147         /* internal I2C */
 148         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 149         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 150 };
 151
 152 static const struct gpio const tx6ul_gpios[] = {
 153         /* These two entries are used to forcefully reinitialize the I2C bus */
 154         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 155         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 156
 157         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 158         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 159         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 160 };
 161
 162 static int pmic_addr __maybe_unused __data = 0x3c;
 163
 164 #define GPIO_DR 0
 165 #define GPIO_DIR 4
 166 #define GPIO_PSR 8
 167
 168 static void tx6_i2c_recover(void)
 169 {
 170         int i;
 171         int bad = 0;
 172 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 173 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 174 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
 175
 176         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
 177                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
 178                 return;
 179
 180         debug("Clearing I2C bus\n");
 181         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
 182                 printf("I2C SCL stuck LOW\n");
 183                 bad++;
 184
 185                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
 186                         I2C_GPIO_BASE + GPIO_DR);
 187                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
 188                         I2C_GPIO_BASE + GPIO_DIR);
 189         }
 190         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
 191                 printf("I2C SDA stuck LOW\n");
 192                 bad++;
 193
 194                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
 195                         I2C_GPIO_BASE + GPIO_DIR);
 196                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
 197                         I2C_GPIO_BASE + GPIO_DR);
 198                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
 199                         I2C_GPIO_BASE + GPIO_DIR);
 200
 201                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 202                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
 203                 udelay(10);
 204
 205                 for (i = 0; i < 18; i++) {
 206                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
 207
 208                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 209                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
 210                         udelay(10);
 211                         if (reg & SCL_BIT &&
 212                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
 213                                 break;
 214                 }
 215         }
 216         if (bad) {
 217                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
 218
 219                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
 220                         printf("I2C bus recovery succeeded\n");
 221                 } else {
 222                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
 223                                 SCL_BIT | SDA_BIT);
 224                 }
 225         }
 226         debug("Setting up I2C Pads\n");
 227 }
 228
 229 /* placed in section '.data' to prevent overwriting relocation info
 230  * overlayed with bss
 231  */
 232 static u32 wrsr __data;
 233
 234 #define WRSR_POR                        (1 << 4)
 235 #define WRSR_TOUT                       (1 << 1)
 236 #define WRSR_SFTW                       (1 << 0)
 237
 238 static void print_reset_cause(void)
 239 {
 240         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 241         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 242         u32 srsr;
 243         char *dlm = "";
 244
 245         printf("Reset cause: ");
 246
 247         srsr = readl(&src_regs->srsr);
 248         wrsr = readw(wdt_base + 4);
 249
 250         if (wrsr & WRSR_POR) {
 251                 printf("%sPOR", dlm);
 252                 dlm = " | ";
 253         }
 254         if (srsr & 0x00004) {
 255                 printf("%sCSU", dlm);
 256                 dlm = " | ";
 257         }
 258         if (srsr & 0x00008) {
 259                 printf("%sIPP USER", dlm);
 260                 dlm = " | ";
 261         }
 262         if (srsr & 0x00010) {
 263                 if (wrsr & WRSR_SFTW) {
 264                         printf("%sSOFT", dlm);
 265                         dlm = " | ";
 266                 }
 267                 if (wrsr & WRSR_TOUT) {
 268                         printf("%sWDOG", dlm);
 269                         dlm = " | ";
 270                 }
 271         }
 272         if (srsr & 0x00020) {
 273                 printf("%sJTAG HIGH-Z", dlm);
 274                 dlm = " | ";
 275         }
 276         if (srsr & 0x00040) {
 277                 printf("%sJTAG SW", dlm);
 278                 dlm = " | ";
 279         }
 280         if (srsr & 0x10000) {
 281                 printf("%sWARM BOOT", dlm);
 282                 dlm = " | ";
 283         }
 284         if (dlm[0] == '\0')
 285                 printf("unknown");
 286
 287         printf("\n");
 288 }
 289
 290 #ifdef CONFIG_IMX6_THERMAL
 291 #include <thermal.h>
 292 #include <imx_thermal.h>
 293 #include <fuse.h>
 294
 295 static void print_temperature(void)
 296 {
 297         struct udevice *thermal_dev;
 298         int cpu_tmp, minc, maxc, ret;
 299         char const *grade_str;
 300         static u32 __data thermal_calib;
 301
 302         puts("Temperature: ");
 303         switch (get_cpu_temp_grade(&minc, &maxc)) {
 304         case TEMP_AUTOMOTIVE:
 305                 grade_str = "Automotive";
 306                 break;
 307         case TEMP_INDUSTRIAL:
 308                 grade_str = "Industrial";
 309                 break;
 310         case TEMP_EXTCOMMERCIAL:
 311                 grade_str = "Extended Commercial";
 312                 break;
 313         default:
 314                 grade_str = "Commercial";
 315         }
 316         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 317         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 318         if (ret == 0) {
 319                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 320
 321                 if (ret == 0)
 322                         printf(" at %dC", cpu_tmp);
 323                 else
 324                         puts(" - failed to read sensor data");
 325         } else {
 326                 puts(" - no sensor device found");
 327         }
 328
 329         if (fuse_read(1, 6, &thermal_calib) == 0) {
 330                 printf(" - calibration data 0x%08x\n", thermal_calib);
 331         } else {
 332                 puts(" - Failed to read thermal calib fuse\n");
 333         }
 334 }
 335 #else
 336 static inline void print_temperature(void)
 337 {
 338 }
 339 #endif
 340
 341 int checkboard(void)
 342 {
 343         u32 cpurev = get_cpu_rev();
 344         char *cpu_str = "?";
 345
 346         switch ((cpurev >> 12) & 0xff) {
 347         case MXC_CPU_MX6SL:
 348                 cpu_str = "SL";
 349                 break;
 350         case MXC_CPU_MX6DL:
 351                 cpu_str = "DL";
 352                 break;
 353         case MXC_CPU_MX6SOLO:
 354                 cpu_str = "SOLO";
 355                 break;
 356         case MXC_CPU_MX6Q:
 357                 cpu_str = "Q";
 358                 break;
 359         case MXC_CPU_MX6UL:
 360                 cpu_str = "UL";
 361                 break;
 362         }
 363
 364         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 365                 cpu_str,
 366                 (cpurev & 0x000F0) >> 4,
 367                 (cpurev & 0x0000F) >> 0,
 368                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 369
 370         print_temperature();
 371         print_reset_cause();
 372 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 373         check_cpu_temperature(1);
 374 #endif
 375         tx6_i2c_recover();
 376         return 0;
 377 }
 378
 379 /* serial port not initialized at this point */
 380 int board_early_init_f(void)
 381 {
 382         return 0;
 383 }
 384
 385 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 386 static bool tx6_temp_check_enabled = true;
 387 #else
 388 #define tx6_temp_check_enabled  0
 389 #endif
 390
 391 static inline u8 tx6ul_mem_suffix(void)
 392 {
 393 #ifdef CONFIG_TX6_NAND
 394         return '0';
 395 #else
 396         return '1';
 397 #endif
 398 }
 399
 400 int board_init(void)
 401 {
 402         int ret;
 403
 404         debug("%s@%d: \n", __func__, __LINE__);
 405
 406         printf("Board: Ka-Ro TXUL-001%c\n",
 407                 tx6ul_mem_suffix());
 408
 409         get_hab_status();
 410
 411         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 412         if (ret < 0) {
 413                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 414         }
 415         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 416
 417         /* Address of boot parameters */
 418         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 419         gd->bd->bi_arch_number = -1;
 420
 421         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 422                 if (wrsr & WRSR_TOUT)
 423                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 424                 else
 425                         printf("<CTRL-C> detected; safeboot enabled\n");
 426 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 427                 tx6_temp_check_enabled = false;
 428 #endif
 429                 return 0;
 430         }
 431
 432         ret = tx6_pmic_init(pmic_addr);
 433         if (ret) {
 434                 printf("Failed to setup PMIC voltages: %d\n", ret);
 435 //              hang();
 436         }
 437         return 0;
 438 }
 439
 440 int dram_init(void)
 441 {
 442         debug("%s@%d: \n", __func__, __LINE__);
 443
 444         /* dram_init must store complete ramsize in gd->ram_size */
 445         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 446                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 447         return 0;
 448 }
 449
 450 void dram_init_banksize(void)
 451 {
 452         debug("%s@%d: \n", __func__, __LINE__);
 453
 454         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 455         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 456                         PHYS_SDRAM_1_SIZE);
 457 #if CONFIG_NR_DRAM_BANKS > 1
 458         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 459         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 460                         PHYS_SDRAM_2_SIZE);
 461 #endif
 462 }
 463
 464 #ifdef  CONFIG_FSL_ESDHC
 465 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
 466                                 PAD_CTL_SPEED_MED |     \
 467                                 PAD_CTL_DSE_40ohm |     \
 468                                 PAD_CTL_SRE_FAST)
 469
 470 static const iomux_v3_cfg_t mmc0_pads[] = {
 471         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 472         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 473         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 474         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 475         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 476         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 477         /* SD1 CD */
 478         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 479 };
 480
 481 #ifdef CONFIG_TX6_EMMC
 482 static const iomux_v3_cfg_t mmc1_pads[] = {
 483         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 484         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 485         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 486         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 487         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 488         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 489         /* eMMC RESET */
 490         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 491                                                 PAD_CTL_DSE_40ohm),
 492 };
 493 #endif
 494
 495 static struct tx6_esdhc_cfg {
 496         const iomux_v3_cfg_t *pads;
 497         int num_pads;
 498         enum mxc_clock clkid;
 499         struct fsl_esdhc_cfg cfg;
 500         int cd_gpio;
 501 } tx6ul_esdhc_cfg[] = {
 502 #ifdef CONFIG_TX6_EMMC
 503         {
 504                 .pads = mmc1_pads,
 505                 .num_pads = ARRAY_SIZE(mmc1_pads),
 506                 .clkid = MXC_ESDHC2_CLK,
 507                 .cfg = {
 508                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 509                         .max_bus_width = 4,
 510                 },
 511                 .cd_gpio = -EINVAL,
 512         },
 513 #endif
 514         {
 515                 .pads = mmc0_pads,
 516                 .num_pads = ARRAY_SIZE(mmc0_pads),
 517                 .clkid = MXC_ESDHC_CLK,
 518                 .cfg = {
 519                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 520                         .max_bus_width = 4,
 521                 },
 522                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 523         },
 524 };
 525
 526 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 527 {
 528         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 529 }
 530
 531 int board_mmc_getcd(struct mmc *mmc)
 532 {
 533         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 534
 535         if (cfg->cd_gpio < 0)
 536                 return 1;
 537
 538         debug("SD card %d is %spresent (GPIO %d)\n",
 539                 cfg - tx6ul_esdhc_cfg,
 540                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 541                 cfg->cd_gpio);
 542         return !gpio_get_value(cfg->cd_gpio);
 543 }
 544
 545 int board_mmc_init(bd_t *bis)
 546 {
 547         int i;
 548
 549         debug("%s@%d: \n", __func__, __LINE__);
 550
 551         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 552                 struct mmc *mmc;
 553                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 554                 int ret;
 555
 556                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 557                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 558
 559                 if (cfg->cd_gpio >= 0) {
 560                         ret = gpio_request_one(cfg->cd_gpio,
 561                                         GPIOFLAG_INPUT, "MMC CD");
 562                         if (ret) {
 563                                 printf("Error %d requesting GPIO%d_%d\n",
 564                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 565                                 continue;
 566                         }
 567                 }
 568
 569                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 570                 fsl_esdhc_initialize(bis, &cfg->cfg);
 571
 572                 mmc = find_mmc_device(i);
 573                 if (mmc == NULL)
 574                         continue;
 575                 if (board_mmc_getcd(mmc))
 576                         mmc_init(mmc);
 577         }
 578         return 0;
 579 }
 580 #endif /* CONFIG_CMD_MMC */
 581
 582 #ifdef CONFIG_FEC_MXC
 583
 584 #ifndef ETH_ALEN
 585 #define ETH_ALEN 6
 586 #endif
 587
 588 int board_eth_init(bd_t *bis)
 589 {
 590         int ret;
 591
 592         debug("%s@%d: \n", __func__, __LINE__);
 593
 594         /* delay at least 21ms for the PHY internal POR signal to deassert */
 595         udelay(22000);
 596
 597         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
 598                                         ARRAY_SIZE(tx6ul_enet1_pads));
 599
 600         /* Deassert RESET to the external phy */
 601         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
 602
 603         if (getenv("ethaddr")) {
 604                 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
 605                 if (ret) {
 606                         printf("failed to initialize FEC0: %d\n", ret);
 607                         return ret;
 608                 }
 609         }
 610         if (getenv("eth1addr")) {
 611                 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
 612                 if (ret) {
 613                         printf("failed to initialize FEC1: %d\n", ret);
 614                         return ret;
 615                 }
 616         }
 617         return 0;
 618 }
 619
 620 static void tx6_init_mac(void)
 621 {
 622         u8 mac[ETH_ALEN];
 623
 624         imx_get_mac_from_fuse(0, mac);
 625         if (!is_valid_ethaddr(mac)) {
 626                 printf("No valid MAC address programmed\n");
 627                 return;
 628         }
 629
 630         printf("MAC addr from fuse: %pM\n", mac);
 631         eth_setenv_enetaddr("ethaddr", mac);
 632
 633         imx_get_mac_from_fuse(1, mac);
 634         eth_setenv_enetaddr("eth1addr", mac);
 635 }
 636 #else
 637 static inline void tx6_init_mac(void)
 638 {
 639 }
 640 #endif /* CONFIG_FEC_MXC */
 641
 642 enum {
 643         LED_STATE_INIT = -1,
 644         LED_STATE_OFF,
 645         LED_STATE_ON,
 646 };
 647
 648 static inline int calc_blink_rate(void)
 649 {
 650         if (!tx6_temp_check_enabled)
 651                 return CONFIG_SYS_HZ;
 652
 653         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 654                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 655                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 656 }
 657
 658 void show_activity(int arg)
 659 {
 660         static int led_state = LED_STATE_INIT;
 661         static int blink_rate;
 662         static ulong last;
 663
 664         if (led_state == LED_STATE_INIT) {
 665                 last = get_timer(0);
 666                 gpio_set_value(TX6UL_LED_GPIO, 1);
 667                 led_state = LED_STATE_ON;
 668                 blink_rate = calc_blink_rate();
 669         } else {
 670                 if (get_timer(last) > blink_rate) {
 671                         blink_rate = calc_blink_rate();
 672                         last = get_timer_masked();
 673                         if (led_state == LED_STATE_ON) {
 674                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 675                         } else {
 676                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 677                         }
 678                         led_state = 1 - led_state;
 679                 }
 680         }
 681 }
 682
 683 static const iomux_v3_cfg_t stk5_pads[] = {
 684         /* SW controlled LED on STK5 baseboard */
 685         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 686
 687         /* I2C bus on DIMM pins 40/41 */
 688         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 689         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 690
 691         /* TSC200x PEN IRQ */
 692         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
 693 #if 0
 694         /* EDT-FT5x06 Polytouch panel */
 695         MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
 696         MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
 697         MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
 698
 699         /* USBH1 */
 700         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
 701         MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
 702         /* USBOTG */
 703         MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
 704         MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
 705         MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
 706 #endif
 707 };
 708
 709 static const struct gpio stk5_gpios[] = {
 710         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 711
 712         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 713         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 714         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 715         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 716         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 717 };
 718
 719 #ifdef CONFIG_LCD
 720 static u16 tx6_cmap[256];
 721 vidinfo_t panel_info = {
 722         /* set to max. size supported by SoC */
 723         .vl_col = 1920,
 724         .vl_row = 1080,
 725
 726         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 727         .cmap = tx6_cmap,
 728 };
 729
 730 static struct fb_videomode tx6_fb_modes[] = {
 731 #ifndef CONFIG_SYS_LVDS_IF
 732         {
 733                 /* Standard VGA timing */
 734                 .name           = "VGA",
 735                 .refresh        = 60,
 736                 .xres           = 640,
 737                 .yres           = 480,
 738                 .pixclock       = KHZ2PICOS(25175),
 739                 .left_margin    = 48,
 740                 .hsync_len      = 96,
 741                 .right_margin   = 16,
 742                 .upper_margin   = 31,
 743                 .vsync_len      = 2,
 744                 .lower_margin   = 12,
 745                 .sync           = FB_SYNC_CLK_LAT_FALL,
 746         },
 747         {
 748                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 749                  * DE high active, 115.2 mm x 86.4 mm display area
 750                  * VGA compatible timing
 751                  */
 752                 .name           = "ETV570",
 753                 .refresh        = 60,
 754                 .xres           = 640,
 755                 .yres           = 480,
 756                 .pixclock       = KHZ2PICOS(25175),
 757                 .left_margin    = 114,
 758                 .hsync_len      = 30,
 759                 .right_margin   = 16,
 760                 .upper_margin   = 32,
 761                 .vsync_len      = 3,
 762                 .lower_margin   = 10,
 763                 .sync           = FB_SYNC_CLK_LAT_FALL,
 764         },
 765         {
 766                 /* Emerging ET0350G0DH6 320 x 240 display.
 767                  * 70.08 mm x 52.56 mm display area.
 768                  */
 769                 .name           = "ET0350",
 770                 .refresh        = 60,
 771                 .xres           = 320,
 772                 .yres           = 240,
 773                 .pixclock       = KHZ2PICOS(6500),
 774                 .left_margin    = 68 - 34,
 775                 .hsync_len      = 34,
 776                 .right_margin   = 20,
 777                 .upper_margin   = 18 - 3,
 778                 .vsync_len      = 3,
 779                 .lower_margin   = 4,
 780                 .sync           = FB_SYNC_CLK_LAT_FALL,
 781         },
 782         {
 783                 /* Emerging ET0430G0DH6 480 x 272 display.
 784                  * 95.04 mm x 53.856 mm display area.
 785                  */
 786                 .name           = "ET0430",
 787                 .refresh        = 60,
 788                 .xres           = 480,
 789                 .yres           = 272,
 790                 .pixclock       = KHZ2PICOS(9000),
 791                 .left_margin    = 2,
 792                 .hsync_len      = 41,
 793                 .right_margin   = 2,
 794                 .upper_margin   = 2,
 795                 .vsync_len      = 10,
 796                 .lower_margin   = 2,
 797         },
 798         {
 799                 /* Emerging ET0500G0DH6 800 x 480 display.
 800                  * 109.6 mm x 66.4 mm display area.
 801                  */
 802                 .name           = "ET0500",
 803                 .refresh        = 60,
 804                 .xres           = 800,
 805                 .yres           = 480,
 806                 .pixclock       = KHZ2PICOS(33260),
 807                 .left_margin    = 216 - 128,
 808                 .hsync_len      = 128,
 809                 .right_margin   = 1056 - 800 - 216,
 810                 .upper_margin   = 35 - 2,
 811                 .vsync_len      = 2,
 812                 .lower_margin   = 525 - 480 - 35,
 813                 .sync           = FB_SYNC_CLK_LAT_FALL,
 814         },
 815         {
 816                 /* Emerging ETQ570G0DH6 320 x 240 display.
 817                  * 115.2 mm x 86.4 mm display area.
 818                  */
 819                 .name           = "ETQ570",
 820                 .refresh        = 60,
 821                 .xres           = 320,
 822                 .yres           = 240,
 823                 .pixclock       = KHZ2PICOS(6400),
 824                 .left_margin    = 38,
 825                 .hsync_len      = 30,
 826                 .right_margin   = 30,
 827                 .upper_margin   = 16, /* 15 according to datasheet */
 828                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 829                 .lower_margin   = 4, /* 4.5 according to datasheet */
 830                 .sync           = FB_SYNC_CLK_LAT_FALL,
 831         },
 832         {
 833                 /* Emerging ET0700G0DH6 800 x 480 display.
 834                  * 152.4 mm x 91.44 mm display area.
 835                  */
 836                 .name           = "ET0700",
 837                 .refresh        = 60,
 838                 .xres           = 800,
 839                 .yres           = 480,
 840                 .pixclock       = KHZ2PICOS(33260),
 841                 .left_margin    = 216 - 128,
 842                 .hsync_len      = 128,
 843                 .right_margin   = 1056 - 800 - 216,
 844                 .upper_margin   = 35 - 2,
 845                 .vsync_len      = 2,
 846                 .lower_margin   = 525 - 480 - 35,
 847                 .sync           = FB_SYNC_CLK_LAT_FALL,
 848         },
 849         {
 850                 /* Emerging ET070001DM6 800 x 480 display.
 851                  * 152.4 mm x 91.44 mm display area.
 852                  */
 853                 .name           = "ET070001DM6",
 854                 .refresh        = 60,
 855                 .xres           = 800,
 856                 .yres           = 480,
 857                 .pixclock       = KHZ2PICOS(33260),
 858                 .left_margin    = 216 - 128,
 859                 .hsync_len      = 128,
 860                 .right_margin   = 1056 - 800 - 216,
 861                 .upper_margin   = 35 - 2,
 862                 .vsync_len      = 2,
 863                 .lower_margin   = 525 - 480 - 35,
 864                 .sync           = 0,
 865         },
 866 #else
 867         {
 868                 /* HannStar HSD100PXN1
 869                  * 202.7m mm x 152.06 mm display area.
 870                  */
 871                 .name           = "HSD100PXN1",
 872                 .refresh        = 60,
 873                 .xres           = 1024,
 874                 .yres           = 768,
 875                 .pixclock       = KHZ2PICOS(65000),
 876                 .left_margin    = 0,
 877                 .hsync_len      = 0,
 878                 .right_margin   = 320,
 879                 .upper_margin   = 0,
 880                 .vsync_len      = 0,
 881                 .lower_margin   = 38,
 882                 .sync           = FB_SYNC_CLK_LAT_FALL,
 883         },
 884 #endif
 885         {
 886                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 887                 .refresh        = 60,
 888                 .left_margin    = 48,
 889                 .hsync_len      = 96,
 890                 .right_margin   = 16,
 891                 .upper_margin   = 31,
 892                 .vsync_len      = 2,
 893                 .lower_margin   = 12,
 894                 .sync           = FB_SYNC_CLK_LAT_FALL,
 895         },
 896 };
 897
 898 static int lcd_enabled = 1;
 899 static int lcd_bl_polarity;
 900
 901 static int lcd_backlight_polarity(void)
 902 {
 903         return lcd_bl_polarity;
 904 }
 905
 906 void lcd_enable(void)
 907 {
 908         /* HACK ALERT:
 909          * global variable from common/lcd.c
 910          * Set to 0 here to prevent messages from going to LCD
 911          * rather than serial console
 912          */
 913         lcd_is_enabled = 0;
 914
 915         if (lcd_enabled) {
 916                 karo_load_splashimage(1);
 917
 918                 debug("Switching LCD on\n");
 919                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
 920                 udelay(100);
 921                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
 922                 udelay(300000);
 923                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
 924                         lcd_backlight_polarity());
 925         }
 926 }
 927
 928 void lcd_disable(void)
 929 {
 930         if (lcd_enabled) {
 931                 printf("Disabling LCD\n");
 932 //              ipuv3_fb_shutdown();
 933         }
 934 }
 935
 936 void lcd_panel_disable(void)
 937 {
 938         if (lcd_enabled) {
 939                 debug("Switching LCD off\n");
 940                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
 941                         !lcd_backlight_polarity());
 942                 gpio_set_value(TX6UL_LCD_RST_GPIO, 0);
 943                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 0);
 944         }
 945 }
 946
 947 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 948 #if 1
 949         /* LCD RESET */
 950         MX6_PAD_LCD_RESET__LCDIF_RESET,
 951         /* LCD POWER_ENABLE */
 952         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 953         /* LCD Backlight (PWM) */
 954         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 955 #endif
 956 #ifdef CONFIG_LCD
 957         /* Display */
 958         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 959         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
 960         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
 961         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
 962         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
 963         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
 964         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
 965         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
 966         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
 967         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
 968         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
 969         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
 970         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
 971         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
 972         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
 973         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
 974         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
 975         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
 976         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
 977         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
 978         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
 979         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
 980         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
 981         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
 982         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
 983         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
 984         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
 985         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
 986 #endif
 987 };
 988
 989 static const struct gpio stk5_lcd_gpios[] = {
 990 //      { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
 991         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
 992         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
 993 };
 994
 995 void lcd_ctrl_init(void *lcdbase)
 996 {
 997         int color_depth = 24;
 998         const char *video_mode = karo_get_vmode(getenv("video_mode"));
 999         const char *vm;
1000         unsigned long val;
1001         int refresh = 60;
1002         struct fb_videomode *p = &tx6_fb_modes[0];
1003         struct fb_videomode fb_mode;
1004         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1005         int pix_fmt;
1006         int lcd_bus_width;
1007
1008         if (!lcd_enabled) {
1009                 debug("LCD disabled\n");
1010                 return;
1011         }
1012
1013         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1014                 debug("Disabling LCD\n");
1015                 lcd_enabled = 0;
1016                 setenv("splashimage", NULL);
1017                 return;
1018         }
1019
1020         karo_fdt_move_fdt();
1021         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1022
1023         if (video_mode == NULL) {
1024                 debug("Disabling LCD\n");
1025                 lcd_enabled = 0;
1026                 return;
1027         }
1028         vm = video_mode;
1029         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1030                 p = &fb_mode;
1031                 debug("Using video mode from FDT\n");
1032                 vm += strlen(vm);
1033                 if (fb_mode.xres > panel_info.vl_col ||
1034                         fb_mode.yres > panel_info.vl_row) {
1035                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1036                                 fb_mode.xres, fb_mode.yres,
1037                                 panel_info.vl_col, panel_info.vl_row);
1038                         lcd_enabled = 0;
1039                         return;
1040                 }
1041         }
1042         if (p->name != NULL)
1043                 debug("Trying compiled-in video modes\n");
1044         while (p->name != NULL) {
1045                 if (strcmp(p->name, vm) == 0) {
1046                         debug("Using video mode: '%s'\n", p->name);
1047                         vm += strlen(vm);
1048                         break;
1049                 }
1050                 p++;
1051         }
1052         if (*vm != '\0')
1053                 debug("Trying to decode video_mode: '%s'\n", vm);
1054         while (*vm != '\0') {
1055                 if (*vm >= '0' && *vm <= '9') {
1056                         char *end;
1057
1058                         val = simple_strtoul(vm, &end, 0);
1059                         if (end > vm) {
1060                                 if (!xres_set) {
1061                                         if (val > panel_info.vl_col)
1062                                                 val = panel_info.vl_col;
1063                                         p->xres = val;
1064                                         panel_info.vl_col = val;
1065                                         xres_set = 1;
1066                                 } else if (!yres_set) {
1067                                         if (val > panel_info.vl_row)
1068                                                 val = panel_info.vl_row;
1069                                         p->yres = val;
1070                                         panel_info.vl_row = val;
1071                                         yres_set = 1;
1072                                 } else if (!bpp_set) {
1073                                         switch (val) {
1074                                         case 32:
1075                                         case 24:
1076                                                 if (is_lvds())
1077                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1078                                                 /* fallthru */
1079                                         case 16:
1080                                         case 8:
1081                                                 color_depth = val;
1082                                                 break;
1083
1084                                         case 18:
1085                                                 if (is_lvds()) {
1086                                                         color_depth = val;
1087                                                         break;
1088                                                 }
1089                                                 /* fallthru */
1090                                         default:
1091                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1092                                                         end - vm, vm, color_depth);
1093                                         }
1094                                         bpp_set = 1;
1095                                 } else if (!refresh_set) {
1096                                         refresh = val;
1097                                         refresh_set = 1;
1098                                 }
1099                         }
1100                         vm = end;
1101                 }
1102                 switch (*vm) {
1103                 case '@':
1104                         bpp_set = 1;
1105                         /* fallthru */
1106                 case '-':
1107                         yres_set = 1;
1108                         /* fallthru */
1109                 case 'x':
1110                         xres_set = 1;
1111                         /* fallthru */
1112                 case 'M':
1113                 case 'R':
1114                         vm++;
1115                         break;
1116
1117                 default:
1118                         if (*vm != '\0')
1119                                 vm++;
1120                 }
1121         }
1122         if (p->xres == 0 || p->yres == 0) {
1123                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1124                 lcd_enabled = 0;
1125                 printf("Supported video modes are:");
1126                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1127                         printf(" %s", p->name);
1128                 }
1129                 printf("\n");
1130                 return;
1131         }
1132         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1133                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1134                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1135                 lcd_enabled = 0;
1136                 return;
1137         }
1138         panel_info.vl_col = p->xres;
1139         panel_info.vl_row = p->yres;
1140
1141         switch (color_depth) {
1142         case 8:
1143                 panel_info.vl_bpix = LCD_COLOR8;
1144                 break;
1145         case 16:
1146                 panel_info.vl_bpix = LCD_COLOR16;
1147                 break;
1148         default:
1149                 panel_info.vl_bpix = LCD_COLOR32;
1150         }
1151
1152         p->pixclock = KHZ2PICOS(refresh *
1153                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1154                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1155                                 1000);
1156         debug("Pixel clock set to %lu.%03lu MHz\n",
1157                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1158
1159         if (p != &fb_mode) {
1160                 int ret;
1161
1162                 debug("Creating new display-timing node from '%s'\n",
1163                         video_mode);
1164                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1165                 if (ret)
1166                         printf("Failed to create new display-timing node from '%s': %d\n",
1167                                 video_mode, ret);
1168         }
1169
1170         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1171         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1172                                         ARRAY_SIZE(stk5_lcd_pads));
1173
1174         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1175         switch (lcd_bus_width) {
1176         case 24:
1177                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1178                 break;
1179
1180         case 18:
1181                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1182                 break;
1183
1184         case 16:
1185                 if (!is_lvds()) {
1186                         pix_fmt = IPU_PIX_FMT_RGB565;
1187                         break;
1188                 }
1189                 /* fallthru */
1190         default:
1191                 lcd_enabled = 0;
1192                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1193                         lcd_bus_width);
1194                 return;
1195         }
1196         if (is_lvds()) {
1197                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1198                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1199                 uint32_t gpr2;
1200                 uint32_t gpr3;
1201
1202                 if (lvds_chan_mask == 0) {
1203                         printf("No LVDS channel active\n");
1204                         lcd_enabled = 0;
1205                         return;
1206                 }
1207
1208                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1209                 if (lcd_bus_width == 24)
1210                         gpr2 |= (1 << 5) | (1 << 7);
1211                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1212                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1213                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1214                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1215
1216                 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1217                 gpr3 &= ~((3 << 8) | (3 << 6));
1218                 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1219         }
1220         if (karo_load_splashimage(0) == 0) {
1221 #if 0
1222                 int ret;
1223
1224                 debug("Initializing LCD controller\n");
1225                 ret = ipuv3_fb_init(p, 0, pix_fmt,
1226                                 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1227                                 di_clk_rate, -1);
1228                 if (ret) {
1229                         printf("Failed to initialize FB driver: %d\n", ret);
1230                         lcd_enabled = 0;
1231                 }
1232 #else
1233                 lcd_enabled = pix_fmt * 0;
1234 #endif
1235         } else {
1236                 debug("Skipping initialization of LCD controller\n");
1237         }
1238 }
1239 #else
1240 #define lcd_enabled 0
1241 #endif /* CONFIG_LCD */
1242
1243 static void stk5_board_init(void)
1244 {
1245         int ret;
1246
1247         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1248         if (ret < 0) {
1249                 printf("Failed to request stk5_gpios: %d\n", ret);
1250                 return;
1251         }
1252         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1253 debug("%s@%d: \n", __func__, __LINE__);
1254 }
1255
1256 static void stk5v3_board_init(void)
1257 {
1258 debug("%s@%d: \n", __func__, __LINE__);
1259         stk5_board_init();
1260 debug("%s@%d: \n", __func__, __LINE__);
1261 }
1262
1263 static void stk5v5_board_init(void)
1264 {
1265         int ret;
1266
1267         stk5_board_init();
1268
1269         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1270                         "Flexcan Transceiver");
1271         if (ret) {
1272                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1273                 return;
1274         }
1275
1276         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1277                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1278 }
1279
1280 static void tx6ul_set_cpu_clock(void)
1281 {
1282         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1283
1284         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1285                 return;
1286
1287         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1288                 printf("%s detected; skipping cpu clock change\n",
1289                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1290                 return;
1291         }
1292         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1293                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1294                 printf("CPU clock set to %lu.%03lu MHz\n",
1295                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1296         } else {
1297                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1298         }
1299 }
1300
1301 int board_late_init(void)
1302 {
1303         int ret = 0;
1304         const char *baseboard;
1305
1306         debug("%s@%d: \n", __func__, __LINE__);
1307
1308         env_cleanup();
1309
1310         if (tx6_temp_check_enabled)
1311                 check_cpu_temperature(1);
1312
1313         tx6ul_set_cpu_clock();
1314
1315         if (had_ctrlc())
1316                 setenv_ulong("safeboot", 1);
1317         else if (wrsr & WRSR_TOUT)
1318                 setenv_ulong("wdreset", 1);
1319         else
1320                 karo_fdt_move_fdt();
1321
1322         baseboard = getenv("baseboard");
1323         if (!baseboard)
1324                 goto exit;
1325
1326         printf("Baseboard: %s\n", baseboard);
1327
1328         if (strncmp(baseboard, "stk5", 4) == 0) {
1329                 if ((strlen(baseboard) == 4) ||
1330                         strcmp(baseboard, "stk5-v3") == 0) {
1331                         stk5v3_board_init();
1332                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1333                         const char *otg_mode = getenv("otg_mode");
1334
1335                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1336                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1337                                         otg_mode, baseboard);
1338                                 setenv("otg_mode", "none");
1339                         }
1340                         stk5v5_board_init();
1341                 } else {
1342                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1343                                 baseboard + 4);
1344                 }
1345         } else {
1346                 printf("WARNING: Unsupported baseboard: '%s'\n",
1347                         baseboard);
1348                 ret = -EINVAL;
1349         }
1350
1351 exit:
1352 debug("%s@%d: \n", __func__, __LINE__);
1353         tx6_init_mac();
1354 debug("%s@%d: \n", __func__, __LINE__);
1355
1356         clear_ctrlc();
1357         return ret;
1358 }
1359
1360 #ifdef CONFIG_SERIAL_TAG
1361 void get_board_serial(struct tag_serialnr *serialnr)
1362 {
1363         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1364         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1365
1366         serialnr->low = readl(&fuse->cfg0);
1367         serialnr->high = readl(&fuse->cfg1);
1368 }
1369 #endif
1370
1371 #if defined(CONFIG_OF_BOARD_SETUP)
1372 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1373 #include <jffs2/jffs2.h>
1374 #include <mtd_node.h>
1375 static struct node_info nodes[] = {
1376         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1377 };
1378 #else
1379 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1380 #endif
1381
1382 static const char *tx6_touchpanels[] = {
1383         "ti,tsc2007",
1384         "edt,edt-ft5x06",
1385         "eeti,egalax_ts",
1386 };
1387
1388 int ft_board_setup(void *blob, bd_t *bd)
1389 {
1390         const char *baseboard = getenv("baseboard");
1391         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1392         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1393         int ret;
1394
1395         ret = fdt_increase_size(blob, 4096);
1396         if (ret) {
1397                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1398                 return ret;
1399         }
1400         if (stk5_v5)
1401                 karo_fdt_enable_node(blob, "stk5led", 0);
1402
1403         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1404         fdt_fixup_ethernet(blob);
1405
1406         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1407                                 ARRAY_SIZE(tx6_touchpanels));
1408         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1409         karo_fdt_fixup_flexcan(blob, stk5_v5);
1410
1411         karo_fdt_update_fb_mode(blob, video_mode);
1412
1413         return 0;
1414 }
1415 #endif /* CONFIG_OF_BOARD_SETUP */