board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37
  38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
  39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
  40
  41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  42
  43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  46
  47 #ifdef CONFIG_SYS_I2C_SOFT
  48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  50 #endif
  51
  52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  70 #ifdef CONFIG_SECURE_BOOT
  71 char __csf_data[0] __attribute__((section(".__csf_data")));
  72 #endif
  73
  74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  75                                         PAD_CTL_SPEED_MED |             \
  76                                         PAD_CTL_DSE_40ohm |             \
  77                                         PAD_CTL_SRE_FAST)
  78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  79                                         PAD_CTL_ODE |                   \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_34ohm |             \
  83                                         PAD_CTL_SRE_FAST)
  84 #define TX6UL_I2C_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  85                                         PAD_CTL_HYS |                   \
  86                                         PAD_CTL_DSE_34ohm |             \
  87                                         PAD_CTL_SPEED_MED)
  88 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
  89                                         PAD_CTL_DSE_48ohm |             \
  90                                         PAD_CTL_PUS_100K_UP |           \
  91                                         PAD_CTL_SRE_FAST)
  92 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  93                                         PAD_CTL_DSE_60ohm |             \
  94                                         PAD_CTL_SRE_SLOW)
  95 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  96                                         PAD_CTL_PUS_47K_UP)
  97
  98
  99 static const iomux_v3_cfg_t const tx6ul_pads[] = {
 100         /* UART pads */
 101 #if CONFIG_MXC_UART_BASE == UART1_BASE
 102         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 103         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 104         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 105         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 106 #endif
 107 #if CONFIG_MXC_UART_BASE == UART2_BASE
 108         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 109         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 110         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 111         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 112 #endif
 113 #if CONFIG_MXC_UART_BASE == UART5_BASE
 114         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 115         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 116         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 117         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 118 #endif
 119         /* FEC PHY GPIO functions */
 120         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
 121         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
 122         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 123 };
 124
 125 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 126         /* FEC functions */
 127         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
 128                                 PAD_CTL_SPEED_MED),
 129         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 130                                 PAD_CTL_DSE_48ohm | PAD_CTL_SPEED_MED),
 131         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
 132                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
 133                                 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST),
 134         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
 135         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
 136         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
 137         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
 138         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
 139         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
 140         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
 141 };
 142
 143 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
 144         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
 145                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
 146                                 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST),
 147         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
 148         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
 149         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
 150         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
 151         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
 152         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
 153         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 154 };
 155
 156 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
 157         /* internal I2C */
 158         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 159                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 160         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 161                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 162 };
 163
 164 static const iomux_v3_cfg_t const tx6ul_i2c_gpio_pads[] = {
 165         /* internal I2C set up for I2C bus recovery */
 166         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 167                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 168         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 169                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 170 };
 171
 172 static const struct gpio const tx6ul_gpios[] = {
 173 #ifdef CONFIG_SYS_I2C_SOFT
 174         /* These two entries are used to forcefully reinitialize the I2C bus */
 175         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 176         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 177 #endif
 178         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 179         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 180         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 181 };
 182
 183 static const struct gpio const tx6ul_fec2_gpios[] = {
 184         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
 185         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
 186 };
 187
 188 #define GPIO_DR 0
 189 #define GPIO_DIR 4
 190 #define GPIO_PSR 8
 191
 192 /* run with default environment */
 193 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
 194 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
 195 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
 196 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 197 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 198
 199 static void * const gpio_ports[] = {
 200         (void *)GPIO1_BASE_ADDR,
 201         (void *)GPIO2_BASE_ADDR,
 202         (void *)GPIO3_BASE_ADDR,
 203         (void *)GPIO4_BASE_ADDR,
 204         (void *)GPIO5_BASE_ADDR,
 205 };
 206
 207 static void tx6ul_i2c_recover(void)
 208 {
 209         int i;
 210         int bad = 0;
 211         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
 212         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 213
 214         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
 215                 (readl(&sda_regs->gpio_psr) & SDA_BIT))
 216                 return;
 217
 218         debug("Clearing I2C bus\n");
 219         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 220                 printf("I2C SCL stuck LOW\n");
 221                 bad++;
 222
 223                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 224                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 225
 226                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
 227                                 MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
 228         }
 229         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 230                 printf("I2C SDA stuck LOW\n");
 231                 bad++;
 232
 233                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
 234                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 235                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 236
 237                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_gpio_pads,
 238                                                 ARRAY_SIZE(tx6ul_i2c_gpio_pads));
 239
 240                 udelay(5);
 241
 242                 for (i = 0; i < 18; i++) {
 243                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 244
 245                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 246                         writel(reg, &scl_regs->gpio_dr);
 247                         udelay(5);
 248                         if (reg & SCL_BIT) {
 249                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
 250                                         break;
 251                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
 252                                         break;
 253                                 break;
 254                         }
 255                 }
 256         }
 257         if (bad) {
 258                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
 259                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 260
 261                 if (scl && sda) {
 262                         printf("I2C bus recovery succeeded\n");
 263                 } else {
 264                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
 265                                 scl, sda);
 266                 }
 267                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
 268                                                 ARRAY_SIZE(tx6ul_i2c_pads));
 269         }
 270 }
 271 #else
 272 static inline void tx6ul_i2c_recover(void)
 273 {
 274 }
 275 #endif
 276
 277 /* placed in section '.data' to prevent overwriting relocation info
 278  * overlayed with bss
 279  */
 280 static u32 wrsr __data;
 281
 282 #define WRSR_POR                        (1 << 4)
 283 #define WRSR_TOUT                       (1 << 1)
 284 #define WRSR_SFTW                       (1 << 0)
 285
 286 static void print_reset_cause(void)
 287 {
 288         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 289         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 290         u32 srsr;
 291         char *dlm = "";
 292
 293         printf("Reset cause: ");
 294
 295         srsr = readl(&src_regs->srsr);
 296         wrsr = readw(wdt_base + 4);
 297
 298         if (wrsr & WRSR_POR) {
 299                 printf("%sPOR", dlm);
 300                 dlm = " | ";
 301         }
 302         if (srsr & 0x00004) {
 303                 printf("%sCSU", dlm);
 304                 dlm = " | ";
 305         }
 306         if (srsr & 0x00008) {
 307                 printf("%sIPP USER", dlm);
 308                 dlm = " | ";
 309         }
 310         if (srsr & 0x00010) {
 311                 if (wrsr & WRSR_SFTW) {
 312                         printf("%sSOFT", dlm);
 313                         dlm = " | ";
 314                 }
 315                 if (wrsr & WRSR_TOUT) {
 316                         printf("%sWDOG", dlm);
 317                         dlm = " | ";
 318                 }
 319         }
 320         if (srsr & 0x00020) {
 321                 printf("%sJTAG HIGH-Z", dlm);
 322                 dlm = " | ";
 323         }
 324         if (srsr & 0x00040) {
 325                 printf("%sJTAG SW", dlm);
 326                 dlm = " | ";
 327         }
 328         if (srsr & 0x10000) {
 329                 printf("%sWARM BOOT", dlm);
 330                 dlm = " | ";
 331         }
 332         if (dlm[0] == '\0')
 333                 printf("unknown");
 334
 335         printf("\n");
 336 }
 337
 338 #ifdef CONFIG_IMX6_THERMAL
 339 #include <thermal.h>
 340 #include <imx_thermal.h>
 341 #include <fuse.h>
 342
 343 static void print_temperature(void)
 344 {
 345         struct udevice *thermal_dev;
 346         int cpu_tmp, minc, maxc, ret;
 347         char const *grade_str;
 348         static u32 __data thermal_calib;
 349
 350         puts("Temperature: ");
 351         switch (get_cpu_temp_grade(&minc, &maxc)) {
 352         case TEMP_AUTOMOTIVE:
 353                 grade_str = "Automotive";
 354                 break;
 355         case TEMP_INDUSTRIAL:
 356                 grade_str = "Industrial";
 357                 break;
 358         case TEMP_EXTCOMMERCIAL:
 359                 grade_str = "Extended Commercial";
 360                 break;
 361         default:
 362                 grade_str = "Commercial";
 363         }
 364         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 365         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 366         if (ret == 0) {
 367                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 368
 369                 if (ret == 0)
 370                         printf(" at %dC", cpu_tmp);
 371                 else
 372                         puts(" - failed to read sensor data");
 373         } else {
 374                 puts(" - no sensor device found");
 375         }
 376
 377         if (fuse_read(1, 6, &thermal_calib) == 0) {
 378                 printf(" - calibration data 0x%08x\n", thermal_calib);
 379         } else {
 380                 puts(" - Failed to read thermal calib fuse\n");
 381         }
 382 }
 383 #else
 384 static inline void print_temperature(void)
 385 {
 386 }
 387 #endif
 388
 389 int checkboard(void)
 390 {
 391         u32 cpurev = get_cpu_rev();
 392         char *cpu_str = "?";
 393
 394         if (is_cpu_type(MXC_CPU_MX6SL))
 395                 cpu_str = "SL";
 396         else if (is_cpu_type(MXC_CPU_MX6DL))
 397                 cpu_str = "DL";
 398         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 399                 cpu_str = "SOLO";
 400         else if (is_cpu_type(MXC_CPU_MX6Q))
 401                 cpu_str = "Q";
 402         else if (is_cpu_type(MXC_CPU_MX6UL))
 403                 cpu_str = "UL";
 404
 405         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 406                 cpu_str,
 407                 (cpurev & 0x000F0) >> 4,
 408                 (cpurev & 0x0000F) >> 0,
 409                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 410
 411         print_temperature();
 412         print_reset_cause();
 413 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 414         check_cpu_temperature(1);
 415 #endif
 416         tx6ul_i2c_recover();
 417         return 0;
 418 }
 419
 420 /* serial port not initialized at this point */
 421 int board_early_init_f(void)
 422 {
 423         return 0;
 424 }
 425
 426 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 427 static bool tx6ul_temp_check_enabled = true;
 428 #else
 429 #define tx6ul_temp_check_enabled        0
 430 #endif
 431
 432 static inline u8 tx6ul_mem_suffix(void)
 433 {
 434 #ifdef CONFIG_TX6_NAND
 435         return '0';
 436 #else
 437         return '1';
 438 #endif
 439 }
 440
 441 #ifdef CONFIG_RN5T567
 442 /* PMIC settings */
 443 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 444 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 445 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 446 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 447 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 448 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 */
 449 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
 450 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
 451 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 452 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 */
 453 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
 454 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 */
 455 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
 456 #define VDD_CSI_VAL             rn5t_mV_to_regval2(1800)        /* LDO4 */
 457 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(1800)
 458
 459 static struct pmic_regs rn5t567_regs[] = {
 460         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 461         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 462         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 463         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
 464         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 465         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 466         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
 467         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 468         { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
 469         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 470         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
 471         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 472         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 473         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 474         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
 475         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
 476         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 477         { RN5T567_LDOEN1, 0x0f, ~0x1f, },
 478         { RN5T567_LDOEN2, 0x10, ~0x30, },
 479         { RN5T567_LDODIS, 0x10, ~0x1f, },
 480         { RN5T567_INTPOL, 0, },
 481         { RN5T567_INTEN, 0x3, },
 482         { RN5T567_IREN, 0xf, },
 483         { RN5T567_EN_GPIR, 0, },
 484 };
 485
 486 static int pmic_addr = 0x33;
 487 #endif
 488
 489 int board_init(void)
 490 {
 491         int ret;
 492         u32 cpurev = get_cpu_rev();
 493
 494         debug("%s@%d: \n", __func__, __LINE__);
 495
 496         printf("Board: Ka-Ro TXUL-%c01%c\n",
 497                 ((cpurev &0xff) > 0x10) ? '5' : '0',
 498                 tx6ul_mem_suffix());
 499
 500         get_hab_status();
 501
 502         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 503         if (ret < 0)
 504                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 505
 506         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 507
 508         /* Address of boot parameters */
 509         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 510         gd->bd->bi_arch_number = -1;
 511
 512         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 513                 if (wrsr & WRSR_TOUT)
 514                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 515                 else
 516                         printf("<CTRL-C> detected; safeboot enabled\n");
 517 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 518                 tx6ul_temp_check_enabled = false;
 519 #endif
 520                 return 0;
 521         }
 522
 523         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 524         if (ret) {
 525                 printf("Failed to setup PMIC voltages: %d\n", ret);
 526                 hang();
 527         }
 528         return 0;
 529 }
 530
 531 int dram_init(void)
 532 {
 533         debug("%s@%d: \n", __func__, __LINE__);
 534
 535         /* dram_init must store complete ramsize in gd->ram_size */
 536         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 537                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 538         return 0;
 539 }
 540
 541 void dram_init_banksize(void)
 542 {
 543         debug("%s@%d: \n", __func__, __LINE__);
 544
 545         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 546         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 547                         PHYS_SDRAM_1_SIZE);
 548 #if CONFIG_NR_DRAM_BANKS > 1
 549         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 550         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 551                         PHYS_SDRAM_2_SIZE);
 552 #endif
 553 }
 554
 555 #ifdef  CONFIG_FSL_ESDHC
 556 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 557                                         PAD_CTL_SPEED_MED |             \
 558                                         PAD_CTL_DSE_40ohm |             \
 559                                         PAD_CTL_SRE_FAST)
 560
 561 static const iomux_v3_cfg_t mmc0_pads[] = {
 562         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
 563         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
 564         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
 565         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
 566         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
 567         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
 568         /* SD1 CD */
 569         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 570 };
 571
 572 #ifdef CONFIG_TX6_EMMC
 573 static const iomux_v3_cfg_t mmc1_pads[] = {
 574         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
 575         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
 576         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
 577         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
 578         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
 579         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
 580         /* eMMC RESET */
 581         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 582                                                 PAD_CTL_DSE_40ohm),
 583 };
 584 #endif
 585
 586 static struct tx6ul_esdhc_cfg {
 587         const iomux_v3_cfg_t *pads;
 588         int num_pads;
 589         enum mxc_clock clkid;
 590         struct fsl_esdhc_cfg cfg;
 591         int cd_gpio;
 592 } tx6ul_esdhc_cfg[] = {
 593 #ifdef CONFIG_TX6_EMMC
 594         {
 595                 .pads = mmc1_pads,
 596                 .num_pads = ARRAY_SIZE(mmc1_pads),
 597                 .clkid = MXC_ESDHC2_CLK,
 598                 .cfg = {
 599                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 600                         .max_bus_width = 4,
 601                 },
 602                 .cd_gpio = -EINVAL,
 603         },
 604 #endif
 605         {
 606                 .pads = mmc0_pads,
 607                 .num_pads = ARRAY_SIZE(mmc0_pads),
 608                 .clkid = MXC_ESDHC_CLK,
 609                 .cfg = {
 610                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 611                         .max_bus_width = 4,
 612                 },
 613                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 614         },
 615 };
 616
 617 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 618 {
 619         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 620 }
 621
 622 int board_mmc_getcd(struct mmc *mmc)
 623 {
 624         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 625
 626         if (cfg->cd_gpio < 0)
 627                 return 1;
 628
 629         debug("SD card %d is %spresent (GPIO %d)\n",
 630                 cfg - tx6ul_esdhc_cfg,
 631                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 632                 cfg->cd_gpio);
 633         return !gpio_get_value(cfg->cd_gpio);
 634 }
 635
 636 int board_mmc_init(bd_t *bis)
 637 {
 638         int i;
 639
 640         debug("%s@%d: \n", __func__, __LINE__);
 641
 642 #ifndef CONFIG_ENV_IS_IN_MMC
 643         if (!(gd->flags & GD_FLG_ENV_READY)) {
 644                 printf("deferred ...");
 645                 return 0;
 646         }
 647 #endif
 648         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 649                 struct mmc *mmc;
 650                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 651                 int ret;
 652
 653                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 654                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 655
 656                 if (cfg->cd_gpio >= 0) {
 657                         ret = gpio_request_one(cfg->cd_gpio,
 658                                         GPIOFLAG_INPUT, "MMC CD");
 659                         if (ret) {
 660                                 printf("Error %d requesting GPIO%d_%d\n",
 661                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 662                                 continue;
 663                         }
 664                 }
 665
 666                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 667                 fsl_esdhc_initialize(bis, &cfg->cfg);
 668
 669                 mmc = find_mmc_device(i);
 670                 if (mmc == NULL)
 671                         continue;
 672                 if (board_mmc_getcd(mmc))
 673                         mmc_init(mmc);
 674         }
 675         return 0;
 676 }
 677 #endif /* CONFIG_FSL_ESDHC */
 678
 679 enum {
 680         LED_STATE_INIT = -1,
 681         LED_STATE_OFF,
 682         LED_STATE_ON,
 683         LED_STATE_ERR,
 684 };
 685
 686 static inline int calc_blink_rate(void)
 687 {
 688         if (!tx6ul_temp_check_enabled)
 689                 return CONFIG_SYS_HZ;
 690
 691         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 692                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 693                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 694 }
 695
 696 void show_activity(int arg)
 697 {
 698         static int led_state = LED_STATE_INIT;
 699         static int blink_rate;
 700         static ulong last;
 701         int ret;
 702
 703         switch (led_state) {
 704         case LED_STATE_ERR:
 705                 return;
 706
 707         case LED_STATE_INIT:
 708                 last = get_timer(0);
 709                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 710                 if (ret)
 711                         led_state = LED_STATE_ERR;
 712                 else
 713                         led_state = LED_STATE_ON;
 714                 blink_rate = calc_blink_rate();
 715                 break;
 716
 717         case LED_STATE_ON:
 718         case LED_STATE_OFF:
 719                 if (get_timer(last) > blink_rate) {
 720                         blink_rate = calc_blink_rate();
 721                         last = get_timer_masked();
 722                         if (led_state == LED_STATE_ON) {
 723                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 724                         } else {
 725                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 726                         }
 727                         led_state = 1 - led_state;
 728                 }
 729                 break;
 730         }
 731 }
 732
 733 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
 734         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
 735         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
 736         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
 737         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
 738         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
 739         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
 740 };
 741
 742 static const iomux_v3_cfg_t stk5_pads[] = {
 743         /* SW controlled LED on STK5 baseboard */
 744         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 745
 746         /* I2C bus on DIMM pins 40/41 */
 747         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 748         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 749
 750         /* TSC200x PEN IRQ */
 751         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
 752
 753         /* EDT-FT5x06 Polytouch panel */
 754         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
 755         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
 756         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 757
 758         /* USBH1 */
 759         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 760         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 761
 762         /* USBOTG */
 763         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 764         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 765 };
 766
 767 static const struct gpio stk5_gpios[] = {
 768         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 769
 770         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
 771         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 772 };
 773
 774 #ifdef CONFIG_LCD
 775 vidinfo_t panel_info = {
 776         /* set to max. size supported by SoC */
 777         .vl_col = 4096,
 778         .vl_row = 1024,
 779
 780         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 781 };
 782
 783 static struct fb_videomode tx6ul_fb_modes[] = {
 784 #ifndef CONFIG_SYS_LVDS_IF
 785         {
 786                 /* Standard VGA timing */
 787                 .name           = "VGA",
 788                 .refresh        = 60,
 789                 .xres           = 640,
 790                 .yres           = 480,
 791                 .pixclock       = KHZ2PICOS(25175),
 792                 .left_margin    = 48,
 793                 .hsync_len      = 96,
 794                 .right_margin   = 16,
 795                 .upper_margin   = 31,
 796                 .vsync_len      = 2,
 797                 .lower_margin   = 12,
 798                 .sync           = FB_SYNC_CLK_LAT_FALL,
 799         },
 800         {
 801                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 802                  * DE high active, 115.2 mm x 86.4 mm display area
 803                  * VGA compatible timing
 804                  */
 805                 .name           = "ETV570",
 806                 .refresh        = 60,
 807                 .xres           = 640,
 808                 .yres           = 480,
 809                 .pixclock       = KHZ2PICOS(25175),
 810                 .left_margin    = 114,
 811                 .hsync_len      = 30,
 812                 .right_margin   = 16,
 813                 .upper_margin   = 32,
 814                 .vsync_len      = 3,
 815                 .lower_margin   = 10,
 816                 .sync           = FB_SYNC_CLK_LAT_FALL,
 817         },
 818         {
 819                 /* Emerging ET0350G0DH6 320 x 240 display.
 820                  * 70.08 mm x 52.56 mm display area.
 821                  */
 822                 .name           = "ET0350",
 823                 .refresh        = 60,
 824                 .xres           = 320,
 825                 .yres           = 240,
 826                 .pixclock       = KHZ2PICOS(6500),
 827                 .left_margin    = 68 - 34,
 828                 .hsync_len      = 34,
 829                 .right_margin   = 20,
 830                 .upper_margin   = 18 - 3,
 831                 .vsync_len      = 3,
 832                 .lower_margin   = 4,
 833                 .sync           = FB_SYNC_CLK_LAT_FALL,
 834         },
 835         {
 836                 /* Emerging ET0430G0DH6 480 x 272 display.
 837                  * 95.04 mm x 53.856 mm display area.
 838                  */
 839                 .name           = "ET0430",
 840                 .refresh        = 60,
 841                 .xres           = 480,
 842                 .yres           = 272,
 843                 .pixclock       = KHZ2PICOS(9000),
 844                 .left_margin    = 2,
 845                 .hsync_len      = 41,
 846                 .right_margin   = 2,
 847                 .upper_margin   = 2,
 848                 .vsync_len      = 10,
 849                 .lower_margin   = 2,
 850         },
 851         {
 852                 /* Emerging ET0500G0DH6 800 x 480 display.
 853                  * 109.6 mm x 66.4 mm display area.
 854                  */
 855                 .name           = "ET0500",
 856                 .refresh        = 60,
 857                 .xres           = 800,
 858                 .yres           = 480,
 859                 .pixclock       = KHZ2PICOS(33260),
 860                 .left_margin    = 216 - 128,
 861                 .hsync_len      = 128,
 862                 .right_margin   = 1056 - 800 - 216,
 863                 .upper_margin   = 35 - 2,
 864                 .vsync_len      = 2,
 865                 .lower_margin   = 525 - 480 - 35,
 866                 .sync           = FB_SYNC_CLK_LAT_FALL,
 867         },
 868         {
 869                 /* Emerging ETQ570G0DH6 320 x 240 display.
 870                  * 115.2 mm x 86.4 mm display area.
 871                  */
 872                 .name           = "ETQ570",
 873                 .refresh        = 60,
 874                 .xres           = 320,
 875                 .yres           = 240,
 876                 .pixclock       = KHZ2PICOS(6400),
 877                 .left_margin    = 38,
 878                 .hsync_len      = 30,
 879                 .right_margin   = 30,
 880                 .upper_margin   = 16, /* 15 according to datasheet */
 881                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 882                 .lower_margin   = 4, /* 4.5 according to datasheet */
 883                 .sync           = FB_SYNC_CLK_LAT_FALL,
 884         },
 885         {
 886                 /* Emerging ET0700G0DH6 800 x 480 display.
 887                  * 152.4 mm x 91.44 mm display area.
 888                  */
 889                 .name           = "ET0700",
 890                 .refresh        = 60,
 891                 .xres           = 800,
 892                 .yres           = 480,
 893                 .pixclock       = KHZ2PICOS(33260),
 894                 .left_margin    = 216 - 128,
 895                 .hsync_len      = 128,
 896                 .right_margin   = 1056 - 800 - 216,
 897                 .upper_margin   = 35 - 2,
 898                 .vsync_len      = 2,
 899                 .lower_margin   = 525 - 480 - 35,
 900                 .sync           = FB_SYNC_CLK_LAT_FALL,
 901         },
 902         {
 903                 /* Emerging ET070001DM6 800 x 480 display.
 904                  * 152.4 mm x 91.44 mm display area.
 905                  */
 906                 .name           = "ET070001DM6",
 907                 .refresh        = 60,
 908                 .xres           = 800,
 909                 .yres           = 480,
 910                 .pixclock       = KHZ2PICOS(33260),
 911                 .left_margin    = 216 - 128,
 912                 .hsync_len      = 128,
 913                 .right_margin   = 1056 - 800 - 216,
 914                 .upper_margin   = 35 - 2,
 915                 .vsync_len      = 2,
 916                 .lower_margin   = 525 - 480 - 35,
 917                 .sync           = 0,
 918         },
 919 #else
 920         {
 921                 /* HannStar HSD100PXN1
 922                  * 202.7m mm x 152.06 mm display area.
 923                  */
 924                 .name           = "HSD100PXN1",
 925                 .refresh        = 60,
 926                 .xres           = 1024,
 927                 .yres           = 768,
 928                 .pixclock       = KHZ2PICOS(65000),
 929                 .left_margin    = 0,
 930                 .hsync_len      = 0,
 931                 .right_margin   = 320,
 932                 .upper_margin   = 0,
 933                 .vsync_len      = 0,
 934                 .lower_margin   = 38,
 935                 .sync           = FB_SYNC_CLK_LAT_FALL,
 936         },
 937 #endif
 938         {
 939                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 940                 .refresh        = 60,
 941                 .left_margin    = 48,
 942                 .hsync_len      = 96,
 943                 .right_margin   = 16,
 944                 .upper_margin   = 31,
 945                 .vsync_len      = 2,
 946                 .lower_margin   = 12,
 947                 .sync           = FB_SYNC_CLK_LAT_FALL,
 948         },
 949 };
 950
 951 static int lcd_enabled = 1;
 952 static int lcd_bl_polarity;
 953
 954 static int lcd_backlight_polarity(void)
 955 {
 956         return lcd_bl_polarity;
 957 }
 958
 959 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 960 #ifdef CONFIG_LCD
 961         /* LCD RESET */
 962         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 963         /* LCD POWER_ENABLE */
 964         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
 965         /* LCD Backlight (PWM) */
 966         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
 967         /* Display */
 968         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 969         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
 970         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
 971         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
 972         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
 973         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
 974         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
 975         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
 976         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
 977         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
 978         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
 979         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
 980         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
 981         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
 982         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
 983         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
 984         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
 985         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
 986         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
 987         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
 988         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
 989         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
 990         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
 991         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
 992         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
 993         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
 994         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
 995         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
 996 #endif
 997 };
 998
 999 static const struct gpio stk5_lcd_gpios[] = {
1000         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1001         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1002         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1003 };
1004
1005 /* run with valid env from NAND/eMMC */
1006 void lcd_enable(void)
1007 {
1008         /* HACK ALERT:
1009          * global variable from common/lcd.c
1010          * Set to 0 here to prevent messages from going to LCD
1011          * rather than serial console
1012          */
1013         lcd_is_enabled = 0;
1014
1015         if (lcd_enabled) {
1016                 karo_load_splashimage(1);
1017
1018                 debug("Switching LCD on\n");
1019                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1020                 udelay(100);
1021                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1022                 udelay(300000);
1023                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1024                         lcd_backlight_polarity());
1025         }
1026 }
1027
1028 static void lcd_disable(void)
1029 {
1030         if (lcd_enabled) {
1031                 printf("Disabling LCD\n");
1032                 panel_info.vl_row = 0;
1033                 lcd_enabled = 0;
1034         }
1035 }
1036
1037 void lcd_ctrl_init(void *lcdbase)
1038 {
1039         int color_depth = 24;
1040         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1041         const char *vm;
1042         unsigned long val;
1043         int refresh = 60;
1044         struct fb_videomode *p = &tx6ul_fb_modes[0];
1045         struct fb_videomode fb_mode;
1046         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1047
1048         if (!lcd_enabled) {
1049                 debug("LCD disabled\n");
1050                 return;
1051         }
1052
1053         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1054                 lcd_disable();
1055                 setenv("splashimage", NULL);
1056                 return;
1057         }
1058
1059         karo_fdt_move_fdt();
1060         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1061
1062         if (video_mode == NULL) {
1063                 lcd_disable();
1064                 return;
1065         }
1066         vm = video_mode;
1067         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1068                 p = &fb_mode;
1069                 debug("Using video mode from FDT\n");
1070                 vm += strlen(vm);
1071                 if (fb_mode.xres > panel_info.vl_col ||
1072                         fb_mode.yres > panel_info.vl_row) {
1073                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1074                                 fb_mode.xres, fb_mode.yres,
1075                                 panel_info.vl_col, panel_info.vl_row);
1076                         lcd_enabled = 0;
1077                         return;
1078                 }
1079         }
1080         if (p->name != NULL)
1081                 debug("Trying compiled-in video modes\n");
1082         while (p->name != NULL) {
1083                 if (strcmp(p->name, vm) == 0) {
1084                         debug("Using video mode: '%s'\n", p->name);
1085                         vm += strlen(vm);
1086                         break;
1087                 }
1088                 p++;
1089         }
1090         if (*vm != '\0')
1091                 debug("Trying to decode video_mode: '%s'\n", vm);
1092         while (*vm != '\0') {
1093                 if (*vm >= '0' && *vm <= '9') {
1094                         char *end;
1095
1096                         val = simple_strtoul(vm, &end, 0);
1097                         if (end > vm) {
1098                                 if (!xres_set) {
1099                                         if (val > panel_info.vl_col)
1100                                                 val = panel_info.vl_col;
1101                                         p->xres = val;
1102                                         panel_info.vl_col = val;
1103                                         xres_set = 1;
1104                                 } else if (!yres_set) {
1105                                         if (val > panel_info.vl_row)
1106                                                 val = panel_info.vl_row;
1107                                         p->yres = val;
1108                                         panel_info.vl_row = val;
1109                                         yres_set = 1;
1110                                 } else if (!bpp_set) {
1111                                         switch (val) {
1112                                         case 8:
1113                                         case 16:
1114                                         case 18:
1115                                         case 24:
1116                                         case 32:
1117                                                 color_depth = val;
1118                                                 break;
1119
1120                                         default:
1121                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1122                                                         end - vm, vm, color_depth);
1123                                         }
1124                                         bpp_set = 1;
1125                                 } else if (!refresh_set) {
1126                                         refresh = val;
1127                                         refresh_set = 1;
1128                                 }
1129                         }
1130                         vm = end;
1131                 }
1132                 switch (*vm) {
1133                 case '@':
1134                         bpp_set = 1;
1135                         /* fallthru */
1136                 case '-':
1137                         yres_set = 1;
1138                         /* fallthru */
1139                 case 'x':
1140                         xres_set = 1;
1141                         /* fallthru */
1142                 case 'M':
1143                 case 'R':
1144                         vm++;
1145                         break;
1146
1147                 default:
1148                         if (*vm != '\0')
1149                                 vm++;
1150                 }
1151         }
1152         if (p->xres == 0 || p->yres == 0) {
1153                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1154                 lcd_enabled = 0;
1155                 printf("Supported video modes are:");
1156                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1157                         printf(" %s", p->name);
1158                 }
1159                 printf("\n");
1160                 return;
1161         }
1162         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1163                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1164                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1165                 lcd_enabled = 0;
1166                 return;
1167         }
1168         panel_info.vl_col = p->xres;
1169         panel_info.vl_row = p->yres;
1170
1171         switch (color_depth) {
1172         case 8:
1173                 panel_info.vl_bpix = LCD_COLOR8;
1174                 break;
1175         case 16:
1176                 panel_info.vl_bpix = LCD_COLOR16;
1177                 break;
1178         default:
1179                 panel_info.vl_bpix = LCD_COLOR32;
1180         }
1181
1182         p->pixclock = KHZ2PICOS(refresh *
1183                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1184                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1185                                 1000);
1186         debug("Pixel clock set to %lu.%03lu MHz\n",
1187                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1188
1189         if (p != &fb_mode) {
1190                 int ret;
1191
1192                 debug("Creating new display-timing node from '%s'\n",
1193                         video_mode);
1194                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1195                 if (ret)
1196                         printf("Failed to create new display-timing node from '%s': %d\n",
1197                                 video_mode, ret);
1198         }
1199
1200         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1201         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1202                                         ARRAY_SIZE(stk5_lcd_pads));
1203
1204         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1205                 color_depth, refresh);
1206
1207         if (karo_load_splashimage(0) == 0) {
1208                 char vmode[128];
1209
1210                 /* setup env variable for mxsfb display driver */
1211                 snprintf(vmode, sizeof(vmode),
1212                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1213                         p->xres, p->yres, p->left_margin, p->right_margin,
1214                         p->upper_margin, p->lower_margin, p->hsync_len,
1215                         p->vsync_len, p->sync, p->pixclock, color_depth);
1216                 setenv("videomode", vmode);
1217
1218                 debug("Initializing LCD controller\n");
1219                 lcdif_clk_enable();
1220                 video_hw_init();
1221                 setenv("videomode", NULL);
1222         } else {
1223                 debug("Skipping initialization of LCD controller\n");
1224         }
1225 }
1226 #else
1227 #define lcd_enabled 0
1228 #endif /* CONFIG_LCD */
1229
1230 #ifndef CONFIG_ENV_IS_IN_MMC
1231 static void tx6ul_mmc_init(void)
1232 {
1233         puts("MMC:   ");
1234         if (board_mmc_init(gd->bd) < 0)
1235                 cpu_mmc_init(gd->bd);
1236         print_mmc_devices(',');
1237 }
1238 #else
1239 static inline void tx6ul_mmc_init(void)
1240 {
1241 }
1242 #endif
1243
1244 static void stk5_board_init(void)
1245 {
1246         int ret;
1247
1248         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1249         if (ret < 0) {
1250                 printf("Failed to request stk5_gpios: %d\n", ret);
1251                 return;
1252         }
1253         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1254         if (getenv_yesno("jtag_enable") != 0) {
1255                 /* true if unset or set to one of: 'yYtT1' */
1256                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1257         }
1258         debug("%s@%d: \n", __func__, __LINE__);
1259 }
1260
1261 static void stk5v3_board_init(void)
1262 {
1263         debug("%s@%d: \n", __func__, __LINE__);
1264         stk5_board_init();
1265         debug("%s@%d: \n", __func__, __LINE__);
1266         tx6ul_mmc_init();
1267 }
1268
1269 static void stk5v5_board_init(void)
1270 {
1271         int ret;
1272
1273         stk5_board_init();
1274         tx6ul_mmc_init();
1275
1276         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1277                         "Flexcan Transceiver");
1278         if (ret) {
1279                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1280                 return;
1281         }
1282
1283         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1284                         TX6UL_GPIO_OUT_PAD_CTRL);
1285 }
1286
1287 static void tx6ul_set_cpu_clock(void)
1288 {
1289         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1290
1291         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1292                 return;
1293
1294         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1295                 printf("%s detected; skipping cpu clock change\n",
1296                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1297                 return;
1298         }
1299         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1300                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1301                 printf("CPU clock set to %lu.%03lu MHz\n",
1302                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1303         } else {
1304                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1305         }
1306 }
1307
1308 int board_late_init(void)
1309 {
1310         const char *baseboard;
1311
1312         debug("%s@%d: \n", __func__, __LINE__);
1313
1314         env_cleanup();
1315
1316         if (tx6ul_temp_check_enabled)
1317                 check_cpu_temperature(1);
1318
1319         tx6ul_set_cpu_clock();
1320
1321         if (had_ctrlc())
1322                 setenv_ulong("safeboot", 1);
1323         else if (wrsr & WRSR_TOUT)
1324                 setenv_ulong("wdreset", 1);
1325         else
1326                 karo_fdt_move_fdt();
1327
1328         baseboard = getenv("baseboard");
1329         if (!baseboard)
1330                 goto exit;
1331
1332         printf("Baseboard: %s\n", baseboard);
1333
1334         if (strncmp(baseboard, "stk5", 4) == 0) {
1335                 if ((strlen(baseboard) == 4) ||
1336                         strcmp(baseboard, "stk5-v3") == 0) {
1337                         stk5v3_board_init();
1338                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1339                         const char *otg_mode = getenv("otg_mode");
1340
1341                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1342                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1343                                         otg_mode, baseboard);
1344                                 setenv("otg_mode", "none");
1345                         }
1346                         stk5v5_board_init();
1347                 } else {
1348                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1349                                 baseboard + 4);
1350                 }
1351         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1352                         const char *otg_mode = getenv("otg_mode");
1353
1354                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1355                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1356                                         otg_mode, baseboard);
1357                                 setenv("otg_mode", "none");
1358                         }
1359                         stk5_board_init();
1360         } else {
1361                 printf("WARNING: Unsupported baseboard: '%s'\n",
1362                         baseboard);
1363                 if (!had_ctrlc())
1364                         return -EINVAL;
1365         }
1366
1367 exit:
1368         debug("%s@%d: \n", __func__, __LINE__);
1369
1370         clear_ctrlc();
1371         return 0;
1372 }
1373
1374 #ifdef CONFIG_FEC_MXC
1375
1376 #ifndef ETH_ALEN
1377 #define ETH_ALEN 6
1378 #endif
1379
1380 static void tx6ul_init_mac(void)
1381 {
1382         u8 mac[ETH_ALEN];
1383         const char *baseboard = getenv("baseboard");
1384
1385         imx_get_mac_from_fuse(0, mac);
1386         if (!is_valid_ethaddr(mac)) {
1387                 printf("No valid MAC address programmed\n");
1388                 return;
1389         }
1390         printf("MAC addr from fuse: %pM\n", mac);
1391         if (!getenv("ethaddr"))
1392                 eth_setenv_enetaddr("ethaddr", mac);
1393
1394         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1395                 setenv("eth1addr", NULL);
1396                 return;
1397         }
1398         if (getenv("eth1addr"))
1399                 return;
1400         imx_get_mac_from_fuse(1, mac);
1401         eth_setenv_enetaddr("eth1addr", mac);
1402 }
1403
1404 int board_eth_init(bd_t *bis)
1405 {
1406         int ret;
1407
1408         tx6ul_init_mac();
1409
1410         /* delay at least 21ms for the PHY internal POR signal to deassert */
1411         udelay(22000);
1412
1413         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1414                                         ARRAY_SIZE(tx6ul_enet1_pads));
1415
1416         /* Deassert RESET to the external phys */
1417         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1418
1419         if (getenv("ethaddr")) {
1420                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1421                 if (ret) {
1422                         printf("failed to initialize FEC0: %d\n", ret);
1423                         return ret;
1424                 }
1425         }
1426         if (getenv("eth1addr")) {
1427                 ret = gpio_request_array(tx6ul_fec2_gpios,
1428                                         ARRAY_SIZE(tx6ul_fec2_gpios));
1429                 if (ret < 0) {
1430                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1431                 }
1432                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1433                                                 ARRAY_SIZE(tx6ul_enet2_pads));
1434
1435                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1436
1437                 /* Minimum PHY reset duration */
1438                 udelay(100);
1439                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1440                 /* Wait for PHY internal POR to finish */
1441                 udelay(22000);
1442
1443                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1444                 if (ret) {
1445                         printf("failed to initialize FEC1: %d\n", ret);
1446                         return ret;
1447                 }
1448         }
1449         return 0;
1450 }
1451 #endif /* CONFIG_FEC_MXC */
1452
1453 #ifdef CONFIG_SERIAL_TAG
1454 void get_board_serial(struct tag_serialnr *serialnr)
1455 {
1456         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1457         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1458
1459         serialnr->low = readl(&fuse->cfg0);
1460         serialnr->high = readl(&fuse->cfg1);
1461 }
1462 #endif
1463
1464 #if defined(CONFIG_OF_BOARD_SETUP)
1465 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1466 #include <jffs2/jffs2.h>
1467 #include <mtd_node.h>
1468 static struct node_info nodes[] = {
1469         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1470 };
1471 #else
1472 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1473 #endif
1474
1475 static const char *tx6ul_touchpanels[] = {
1476         "ti,tsc2007",
1477         "edt,edt-ft5x06",
1478         "eeti,egalax_ts",
1479 };
1480
1481 int ft_board_setup(void *blob, bd_t *bd)
1482 {
1483         const char *baseboard = getenv("baseboard");
1484         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1485         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1486         int ret;
1487
1488         ret = fdt_increase_size(blob, 4096);
1489         if (ret) {
1490                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1491                 return ret;
1492         }
1493         if (stk5_v5)
1494                 karo_fdt_enable_node(blob, "stk5led", 0);
1495
1496         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1497
1498         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1499                                 ARRAY_SIZE(tx6ul_touchpanels));
1500         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1501         karo_fdt_fixup_flexcan(blob, stk5_v5);
1502
1503         karo_fdt_update_fb_mode(blob, video_mode);
1504
1505         return 0;
1506 }
1507 #endif /* CONFIG_OF_BOARD_SETUP */