board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37
  38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
  39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
  40
  41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  42
  43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  46
  47 #ifdef CONFIG_SYS_I2C_SOFT
  48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  50 #endif
  51
  52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  53
  54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  56 #else
  57 #define TEMPERATURE_MIN                 (-40)
  58 #endif
  59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  61 #else
  62 #define TEMPERATURE_HOT                 80
  63 #endif
  64
  65 DECLARE_GLOBAL_DATA_PTR;
  66
  67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  68
  69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  70 #ifdef CONFIG_SECURE_BOOT
  71 char __csf_data[0] __attribute__((section(".__csf_data")));
  72 #endif
  73
  74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
  75                                         PAD_CTL_SPEED_MED |             \
  76                                         PAD_CTL_DSE_40ohm |             \
  77                                         PAD_CTL_SRE_FAST)
  78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
  79                                         PAD_CTL_ODE |                   \
  80                                         PAD_CTL_HYS |                   \
  81                                         PAD_CTL_SPEED_LOW |             \
  82                                         PAD_CTL_DSE_34ohm |             \
  83                                         PAD_CTL_SRE_FAST)
  84 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
  85                                         PAD_CTL_DSE_120ohm |            \
  86                                         PAD_CTL_PUS_100K_UP |           \
  87                                         PAD_CTL_SRE_FAST)
  88 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  89                                         PAD_CTL_DSE_60ohm |             \
  90                                         PAD_CTL_SRE_SLOW)
  91 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
  92                                         PAD_CTL_PUS_47K_UP)
  93
  94
  95 static const iomux_v3_cfg_t tx6ul_pads[] = {
  96         /* UART pads */
  97 #if CONFIG_MXC_UART_BASE == UART1_BASE
  98         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
  99         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 100         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 101         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 102 #endif
 103 #if CONFIG_MXC_UART_BASE == UART2_BASE
 104         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 105         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 106         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 107         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 108 #endif
 109 #if CONFIG_MXC_UART_BASE == UART5_BASE
 110         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
 111         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
 112         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
 113         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
 114 #endif
 115         /* FEC PHY GPIO functions */
 116         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
 117         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
 118         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
 119 };
 120
 121 static const iomux_v3_cfg_t tx6ul_enet1_pads[] = {
 122         /* FEC functions */
 123         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
 124                                                      PAD_CTL_SPEED_LOW),
 125         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 126                                                       PAD_CTL_DSE_120ohm |
 127                                                       PAD_CTL_SPEED_LOW),
 128         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
 129                                                      PAD_CTL_DSE_80ohm |
 130                                                      PAD_CTL_SRE_SLOW),
 131
 132         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
 133         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
 134         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
 135         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
 136         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
 137         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
 138         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
 139 };
 140
 141 static const iomux_v3_cfg_t tx6ul_enet2_pads[] = {
 142         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
 143                                                             PAD_CTL_DSE_80ohm |
 144                                                             PAD_CTL_SRE_SLOW),
 145         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
 146         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
 147         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
 148         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
 149         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
 150         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
 151         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
 152 };
 153
 154 static const iomux_v3_cfg_t tx6ul_i2c_pads[] = {
 155         /* internal I2C */
 156         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
 157                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
 158         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
 159                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
 160 };
 161
 162 static const struct gpio tx6ul_gpios[] = {
 163 #ifdef CONFIG_SYS_I2C_SOFT
 164         /* These two entries are used to forcefully reinitialize the I2C bus */
 165         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 166         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 167 #endif
 168         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 169         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 170         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 171 };
 172
 173 static const struct gpio tx6ul_fec2_gpios[] = {
 174         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
 175         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
 176 };
 177
 178 #define GPIO_DR 0
 179 #define GPIO_DIR 4
 180 #define GPIO_PSR 8
 181
 182 /* run with default environment */
 183 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
 184 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
 185 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
 186 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 187 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 188
 189 static void * const gpio_ports[] = {
 190         (void *)GPIO1_BASE_ADDR,
 191         (void *)GPIO2_BASE_ADDR,
 192         (void *)GPIO3_BASE_ADDR,
 193         (void *)GPIO4_BASE_ADDR,
 194         (void *)GPIO5_BASE_ADDR,
 195 };
 196
 197 static void tx6ul_i2c_recover(void)
 198 {
 199         int i;
 200         int bad = 0;
 201         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
 202         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
 203
 204         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
 205             (readl(&sda_regs->gpio_psr) & SDA_BIT))
 206                 return;
 207
 208         debug("Clearing I2C bus\n");
 209         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
 210                 printf("I2C SCL stuck LOW\n");
 211                 bad++;
 212
 213                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 214                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 215
 216                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
 217                                        MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
 218         }
 219         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
 220                 printf("I2C SDA stuck LOW\n");
 221                 bad++;
 222
 223                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
 224                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
 225                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
 226
 227                 udelay(5);
 228
 229                 for (i = 0; i < 18; i++) {
 230                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
 231
 232                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 233                         writel(reg, &scl_regs->gpio_dr);
 234                         udelay(5);
 235                         if (reg & SCL_BIT) {
 236                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
 237                                         break;
 238                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
 239                                         break;
 240                                 break;
 241                         }
 242                 }
 243         }
 244         if (bad) {
 245                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
 246                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
 247
 248                 if (scl && sda) {
 249                         printf("I2C bus recovery succeeded\n");
 250                 } else {
 251                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
 252                                scl, sda);
 253                 }
 254                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
 255                                                  ARRAY_SIZE(tx6ul_i2c_pads));
 256         }
 257 }
 258 #else
 259 static inline void tx6ul_i2c_recover(void)
 260 {
 261 }
 262 #endif
 263
 264 /* placed in section '.data' to prevent overwriting relocation info
 265  * overlayed with bss
 266  */
 267 static u32 wrsr __data;
 268
 269 #define WRSR_POR                        (1 << 4)
 270 #define WRSR_TOUT                       (1 << 1)
 271 #define WRSR_SFTW                       (1 << 0)
 272
 273 static void print_reset_cause(void)
 274 {
 275         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 276         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 277         u32 srsr;
 278         char *dlm = "";
 279
 280         printf("Reset cause: ");
 281
 282         srsr = readl(&src_regs->srsr);
 283         wrsr = readw(wdt_base + 4);
 284
 285         if (wrsr & WRSR_POR) {
 286                 printf("%sPOR", dlm);
 287                 dlm = " | ";
 288         }
 289         if (srsr & 0x00004) {
 290                 printf("%sCSU", dlm);
 291                 dlm = " | ";
 292         }
 293         if (srsr & 0x00008) {
 294                 printf("%sIPP USER", dlm);
 295                 dlm = " | ";
 296         }
 297         if (srsr & 0x00010) {
 298                 if (wrsr & WRSR_SFTW) {
 299                         printf("%sSOFT", dlm);
 300                         dlm = " | ";
 301                 }
 302                 if (wrsr & WRSR_TOUT) {
 303                         printf("%sWDOG", dlm);
 304                         dlm = " | ";
 305                 }
 306         }
 307         if (srsr & 0x00020) {
 308                 printf("%sJTAG HIGH-Z", dlm);
 309                 dlm = " | ";
 310         }
 311         if (srsr & 0x00040) {
 312                 printf("%sJTAG SW", dlm);
 313                 dlm = " | ";
 314         }
 315         if (srsr & 0x10000) {
 316                 printf("%sWARM BOOT", dlm);
 317                 dlm = " | ";
 318         }
 319         if (dlm[0] == '\0')
 320                 printf("unknown");
 321
 322         printf("\n");
 323 }
 324
 325 #ifdef CONFIG_IMX6_THERMAL
 326 #include <thermal.h>
 327 #include <imx_thermal.h>
 328 #include <fuse.h>
 329
 330 static void print_temperature(void)
 331 {
 332         struct udevice *thermal_dev;
 333         int cpu_tmp, minc, maxc, ret;
 334         char const *grade_str;
 335         static u32 __data thermal_calib;
 336
 337         puts("Temperature: ");
 338         switch (get_cpu_temp_grade(&minc, &maxc)) {
 339         case TEMP_AUTOMOTIVE:
 340                 grade_str = "Automotive";
 341                 break;
 342         case TEMP_INDUSTRIAL:
 343                 grade_str = "Industrial";
 344                 break;
 345         case TEMP_EXTCOMMERCIAL:
 346                 grade_str = "Extended Commercial";
 347                 break;
 348         default:
 349                 grade_str = "Commercial";
 350         }
 351         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 352         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 353         if (ret == 0) {
 354                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 355
 356                 if (ret == 0)
 357                         printf(" at %dC", cpu_tmp);
 358                 else
 359                         puts(" - failed to read sensor data");
 360         } else {
 361                 puts(" - no sensor device found");
 362         }
 363
 364         if (fuse_read(1, 6, &thermal_calib) == 0) {
 365                 printf(" - calibration data 0x%08x\n", thermal_calib);
 366         } else {
 367                 puts(" - Failed to read thermal calib fuse\n");
 368         }
 369 }
 370 #else
 371 static inline void print_temperature(void)
 372 {
 373 }
 374 #endif
 375
 376 int checkboard(void)
 377 {
 378         u32 cpurev = get_cpu_rev();
 379         char *cpu_str = "?";
 380
 381         if (is_cpu_type(MXC_CPU_MX6SL))
 382                 cpu_str = "SL";
 383         else if (is_cpu_type(MXC_CPU_MX6DL))
 384                 cpu_str = "DL";
 385         else if (is_cpu_type(MXC_CPU_MX6SOLO))
 386                 cpu_str = "SOLO";
 387         else if (is_cpu_type(MXC_CPU_MX6Q))
 388                 cpu_str = "Q";
 389         else if (is_cpu_type(MXC_CPU_MX6UL))
 390                 cpu_str = "UL";
 391         else if (is_cpu_type(MXC_CPU_MX6ULL))
 392                 cpu_str = "ULL";
 393
 394         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 395                 cpu_str,
 396                 (cpurev & 0x000F0) >> 4,
 397                 (cpurev & 0x0000F) >> 0,
 398                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 399
 400         print_temperature();
 401         print_reset_cause();
 402 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 403         check_cpu_temperature(1);
 404 #endif
 405         tx6ul_i2c_recover();
 406         return 0;
 407 }
 408
 409 /* serial port not initialized at this point */
 410 int board_early_init_f(void)
 411 {
 412         return 0;
 413 }
 414
 415 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 416 static bool tx6ul_temp_check_enabled = true;
 417 #else
 418 #define tx6ul_temp_check_enabled        0
 419 #endif
 420
 421 #ifndef CONFIG_SYS_NAND_BLOCKS
 422 #define CONFIG_SYS_NAND_BLOCKS 0
 423 #endif
 424
 425 static inline u8 tx6ul_mem_suffix(void)
 426 {
 427         return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
 428                 IS_ENABLED(CONFIG_TX6_EMMC) +
 429                 CONFIG_SYS_NAND_BLOCKS / 2048 * 4;
 430 }
 431
 432 #ifdef CONFIG_RN5T567
 433 /* PMIC settings */
 434 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 435 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 436 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 437 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 SDRAM 1.35V */
 438 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 439 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 eMMC/NAND,VDDIO_EXT 3.0V */
 440 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
 441 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 ENET,GPIO,LCD,SD1,UART,3.3V */
 442 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
 443 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 ADC */
 444 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
 445 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 PMIC */
 446 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
 447 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 CSI */
 448 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
 449 #define VDD_LDO5_VAL            rn5t_mV_to_regval2(1200)        /* LDO5 1.2V */
 450 #define LDOEN1_LDO1EN           (1 << 0)
 451 #define LDOEN1_LDO2EN           (1 << 1)
 452 #define LDOEN1_LDO3EN           (1 << 2)
 453 #define LDOEN1_LDO4EN           (1 << 3)
 454 #define LDOEN1_LDO5EN           (1 << 4)
 455 #define LDOEN1_VAL              (LDOEN1_LDO1EN | LDOEN1_LDO2EN | LDOEN1_LDO3EN | LDOEN1_LDO4EN)
 456 #define LDOEN1_MASK             0x1f
 457 #define LDOEN2_LDORTC1EN        (1 << 4)
 458 #define LDOEN2_LDORTC2EN        (1 << 5)
 459 #define LDOEN2_VAL              LDOEN2_LDORTC1EN
 460 #define LDOEN2_MASK             0x30
 461
 462 static struct pmic_regs rn5t567_regs[] = {
 463         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 464         { RN5T567_SLPCNT, 0, },
 465         { RN5T567_REPCNT, (3 << 4) | (0 << 1), },
 466         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 467         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 468         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
 469         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 470         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 471         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
 472         { RN5T567_DC1CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
 473         { RN5T567_DC2CTL, DCnCTL_DIS, },
 474         { RN5T567_DC3CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
 475         { RN5T567_DC4CTL, DCnCTL_EN | DCnCTL_DIS | DCnMODE_SLP(MODE_PSM), },
 476         { RN5T567_DC1CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
 477         { RN5T567_DC2CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
 478         { RN5T567_DC3CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
 479         { RN5T567_DC4CTL2, DCnCTL2_LIMSDEN | DCnCTL2_LIM_HIGH | DCnCTL2_SR_HIGH | DCnCTL2_OSC_LOW, },
 480         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 481         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 482         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
 483         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
 484         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
 485         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 486         { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
 487         { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
 488         { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
 489         { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
 490         { RN5T567_LDO5DAC, VDD_LDO5_VAL, },
 491         { RN5T567_LDO1DAC_SLP, VDD_IO_INT_VAL_LP, },
 492         { RN5T567_LDO2DAC_SLP, VDD_ADC_VAL_LP, },
 493         { RN5T567_LDO3DAC_SLP, VDD_PMIC_VAL_LP, },
 494         { RN5T567_LDO4DAC_SLP, VDD_CSI_VAL_LP, },
 495         { RN5T567_LDOEN1, LDOEN1_VAL, ~LDOEN1_MASK, },
 496         { RN5T567_LDOEN2, LDOEN2_VAL, ~LDOEN2_MASK, },
 497         { RN5T567_LDODIS, 0x1f, ~0x1f, },
 498         { RN5T567_INTPOL, 0, },
 499         { RN5T567_INTEN, 0x3, },
 500         { RN5T567_DCIREN, 0xf, },
 501         { RN5T567_EN_GPIR, 0, },
 502 };
 503
 504 static int pmic_addr = 0x33;
 505 #endif
 506
 507 int board_init(void)
 508 {
 509         int ret;
 510         u32 cpurev = get_cpu_rev();
 511         char f = '?';
 512
 513         if (is_cpu_type(MXC_CPU_MX6UL))
 514                 f = ((cpurev & 0xff) > 0x10) ? '5' : '0';
 515         else if (is_cpu_type(MXC_CPU_MX6ULL))
 516                 f = '8';
 517
 518         debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
 519
 520         printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
 521
 522         get_hab_status();
 523
 524         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 525         if (ret < 0)
 526                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 527
 528         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 529
 530         /* Address of boot parameters */
 531         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 532         gd->bd->bi_arch_number = -1;
 533
 534         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 535                 if (wrsr & WRSR_TOUT)
 536                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 537                 else
 538                         printf("<CTRL-C> detected; safeboot enabled\n");
 539 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 540                 tx6ul_temp_check_enabled = false;
 541 #endif
 542                 return 0;
 543         }
 544
 545         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 546         if (ret) {
 547                 printf("Failed to setup PMIC voltages: %d\n", ret);
 548                 hang();
 549         }
 550         return 0;
 551 }
 552
 553 int dram_init(void)
 554 {
 555         debug("%s@%d: \n", __func__, __LINE__);
 556
 557         /* dram_init must store complete ramsize in gd->ram_size */
 558         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 559                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 560         return 0;
 561 }
 562
 563 void dram_init_banksize(void)
 564 {
 565         debug("%s@%d: \n", __func__, __LINE__);
 566
 567         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 568         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 569                                                PHYS_SDRAM_1_SIZE);
 570 #if CONFIG_NR_DRAM_BANKS > 1
 571         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 572         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 573                                                PHYS_SDRAM_2_SIZE);
 574 #endif
 575 }
 576
 577 #ifdef  CONFIG_FSL_ESDHC
 578 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
 579                                         PAD_CTL_SPEED_MED |             \
 580                                         PAD_CTL_DSE_40ohm |             \
 581                                         PAD_CTL_SRE_FAST)
 582
 583 static const iomux_v3_cfg_t mmc0_pads[] = {
 584         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
 585         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
 586         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
 587         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
 588         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
 589         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
 590         /* SD1 CD */
 591         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
 592 };
 593
 594 #ifdef CONFIG_TX6_EMMC
 595 static const iomux_v3_cfg_t mmc1_pads[] = {
 596         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
 597         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
 598         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
 599         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
 600         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
 601         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
 602         /* eMMC RESET */
 603         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 604                                                         PAD_CTL_DSE_40ohm),
 605 };
 606 #endif
 607
 608 static struct tx6ul_esdhc_cfg {
 609         const iomux_v3_cfg_t *pads;
 610         int num_pads;
 611         enum mxc_clock clkid;
 612         struct fsl_esdhc_cfg cfg;
 613         int cd_gpio;
 614 } tx6ul_esdhc_cfg[] = {
 615 #ifdef CONFIG_TX6_EMMC
 616         {
 617                 .pads = mmc1_pads,
 618                 .num_pads = ARRAY_SIZE(mmc1_pads),
 619                 .clkid = MXC_ESDHC2_CLK,
 620                 .cfg = {
 621                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 622                         .max_bus_width = 4,
 623                 },
 624                 .cd_gpio = -EINVAL,
 625         },
 626 #endif
 627         {
 628                 .pads = mmc0_pads,
 629                 .num_pads = ARRAY_SIZE(mmc0_pads),
 630                 .clkid = MXC_ESDHC_CLK,
 631                 .cfg = {
 632                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 633                         .max_bus_width = 4,
 634                 },
 635                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 636         },
 637 };
 638
 639 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 640 {
 641         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
 642 }
 643
 644 int board_mmc_getcd(struct mmc *mmc)
 645 {
 646         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
 647
 648         if (cfg->cd_gpio < 0)
 649                 return 1;
 650
 651         debug("SD card %d is %spresent (GPIO %d)\n",
 652               cfg - tx6ul_esdhc_cfg,
 653               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 654               cfg->cd_gpio);
 655         return !gpio_get_value(cfg->cd_gpio);
 656 }
 657
 658 int board_mmc_init(bd_t *bis)
 659 {
 660         int i;
 661
 662         debug("%s@%d: \n", __func__, __LINE__);
 663
 664 #ifndef CONFIG_ENV_IS_IN_MMC
 665         if (!(gd->flags & GD_FLG_ENV_READY)) {
 666                 printf("deferred ...");
 667                 return 0;
 668         }
 669 #endif
 670         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 671                 struct mmc *mmc;
 672                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 673                 int ret;
 674
 675                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 676                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 677
 678                 if (cfg->cd_gpio >= 0) {
 679                         ret = gpio_request_one(cfg->cd_gpio,
 680                                                GPIOFLAG_INPUT, "MMC CD");
 681                         if (ret) {
 682                                 printf("Error %d requesting GPIO%d_%d\n",
 683                                        ret, cfg->cd_gpio / 32,
 684                                        cfg->cd_gpio % 32);
 685                                 continue;
 686                         }
 687                 }
 688
 689                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 690                 fsl_esdhc_initialize(bis, &cfg->cfg);
 691
 692                 mmc = find_mmc_device(i);
 693                 if (mmc == NULL)
 694                         continue;
 695                 if (board_mmc_getcd(mmc))
 696                         mmc_init(mmc);
 697         }
 698         return 0;
 699 }
 700 #endif /* CONFIG_FSL_ESDHC */
 701
 702 enum {
 703         LED_STATE_INIT = -1,
 704         LED_STATE_OFF,
 705         LED_STATE_ON,
 706         LED_STATE_ERR,
 707 };
 708
 709 static inline int calc_blink_rate(void)
 710 {
 711         if (!tx6ul_temp_check_enabled)
 712                 return CONFIG_SYS_HZ;
 713
 714         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 715                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 716                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 717 }
 718
 719 void show_activity(int arg)
 720 {
 721         static int led_state = LED_STATE_INIT;
 722         static int blink_rate;
 723         static ulong last;
 724         int ret;
 725
 726         switch (led_state) {
 727         case LED_STATE_ERR:
 728                 return;
 729
 730         case LED_STATE_INIT:
 731                 last = get_timer(0);
 732                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
 733                 if (ret)
 734                         led_state = LED_STATE_ERR;
 735                 else
 736                         led_state = LED_STATE_ON;
 737                 blink_rate = calc_blink_rate();
 738                 break;
 739
 740         case LED_STATE_ON:
 741         case LED_STATE_OFF:
 742                 if (get_timer(last) > blink_rate) {
 743                         blink_rate = calc_blink_rate();
 744                         last = get_timer_masked();
 745                         if (led_state == LED_STATE_ON) {
 746                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 747                         } else {
 748                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 749                         }
 750                         led_state = 1 - led_state;
 751                 }
 752                 break;
 753         }
 754 }
 755
 756 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
 757         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
 758         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
 759         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
 760         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
 761         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
 762         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
 763 };
 764
 765 static const iomux_v3_cfg_t stk5_pads[] = {
 766         /* SW controlled LED on STK5 baseboard */
 767         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 768
 769         /* I2C bus on DIMM pins 40/41 */
 770         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 771         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 772
 773         /* TSC200x PEN IRQ */
 774         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
 775
 776         /* EDT-FT5x06 Polytouch panel */
 777         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
 778         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
 779         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
 780
 781         /* USBH1 */
 782         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 783         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 784
 785         /* USBOTG */
 786         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 787         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 788 };
 789
 790 static const struct gpio stk5_gpios[] = {
 791         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 792
 793         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
 794         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 795 };
 796
 797 static const iomux_v3_cfg_t tx_tester_pads[] = {
 798         /* SW controlled LEDs on TX-TESTER-V5 baseboard */
 799         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04, /* red LED */
 800         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09, /* yellow LED */
 801         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08, /* green LED */
 802
 803         MX6_PAD_LCD_DATA04__GPIO3_IO09, /* IO_RESET */
 804
 805         /* I2C bus on DIMM pins 40/41 */
 806         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 807         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
 808
 809         /* USBH1 */
 810         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 811         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 812
 813         /* USBOTG */
 814         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
 815         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
 816
 817         MX6_PAD_LCD_DATA08__GPIO3_IO13 | TX6UL_GPIO_OUT_PAD_CTRL,
 818         MX6_PAD_LCD_DATA09__GPIO3_IO14 | TX6UL_GPIO_OUT_PAD_CTRL,
 819         MX6_PAD_LCD_DATA10__GPIO3_IO15 | TX6UL_GPIO_OUT_PAD_CTRL,
 820
 821         /* USBH_VBUSEN */
 822         MX6_PAD_LCD_DATA11__GPIO3_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
 823
 824         /*
 825          * no drive capability for DUT_ETN_LINKLED, DUT_ETN_ACTLED
 826          * to not interfere whith the DUT ETN PHY strap pins
 827          */
 828         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02, MUX_PAD_CTRL(PAD_CTL_HYS |
 829                                                        PAD_CTL_DSE_DISABLE |
 830                                                        PAD_CTL_SPEED_LOW),
 831         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03, MUX_PAD_CTRL(PAD_CTL_HYS |
 832                                                        PAD_CTL_DSE_DISABLE |
 833                                                        PAD_CTL_SPEED_LOW),
 834 };
 835
 836 static const struct gpio tx_tester_gpios[] = {
 837         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LEDGE#", },
 838         { IMX_GPIO_NR(5, 4), GPIOFLAG_OUTPUT_INIT_LOW, "LEDRT#", },
 839         { IMX_GPIO_NR(5, 8), GPIOFLAG_OUTPUT_INIT_LOW, "LEDGN#", },
 840
 841         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_HIGH, "PMIC PWR_ON", },
 842
 843         { IMX_GPIO_NR(3, 5), GPIOFLAG_INPUT, "TSTART#", },
 844         { IMX_GPIO_NR(3, 6), GPIOFLAG_INPUT, "STARTED", },
 845         { IMX_GPIO_NR(3, 7), GPIOFLAG_INPUT, "TSTOP#", },
 846         { IMX_GPIO_NR(3, 8), GPIOFLAG_OUTPUT_INIT_LOW, "STOP#", },
 847
 848         { IMX_GPIO_NR(3, 10), GPIOFLAG_INPUT, "DUT_PGOOD", },
 849
 850         { IMX_GPIO_NR(3, 11), GPIOFLAG_OUTPUT_INIT_HIGH, "VBACKUP_OFF", },
 851         { IMX_GPIO_NR(3, 12), GPIOFLAG_OUTPUT_INIT_LOW, "VBACKUP_LOAD", },
 852
 853         { IMX_GPIO_NR(1, 10), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD1", },
 854         { IMX_GPIO_NR(3, 30), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD2", },
 855         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "VOUTLOAD3", },
 856
 857         { IMX_GPIO_NR(3, 13), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD1", },
 858         { IMX_GPIO_NR(3, 14), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD2", },
 859         { IMX_GPIO_NR(3, 15), GPIOFLAG_OUTPUT_INIT_LOW, "VIOLOAD3", },
 860 };
 861
 862 #ifdef CONFIG_LCD
 863 vidinfo_t panel_info = {
 864         /* set to max. size supported by SoC */
 865         .vl_col = 4096,
 866         .vl_row = 1024,
 867
 868         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 869 };
 870
 871 static struct fb_videomode tx6ul_fb_modes[] = {
 872 #ifndef CONFIG_SYS_LVDS_IF
 873         {
 874                 /* Standard VGA timing */
 875                 .name           = "VGA",
 876                 .refresh        = 60,
 877                 .xres           = 640,
 878                 .yres           = 480,
 879                 .pixclock       = KHZ2PICOS(25175),
 880                 .left_margin    = 48,
 881                 .hsync_len      = 96,
 882                 .right_margin   = 16,
 883                 .upper_margin   = 31,
 884                 .vsync_len      = 2,
 885                 .lower_margin   = 12,
 886                 .sync           = FB_SYNC_CLK_LAT_FALL,
 887         },
 888         {
 889                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 890                  * DE high active, 115.2 mm x 86.4 mm display area
 891                  * VGA compatible timing
 892                  */
 893                 .name           = "ETV570",
 894                 .refresh        = 60,
 895                 .xres           = 640,
 896                 .yres           = 480,
 897                 .pixclock       = KHZ2PICOS(25175),
 898                 .left_margin    = 114,
 899                 .hsync_len      = 30,
 900                 .right_margin   = 16,
 901                 .upper_margin   = 32,
 902                 .vsync_len      = 3,
 903                 .lower_margin   = 10,
 904                 .sync           = FB_SYNC_CLK_LAT_FALL,
 905         },
 906         {
 907                 /* Emerging ET0350G0DH6 320 x 240 display.
 908                  * 70.08 mm x 52.56 mm display area.
 909                  */
 910                 .name           = "ET0350",
 911                 .refresh        = 60,
 912                 .xres           = 320,
 913                 .yres           = 240,
 914                 .pixclock       = KHZ2PICOS(6500),
 915                 .left_margin    = 68 - 34,
 916                 .hsync_len      = 34,
 917                 .right_margin   = 20,
 918                 .upper_margin   = 18 - 3,
 919                 .vsync_len      = 3,
 920                 .lower_margin   = 4,
 921                 .sync           = FB_SYNC_CLK_LAT_FALL,
 922         },
 923         {
 924                 /* Emerging ET0430G0DH6 480 x 272 display.
 925                  * 95.04 mm x 53.856 mm display area.
 926                  */
 927                 .name           = "ET0430",
 928                 .refresh        = 60,
 929                 .xres           = 480,
 930                 .yres           = 272,
 931                 .pixclock       = KHZ2PICOS(9000),
 932                 .left_margin    = 2,
 933                 .hsync_len      = 41,
 934                 .right_margin   = 2,
 935                 .upper_margin   = 2,
 936                 .vsync_len      = 10,
 937                 .lower_margin   = 2,
 938         },
 939         {
 940                 /* Emerging ET0500G0DH6 800 x 480 display.
 941                  * 109.6 mm x 66.4 mm display area.
 942                  */
 943                 .name           = "ET0500",
 944                 .refresh        = 60,
 945                 .xres           = 800,
 946                 .yres           = 480,
 947                 .pixclock       = KHZ2PICOS(33260),
 948                 .left_margin    = 216 - 128,
 949                 .hsync_len      = 128,
 950                 .right_margin   = 1056 - 800 - 216,
 951                 .upper_margin   = 35 - 2,
 952                 .vsync_len      = 2,
 953                 .lower_margin   = 525 - 480 - 35,
 954                 .sync           = FB_SYNC_CLK_LAT_FALL,
 955         },
 956         {
 957                 /* Emerging ETQ570G0DH6 320 x 240 display.
 958                  * 115.2 mm x 86.4 mm display area.
 959                  */
 960                 .name           = "ETQ570",
 961                 .refresh        = 60,
 962                 .xres           = 320,
 963                 .yres           = 240,
 964                 .pixclock       = KHZ2PICOS(6400),
 965                 .left_margin    = 38,
 966                 .hsync_len      = 30,
 967                 .right_margin   = 30,
 968                 .upper_margin   = 16, /* 15 according to datasheet */
 969                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 970                 .lower_margin   = 4, /* 4.5 according to datasheet */
 971                 .sync           = FB_SYNC_CLK_LAT_FALL,
 972         },
 973         {
 974                 /* Emerging ET0700G0DH6 800 x 480 display.
 975                  * 152.4 mm x 91.44 mm display area.
 976                  */
 977                 .name           = "ET0700",
 978                 .refresh        = 60,
 979                 .xres           = 800,
 980                 .yres           = 480,
 981                 .pixclock       = KHZ2PICOS(33260),
 982                 .left_margin    = 216 - 128,
 983                 .hsync_len      = 128,
 984                 .right_margin   = 1056 - 800 - 216,
 985                 .upper_margin   = 35 - 2,
 986                 .vsync_len      = 2,
 987                 .lower_margin   = 525 - 480 - 35,
 988                 .sync           = FB_SYNC_CLK_LAT_FALL,
 989         },
 990         {
 991                 /* Emerging ET070001DM6 800 x 480 display.
 992                  * 152.4 mm x 91.44 mm display area.
 993                  */
 994                 .name           = "ET070001DM6",
 995                 .refresh        = 60,
 996                 .xres           = 800,
 997                 .yres           = 480,
 998                 .pixclock       = KHZ2PICOS(33260),
 999                 .left_margin    = 216 - 128,
1000                 .hsync_len      = 128,
1001                 .right_margin   = 1056 - 800 - 216,
1002                 .upper_margin   = 35 - 2,
1003                 .vsync_len      = 2,
1004                 .lower_margin   = 525 - 480 - 35,
1005                 .sync           = 0,
1006         },
1007 #else
1008         {
1009                 /* HannStar HSD100PXN1
1010                  * 202.7m mm x 152.06 mm display area.
1011                  */
1012                 .name           = "HSD100PXN1",
1013                 .refresh        = 60,
1014                 .xres           = 1024,
1015                 .yres           = 768,
1016                 .pixclock       = KHZ2PICOS(65000),
1017                 .left_margin    = 0,
1018                 .hsync_len      = 0,
1019                 .right_margin   = 320,
1020                 .upper_margin   = 0,
1021                 .vsync_len      = 0,
1022                 .lower_margin   = 38,
1023                 .sync           = FB_SYNC_CLK_LAT_FALL,
1024         },
1025 #endif
1026         {
1027                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
1028                 .refresh        = 60,
1029                 .left_margin    = 48,
1030                 .hsync_len      = 96,
1031                 .right_margin   = 16,
1032                 .upper_margin   = 31,
1033                 .vsync_len      = 2,
1034                 .lower_margin   = 12,
1035                 .sync           = FB_SYNC_CLK_LAT_FALL,
1036         },
1037 };
1038
1039 static int lcd_enabled = 1;
1040 static int lcd_bl_polarity;
1041
1042 static int lcd_backlight_polarity(void)
1043 {
1044         return lcd_bl_polarity;
1045 }
1046
1047 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1048 #ifdef CONFIG_LCD
1049         /* LCD RESET */
1050         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1051         /* LCD POWER_ENABLE */
1052         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
1053         /* LCD Backlight (PWM) */
1054         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
1055         /* Display */
1056         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
1057         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
1058         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
1059         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
1060         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
1061         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
1062         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
1063         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
1064         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
1065         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
1066         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
1067         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
1068         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
1069         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
1070         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
1071         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
1072         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
1073         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
1074         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
1075         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1076         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1077         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1078         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1079         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1080         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1081         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1082         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1083         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1084 #endif
1085 };
1086
1087 static const struct gpio stk5_lcd_gpios[] = {
1088         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1089         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1090         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1091 };
1092
1093 /* run with valid env from NAND/eMMC */
1094 void lcd_enable(void)
1095 {
1096         /* HACK ALERT:
1097          * global variable from common/lcd.c
1098          * Set to 0 here to prevent messages from going to LCD
1099          * rather than serial console
1100          */
1101         lcd_is_enabled = 0;
1102
1103         if (lcd_enabled) {
1104                 karo_load_splashimage(1);
1105
1106                 debug("Switching LCD on\n");
1107                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1108                 udelay(100);
1109                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1110                 udelay(300000);
1111                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1112                                lcd_backlight_polarity());
1113         }
1114 }
1115
1116 static void lcd_disable(void)
1117 {
1118         if (lcd_enabled) {
1119                 printf("Disabling LCD\n");
1120                 panel_info.vl_row = 0;
1121                 lcd_enabled = 0;
1122         }
1123 }
1124
1125 void lcd_ctrl_init(void *lcdbase)
1126 {
1127         int color_depth = 24;
1128         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1129         const char *vm;
1130         unsigned long val;
1131         int refresh = 60;
1132         struct fb_videomode *p = &tx6ul_fb_modes[0];
1133         struct fb_videomode fb_mode;
1134         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1135
1136         if (!lcd_enabled) {
1137                 debug("LCD disabled\n");
1138                 return;
1139         }
1140
1141         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1142                 lcd_disable();
1143                 setenv("splashimage", NULL);
1144                 return;
1145         }
1146
1147         karo_fdt_move_fdt();
1148         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1149
1150         if (video_mode == NULL) {
1151                 lcd_disable();
1152                 return;
1153         }
1154         vm = video_mode;
1155         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1156                 p = &fb_mode;
1157                 debug("Using video mode from FDT\n");
1158                 vm += strlen(vm);
1159                 if (fb_mode.xres > panel_info.vl_col ||
1160                         fb_mode.yres > panel_info.vl_row) {
1161                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1162                                fb_mode.xres, fb_mode.yres,
1163                                panel_info.vl_col, panel_info.vl_row);
1164                         lcd_enabled = 0;
1165                         return;
1166                 }
1167         }
1168         if (p->name != NULL)
1169                 debug("Trying compiled-in video modes\n");
1170         while (p->name != NULL) {
1171                 if (strcmp(p->name, vm) == 0) {
1172                         debug("Using video mode: '%s'\n", p->name);
1173                         vm += strlen(vm);
1174                         break;
1175                 }
1176                 p++;
1177         }
1178         if (*vm != '\0')
1179                 debug("Trying to decode video_mode: '%s'\n", vm);
1180         while (*vm != '\0') {
1181                 if (*vm >= '0' && *vm <= '9') {
1182                         char *end;
1183
1184                         val = simple_strtoul(vm, &end, 0);
1185                         if (end > vm) {
1186                                 if (!xres_set) {
1187                                         if (val > panel_info.vl_col)
1188                                                 val = panel_info.vl_col;
1189                                         p->xres = val;
1190                                         panel_info.vl_col = val;
1191                                         xres_set = 1;
1192                                 } else if (!yres_set) {
1193                                         if (val > panel_info.vl_row)
1194                                                 val = panel_info.vl_row;
1195                                         p->yres = val;
1196                                         panel_info.vl_row = val;
1197                                         yres_set = 1;
1198                                 } else if (!bpp_set) {
1199                                         switch (val) {
1200                                         case 8:
1201                                         case 16:
1202                                         case 18:
1203                                         case 24:
1204                                         case 32:
1205                                                 color_depth = val;
1206                                                 break;
1207
1208                                         default:
1209                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1210                                                        end - vm, vm,
1211                                                        color_depth);
1212                                         }
1213                                         bpp_set = 1;
1214                                 } else if (!refresh_set) {
1215                                         refresh = val;
1216                                         refresh_set = 1;
1217                                 }
1218                         }
1219                         vm = end;
1220                 }
1221                 switch (*vm) {
1222                 case '@':
1223                         bpp_set = 1;
1224                         /* fallthru */
1225                 case '-':
1226                         yres_set = 1;
1227                         /* fallthru */
1228                 case 'x':
1229                         xres_set = 1;
1230                         /* fallthru */
1231                 case 'M':
1232                 case 'R':
1233                         vm++;
1234                         break;
1235
1236                 default:
1237                         if (*vm != '\0')
1238                                 vm++;
1239                 }
1240         }
1241         if (p->xres == 0 || p->yres == 0) {
1242                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1243                 lcd_enabled = 0;
1244                 printf("Supported video modes are:");
1245                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1246                         printf(" %s", p->name);
1247                 }
1248                 printf("\n");
1249                 return;
1250         }
1251         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1252                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1253                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1254                 lcd_enabled = 0;
1255                 return;
1256         }
1257         panel_info.vl_col = p->xres;
1258         panel_info.vl_row = p->yres;
1259
1260         switch (color_depth) {
1261         case 8:
1262                 panel_info.vl_bpix = LCD_COLOR8;
1263                 break;
1264         case 16:
1265                 panel_info.vl_bpix = LCD_COLOR16;
1266                 break;
1267         default:
1268                 panel_info.vl_bpix = LCD_COLOR32;
1269         }
1270
1271         if (refresh_set || p->pixclock == 0)
1272                 p->pixclock = KHZ2PICOS(refresh *
1273                                         (p->xres + p->left_margin +
1274                                          p->right_margin + p->hsync_len) *
1275                                         (p->yres + p->upper_margin +
1276                                          p->lower_margin + p->vsync_len) /
1277                                         1000);
1278         debug("Pixel clock set to %lu.%03lu MHz\n",
1279               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1280
1281         if (p != &fb_mode) {
1282                 int ret;
1283
1284                 debug("Creating new display-timing node from '%s'\n",
1285                       video_mode);
1286                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1287                 if (ret)
1288                         printf("Failed to create new display-timing node from '%s': %d\n",
1289                                video_mode, ret);
1290         }
1291
1292         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1293         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1294                                          ARRAY_SIZE(stk5_lcd_pads));
1295
1296         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1297               color_depth, refresh);
1298
1299         if (karo_load_splashimage(0) == 0) {
1300                 char vmode[128];
1301
1302                 /* setup env variable for mxsfb display driver */
1303                 snprintf(vmode, sizeof(vmode),
1304                          "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1305                          p->xres, p->yres, p->left_margin, p->right_margin,
1306                          p->upper_margin, p->lower_margin, p->hsync_len,
1307                          p->vsync_len, p->sync, p->pixclock, color_depth);
1308                 setenv("videomode", vmode);
1309
1310                 debug("Initializing LCD controller\n");
1311                 lcdif_clk_enable();
1312                 video_hw_init();
1313                 setenv("videomode", NULL);
1314         } else {
1315                 debug("Skipping initialization of LCD controller\n");
1316         }
1317 }
1318 #else
1319 #define lcd_enabled 0
1320 #endif /* CONFIG_LCD */
1321
1322 #ifndef CONFIG_ENV_IS_IN_MMC
1323 static void tx6ul_mmc_init(void)
1324 {
1325         puts("MMC:   ");
1326         if (board_mmc_init(gd->bd) < 0)
1327                 cpu_mmc_init(gd->bd);
1328         print_mmc_devices(',');
1329 }
1330 #else
1331 static inline void tx6ul_mmc_init(void)
1332 {
1333 }
1334 #endif
1335
1336 static void stk5_board_init(void)
1337 {
1338         int ret;
1339
1340         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1341         if (ret < 0) {
1342                 printf("Failed to request stk5_gpios: %d\n", ret);
1343                 return;
1344         }
1345
1346         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1347         if (getenv_yesno("jtag_enable") != 0) {
1348                 /* true if unset or set to one of: 'yYtT1' */
1349                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1350         }
1351
1352         debug("%s@%d: \n", __func__, __LINE__);
1353 }
1354
1355 static void stk5v3_board_init(void)
1356 {
1357         debug("%s@%d: \n", __func__, __LINE__);
1358         stk5_board_init();
1359         debug("%s@%d: \n", __func__, __LINE__);
1360         tx6ul_mmc_init();
1361 }
1362
1363 static void stk5v5_board_init(void)
1364 {
1365         int ret;
1366
1367         stk5_board_init();
1368         tx6ul_mmc_init();
1369
1370         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1371                                "Flexcan Transceiver");
1372         if (ret) {
1373                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1374                 return;
1375         }
1376
1377         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1378                                TX6UL_GPIO_OUT_PAD_CTRL);
1379 }
1380
1381 static void tx_tester_board_init(void)
1382 {
1383         int ret;
1384
1385         setenv("video_mode", NULL);
1386         setenv("touchpanel", NULL);
1387         if (getenv("eth1addr") && !getenv("ethprime"))
1388                 setenv("ethprime", "FEC1");
1389
1390         ret = gpio_request_array(tx_tester_gpios, ARRAY_SIZE(tx_tester_gpios));
1391         if (ret) {
1392                 printf("Failed to request TX-Tester GPIOs: %d\n", ret);
1393                 return;
1394         }
1395         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1396
1397         if (wrsr & WRSR_TOUT)
1398                 gpio_set_value(IMX_GPIO_NR(5, 4), 1);
1399
1400         if (getenv_yesno("jtag_enable") != 0) {
1401                 /* true if unset or set to one of: 'yYtT1' */
1402                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads,
1403                                                  ARRAY_SIZE(stk5_jtag_pads));
1404         }
1405
1406         gpio_set_value(IMX_GPIO_NR(3, 8), 1);
1407 }
1408
1409 static void tx6ul_set_cpu_clock(void)
1410 {
1411         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1412
1413         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1414                 return;
1415
1416         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1417                 printf("%s detected; skipping cpu clock change\n",
1418                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1419                 return;
1420         }
1421         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1422                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1423                 printf("CPU clock set to %lu.%03lu MHz\n",
1424                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1425         } else {
1426                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1427         }
1428 }
1429
1430 int board_late_init(void)
1431 {
1432         const char *baseboard;
1433
1434         debug("%s@%d: \n", __func__, __LINE__);
1435
1436         env_cleanup();
1437
1438         if (tx6ul_temp_check_enabled)
1439                 check_cpu_temperature(1);
1440
1441         tx6ul_set_cpu_clock();
1442
1443         if (had_ctrlc())
1444                 setenv_ulong("safeboot", 1);
1445         else if (wrsr & WRSR_TOUT)
1446                 setenv_ulong("wdreset", 1);
1447         else
1448                 karo_fdt_move_fdt();
1449
1450         baseboard = getenv("baseboard");
1451         if (!baseboard)
1452                 goto exit;
1453
1454         printf("Baseboard: %s\n", baseboard);
1455
1456         if (strncmp(baseboard, "stk5", 4) == 0) {
1457                 if ((strlen(baseboard) == 4) ||
1458                         strcmp(baseboard, "stk5-v3") == 0) {
1459                         stk5v3_board_init();
1460                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1461                         const char *otg_mode = getenv("otg_mode");
1462
1463                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1464                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1465                                        otg_mode, baseboard);
1466                                 setenv("otg_mode", "none");
1467                         }
1468                         stk5v5_board_init();
1469                 } else {
1470                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1471                                 baseboard + 4);
1472                 }
1473         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1474                         const char *otg_mode = getenv("otg_mode");
1475
1476                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1477                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1478                                        otg_mode, baseboard);
1479                                 setenv("otg_mode", "none");
1480                         }
1481                         stk5_board_init();
1482         } else if (strncmp(baseboard, "tx-tester-", 10) == 0) {
1483                         const char *otg_mode = getenv("otg_mode");
1484
1485                         if (!otg_mode || strcmp(otg_mode, "none") != 0)
1486                                 setenv("otg_mode", "device");
1487                         tx_tester_board_init();
1488         } else {
1489                 printf("WARNING: Unsupported baseboard: '%s'\n",
1490                         baseboard);
1491                 printf("Reboot with <CTRL-C> pressed to fix this\n");
1492                 if (!had_ctrlc())
1493                         return -EINVAL;
1494         }
1495
1496 exit:
1497         debug("%s@%d: \n", __func__, __LINE__);
1498
1499         clear_ctrlc();
1500         return 0;
1501 }
1502
1503 #ifdef CONFIG_FEC_MXC
1504
1505 #ifndef ETH_ALEN
1506 #define ETH_ALEN 6
1507 #endif
1508
1509 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
1510 {
1511         unsigned int mac0, mac1, mac2;
1512         unsigned int __maybe_unused fuse3_override, fuse4_override;
1513
1514         memset(mac, 0, 6);
1515
1516         switch (dev_id) {
1517         case 0:
1518                 if (fuse_read(4, 2, &mac0)) {
1519                         printf("Failed to read MAC0 fuse\n");
1520                         return;
1521                 }
1522                 if (fuse_read(4, 3, &mac1)) {
1523                         printf("Failed to read MAC1 fuse\n");
1524                         return;
1525                 }
1526                 mac[0] = mac1 >> 8;
1527                 mac[1] = mac1;
1528                 mac[2] = mac0 >> 24;
1529                 mac[3] = mac0 >> 16;
1530                 mac[4] = mac0 >> 8;
1531                 mac[5] = mac0;
1532                 break;
1533
1534         case 1:
1535                 if (fuse_read(4, 3, &mac1)) {
1536                         printf("Failed to read MAC1 fuse\n");
1537                         return;
1538                 }
1539                 debug("read %08x from fuse 3\n", mac1);
1540                 if (fuse_read(4, 4, &mac2)) {
1541                         printf("Failed to read MAC2 fuse\n");
1542                         return;
1543                 }
1544                 debug("read %08x from fuse 4\n", mac2);
1545                 mac[0] = mac2 >> 24;
1546                 mac[1] = mac2 >> 16;
1547                 mac[2] = mac2 >> 8;
1548                 mac[3] = mac2;
1549                 mac[4] = mac1 >> 24;
1550                 mac[5] = mac1 >> 16;
1551                 break;
1552
1553         default:
1554                 return;
1555         }
1556         debug("%s@%d: Done %d %pM\n", __func__, __LINE__, dev_id, mac);
1557 }
1558
1559 static void tx6ul_init_mac(void)
1560 {
1561         u8 mac[ETH_ALEN];
1562         const char *baseboard = getenv("baseboard");
1563
1564         imx_get_mac_from_fuse(0, mac);
1565         if (!is_valid_ethaddr(mac)) {
1566                 printf("No valid MAC address programmed\n");
1567                 return;
1568         }
1569         printf("MAC addr from fuse: %pM\n", mac);
1570         if (!getenv("ethaddr"))
1571                 eth_setenv_enetaddr("ethaddr", mac);
1572
1573         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1574                 setenv("eth1addr", NULL);
1575                 return;
1576         }
1577         if (getenv("eth1addr"))
1578                 return;
1579         imx_get_mac_from_fuse(1, mac);
1580         if (is_valid_ethaddr(mac))
1581                 eth_setenv_enetaddr("eth1addr", mac);
1582 }
1583
1584 int board_eth_init(bd_t *bis)
1585 {
1586         int ret;
1587
1588         tx6ul_init_mac();
1589
1590         /* delay at least 21ms for the PHY internal POR signal to deassert */
1591         udelay(22000);
1592
1593         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1594                                          ARRAY_SIZE(tx6ul_enet1_pads));
1595
1596         /* Deassert RESET to the external phys */
1597         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1598
1599         if (getenv("ethaddr")) {
1600                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1601                 if (ret) {
1602                         printf("failed to initialize FEC0: %d\n", ret);
1603                         return ret;
1604                 }
1605         }
1606         if (getenv("eth1addr")) {
1607                 ret = gpio_request_array(tx6ul_fec2_gpios,
1608                                          ARRAY_SIZE(tx6ul_fec2_gpios));
1609                 if (ret < 0) {
1610                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1611                 }
1612                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1613                                                  ARRAY_SIZE(tx6ul_enet2_pads));
1614
1615                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1616
1617                 /* Minimum PHY reset duration */
1618                 udelay(100);
1619                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1620                 /* Wait for PHY internal POR to finish */
1621                 udelay(22000);
1622
1623                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1624                 if (ret) {
1625                         printf("failed to initialize FEC1: %d\n", ret);
1626                         return ret;
1627                 }
1628         }
1629         return 0;
1630 }
1631 #endif /* CONFIG_FEC_MXC */
1632
1633 #ifdef CONFIG_SERIAL_TAG
1634 void get_board_serial(struct tag_serialnr *serialnr)
1635 {
1636         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1637         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1638
1639         serialnr->low = readl(&fuse->cfg0);
1640         serialnr->high = readl(&fuse->cfg1);
1641 }
1642 #endif
1643
1644 #if defined(CONFIG_OF_BOARD_SETUP)
1645 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1646 #include <jffs2/jffs2.h>
1647 #include <mtd_node.h>
1648 static struct node_info nodes[] = {
1649         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1650 };
1651 #else
1652 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1653 #endif
1654
1655 static const char *tx6ul_touchpanels[] = {
1656         "ti,tsc2007",
1657         "edt,edt-ft5x06",
1658         "eeti,egalax_ts",
1659 };
1660
1661 int ft_board_setup(void *blob, bd_t *bd)
1662 {
1663         const char *baseboard = getenv("baseboard");
1664         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1665         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1666         int ret;
1667
1668         ret = fdt_increase_size(blob, 4096);
1669         if (ret) {
1670                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1671                 return ret;
1672         }
1673         if (stk5_v5)
1674                 karo_fdt_enable_node(blob, "stk5led", 0);
1675
1676         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1677
1678         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1679                                   ARRAY_SIZE(tx6ul_touchpanels));
1680         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1681         karo_fdt_fixup_flexcan(blob, stk5_v5);
1682
1683         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1684
1685         return 0;
1686 }
1687 #endif /* CONFIG_OF_BOARD_SETUP */