board/karo/tx6/tx6ul.c

   1 /*
   2  * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  *
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <libfdt.h>
  10 #include <fdt_support.h>
  11 #include <lcd.h>
  12 #include <netdev.h>
  13 #include <mmc.h>
  14 #include <fsl_esdhc.h>
  15 #include <video_fb.h>
  16 #include <ipu.h>
  17 #include <mxcfb.h>
  18 #include <i2c.h>
  19 #include <linux/fb.h>
  20 #include <asm/io.h>
  21 #include <asm/gpio.h>
  22 #include <asm/arch/mx6-pins.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/hab.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28
  29 #include "../common/karo.h"
  30 #include "pmic.h"
  31
  32 #define __data __attribute__((section(".data")))
  33
  34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
  35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
  36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
  37 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
  38
  39 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
  40 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
  41 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
  42
  43 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
  44 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
  45
  46 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
  47
  48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
  49 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
  50 #else
  51 #define TEMPERATURE_MIN                 (-40)
  52 #endif
  53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
  54 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
  55 #else
  56 #define TEMPERATURE_HOT                 80
  57 #endif
  58
  59 DECLARE_GLOBAL_DATA_PTR;
  60
  61 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
  62
  63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
  64 #ifdef CONFIG_SECURE_BOOT
  65 char __csf_data[0] __attribute__((section(".__csf_data")));
  66 #endif
  67
  68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
  69         /* UART pads */
  70 #if CONFIG_MXC_UART_BASE == UART1_BASE
  71         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
  72         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
  73         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
  74         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
  75 #endif
  76 #if CONFIG_MXC_UART_BASE == UART2_BASE
  77         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
  78         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
  79         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
  80         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
  81 #endif
  82 #if CONFIG_MXC_UART_BASE == UART5_BASE
  83         MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
  84         MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
  85         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
  86         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
  87 #endif
  88         /* internal I2C */
  89         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
  90                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
  91         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
  92                         MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
  93                         PAD_CTL_ODE), /* I2C SDA */
  94
  95         /* FEC PHY GPIO functions */
  96         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
  97         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
  98         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
  99                                                         PAD_CTL_DSE_40ohm), /* PHY INT */
 100 };
 101
 102 #define TX6_ENET_PAD_CTRL       (PAD_CTL_SPEED_HIGH |   \
 103                                 PAD_CTL_DSE_48ohm |     \
 104                                 PAD_CTL_PUS_100K_UP |   \
 105                                 PAD_CTL_SRE_FAST)
 106 #define TX6_GPIO_OUT_PAD_CTRL   (PAD_CTL_SPEED_LOW |    \
 107                                 PAD_CTL_DSE_60ohm |     \
 108                                 PAD_CTL_SRE_SLOW)
 109 #define TX6_GPIO_IN_PAD_CTRL    (PAD_CTL_SPEED_LOW |    \
 110                                 PAD_CTL_PUS_47K_UP)
 111
 112 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
 113         /* FEC functions */
 114         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
 115                                 PAD_CTL_SPEED_MED),
 116         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
 117                                 PAD_CTL_DSE_48ohm |
 118                                 PAD_CTL_SPEED_MED),
 119         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
 120                                 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
 121                                 PAD_CTL_DSE_40ohm |
 122                                 PAD_CTL_SRE_FAST),
 123         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 124         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 125         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 126         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 127         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 128         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 129         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 130
 131         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
 132                                 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
 133                                 PAD_CTL_DSE_48ohm |
 134                                 PAD_CTL_SRE_FAST),
 135         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 136         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 137         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 138         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 139         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 140         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 141         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
 142 };
 143
 144 #define TX6_I2C_PAD_CTRL        (PAD_CTL_PUS_22K_UP |   \
 145                                 PAD_CTL_SPEED_MED |     \
 146                                 PAD_CTL_DSE_34ohm |     \
 147                                 PAD_CTL_SRE_FAST)
 148
 149 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
 150         /* internal I2C */
 151         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 152         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 153 };
 154
 155 static const struct gpio const tx6ul_gpios[] = {
 156         /* These two entries are used to forcefully reinitialize the I2C bus */
 157         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
 158         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
 159
 160         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
 161         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
 162         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
 163 };
 164
 165 #define GPIO_DR 0
 166 #define GPIO_DIR 4
 167 #define GPIO_PSR 8
 168
 169 static void tx6_i2c_recover(void)
 170 {
 171         int i;
 172         int bad = 0;
 173 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
 174 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
 175 #define I2C_GPIO_BASE   (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
 176
 177         if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
 178                         (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
 179                 return;
 180
 181         debug("Clearing I2C bus\n");
 182         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
 183                 printf("I2C SCL stuck LOW\n");
 184                 bad++;
 185
 186                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
 187                         I2C_GPIO_BASE + GPIO_DR);
 188                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
 189                         I2C_GPIO_BASE + GPIO_DIR);
 190         }
 191         if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
 192                 printf("I2C SDA stuck LOW\n");
 193                 bad++;
 194
 195                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
 196                         I2C_GPIO_BASE + GPIO_DIR);
 197                 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
 198                         I2C_GPIO_BASE + GPIO_DR);
 199                 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
 200                         I2C_GPIO_BASE + GPIO_DIR);
 201
 202                 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
 203                                                 ARRAY_SIZE(tx6_i2c_gpio_pads));
 204                 udelay(10);
 205
 206                 for (i = 0; i < 18; i++) {
 207                         u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
 208
 209                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
 210                         writel(reg, I2C_GPIO_BASE + GPIO_DR);
 211                         udelay(10);
 212                         if (reg & SCL_BIT &&
 213                                 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
 214                                 break;
 215                 }
 216         }
 217         if (bad) {
 218                 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
 219
 220                 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
 221                         printf("I2C bus recovery succeeded\n");
 222                 } else {
 223                         printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
 224                                 SCL_BIT | SDA_BIT);
 225                 }
 226         }
 227 }
 228
 229 /* placed in section '.data' to prevent overwriting relocation info
 230  * overlayed with bss
 231  */
 232 static u32 wrsr __data;
 233
 234 #define WRSR_POR                        (1 << 4)
 235 #define WRSR_TOUT                       (1 << 1)
 236 #define WRSR_SFTW                       (1 << 0)
 237
 238 static void print_reset_cause(void)
 239 {
 240         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 241         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
 242         u32 srsr;
 243         char *dlm = "";
 244
 245         printf("Reset cause: ");
 246
 247         srsr = readl(&src_regs->srsr);
 248         wrsr = readw(wdt_base + 4);
 249
 250         if (wrsr & WRSR_POR) {
 251                 printf("%sPOR", dlm);
 252                 dlm = " | ";
 253         }
 254         if (srsr & 0x00004) {
 255                 printf("%sCSU", dlm);
 256                 dlm = " | ";
 257         }
 258         if (srsr & 0x00008) {
 259                 printf("%sIPP USER", dlm);
 260                 dlm = " | ";
 261         }
 262         if (srsr & 0x00010) {
 263                 if (wrsr & WRSR_SFTW) {
 264                         printf("%sSOFT", dlm);
 265                         dlm = " | ";
 266                 }
 267                 if (wrsr & WRSR_TOUT) {
 268                         printf("%sWDOG", dlm);
 269                         dlm = " | ";
 270                 }
 271         }
 272         if (srsr & 0x00020) {
 273                 printf("%sJTAG HIGH-Z", dlm);
 274                 dlm = " | ";
 275         }
 276         if (srsr & 0x00040) {
 277                 printf("%sJTAG SW", dlm);
 278                 dlm = " | ";
 279         }
 280         if (srsr & 0x10000) {
 281                 printf("%sWARM BOOT", dlm);
 282                 dlm = " | ";
 283         }
 284         if (dlm[0] == '\0')
 285                 printf("unknown");
 286
 287         printf("\n");
 288 }
 289
 290 #ifdef CONFIG_IMX6_THERMAL
 291 #include <thermal.h>
 292 #include <imx_thermal.h>
 293 #include <fuse.h>
 294
 295 static void print_temperature(void)
 296 {
 297         struct udevice *thermal_dev;
 298         int cpu_tmp, minc, maxc, ret;
 299         char const *grade_str;
 300         static u32 __data thermal_calib;
 301
 302         puts("Temperature: ");
 303         switch (get_cpu_temp_grade(&minc, &maxc)) {
 304         case TEMP_AUTOMOTIVE:
 305                 grade_str = "Automotive";
 306                 break;
 307         case TEMP_INDUSTRIAL:
 308                 grade_str = "Industrial";
 309                 break;
 310         case TEMP_EXTCOMMERCIAL:
 311                 grade_str = "Extended Commercial";
 312                 break;
 313         default:
 314                 grade_str = "Commercial";
 315         }
 316         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
 317         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
 318         if (ret == 0) {
 319                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
 320
 321                 if (ret == 0)
 322                         printf(" at %dC", cpu_tmp);
 323                 else
 324                         puts(" - failed to read sensor data");
 325         } else {
 326                 puts(" - no sensor device found");
 327         }
 328
 329         if (fuse_read(1, 6, &thermal_calib) == 0) {
 330                 printf(" - calibration data 0x%08x\n", thermal_calib);
 331         } else {
 332                 puts(" - Failed to read thermal calib fuse\n");
 333         }
 334 }
 335 #else
 336 static inline void print_temperature(void)
 337 {
 338 }
 339 #endif
 340
 341 int checkboard(void)
 342 {
 343         u32 cpurev = get_cpu_rev();
 344         char *cpu_str = "?";
 345
 346         switch ((cpurev >> 12) & 0xff) {
 347         case MXC_CPU_MX6SL:
 348                 cpu_str = "SL";
 349                 break;
 350         case MXC_CPU_MX6DL:
 351                 cpu_str = "DL";
 352                 break;
 353         case MXC_CPU_MX6SOLO:
 354                 cpu_str = "SOLO";
 355                 break;
 356         case MXC_CPU_MX6Q:
 357                 cpu_str = "Q";
 358                 break;
 359         case MXC_CPU_MX6UL:
 360                 cpu_str = "UL";
 361                 break;
 362         }
 363
 364         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
 365                 cpu_str,
 366                 (cpurev & 0x000F0) >> 4,
 367                 (cpurev & 0x0000F) >> 0,
 368                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 369
 370         print_temperature();
 371         print_reset_cause();
 372 #ifdef CONFIG_MX6_TEMPERATURE_HOT
 373         check_cpu_temperature(1);
 374 #endif
 375         tx6_i2c_recover();
 376         return 0;
 377 }
 378
 379 /* serial port not initialized at this point */
 380 int board_early_init_f(void)
 381 {
 382         return 0;
 383 }
 384
 385 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 386 static bool tx6_temp_check_enabled = true;
 387 #else
 388 #define tx6_temp_check_enabled  0
 389 #endif
 390
 391 static inline u8 tx6ul_mem_suffix(void)
 392 {
 393 #ifdef CONFIG_TX6_NAND
 394         return '0';
 395 #else
 396         return '1';
 397 #endif
 398 }
 399
 400 /* PMIC settings */
 401 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
 402 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
 403 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
 404 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
 405 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
 406 #define VDD_HIGH_VAL            rn5t_mV_to_regval(3300)         /* DCDC4 */
 407 #define VDD_HIGH_VAL_LP         rn5t_mV_to_regval(3300)
 408 #define VDD_CSI_VAL             rn5t_mV_to_regval2(3300)        /* LDO4 */
 409 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(3300)
 410
 411 static struct pmic_regs rn5t567_regs[] = {
 412         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
 413         { RN5T567_DC2CTL, DC2_DC2DIS, },
 414         { RN5T567_DC1DAC, VDD_CORE_VAL, },
 415         { RN5T567_DC3DAC, VDD_DDR_VAL, },
 416         { RN5T567_DC4DAC, VDD_HIGH_VAL, },
 417         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
 418         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
 419         { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
 420         { RN5T567_LDOEN1, 0x01f, ~0x1f, },
 421         { RN5T567_LDOEN2, 0x10, ~0x30, },
 422         { RN5T567_LDODIS, 0x00, },
 423         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
 424         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
 425         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
 426 };
 427
 428 static int pmic_addr __maybe_unused = 0x33;
 429
 430 int board_init(void)
 431 {
 432         int ret;
 433
 434         debug("%s@%d: \n", __func__, __LINE__);
 435
 436         printf("Board: Ka-Ro TXUL-001%c\n",
 437                 tx6ul_mem_suffix());
 438
 439         get_hab_status();
 440
 441         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
 442         if (ret < 0) {
 443                 printf("Failed to request tx6ul_gpios: %d\n", ret);
 444         }
 445         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
 446
 447         /* Address of boot parameters */
 448         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
 449         gd->bd->bi_arch_number = -1;
 450
 451         if (ctrlc() || (wrsr & WRSR_TOUT)) {
 452                 if (wrsr & WRSR_TOUT)
 453                         printf("WDOG RESET detected; Skipping PMIC setup\n");
 454                 else
 455                         printf("<CTRL-C> detected; safeboot enabled\n");
 456 #ifndef CONFIG_MX6_TEMPERATURE_HOT
 457                 tx6_temp_check_enabled = false;
 458 #endif
 459                 return 0;
 460         }
 461
 462         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
 463         if (ret) {
 464                 printf("Failed to setup PMIC voltages: %d\n", ret);
 465                 hang();
 466         }
 467         return 0;
 468 }
 469
 470 int dram_init(void)
 471 {
 472         debug("%s@%d: \n", __func__, __LINE__);
 473
 474         /* dram_init must store complete ramsize in gd->ram_size */
 475         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 476                                 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
 477         return 0;
 478 }
 479
 480 void dram_init_banksize(void)
 481 {
 482         debug("%s@%d: \n", __func__, __LINE__);
 483
 484         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 485         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
 486                         PHYS_SDRAM_1_SIZE);
 487 #if CONFIG_NR_DRAM_BANKS > 1
 488         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 489         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
 490                         PHYS_SDRAM_2_SIZE);
 491 #endif
 492 }
 493
 494 #ifdef  CONFIG_FSL_ESDHC
 495 #define TX6_SD_PAD_CTRL         (PAD_CTL_PUS_47K_UP |   \
 496                                 PAD_CTL_SPEED_MED |     \
 497                                 PAD_CTL_DSE_40ohm |     \
 498                                 PAD_CTL_SRE_FAST)
 499
 500 static const iomux_v3_cfg_t mmc0_pads[] = {
 501         MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 502         MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 503         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 504         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 505         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 506         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 507         /* SD1 CD */
 508         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 509 };
 510
 511 #ifdef CONFIG_TX6_EMMC
 512 static const iomux_v3_cfg_t mmc1_pads[] = {
 513         MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 514         MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 515         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 516         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 517         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 518         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
 519         /* eMMC RESET */
 520         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
 521                                                 PAD_CTL_DSE_40ohm),
 522 };
 523 #endif
 524
 525 static struct tx6_esdhc_cfg {
 526         const iomux_v3_cfg_t *pads;
 527         int num_pads;
 528         enum mxc_clock clkid;
 529         struct fsl_esdhc_cfg cfg;
 530         int cd_gpio;
 531 } tx6ul_esdhc_cfg[] = {
 532 #ifdef CONFIG_TX6_EMMC
 533         {
 534                 .pads = mmc1_pads,
 535                 .num_pads = ARRAY_SIZE(mmc1_pads),
 536                 .clkid = MXC_ESDHC2_CLK,
 537                 .cfg = {
 538                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
 539                         .max_bus_width = 4,
 540                 },
 541                 .cd_gpio = -EINVAL,
 542         },
 543 #endif
 544         {
 545                 .pads = mmc0_pads,
 546                 .num_pads = ARRAY_SIZE(mmc0_pads),
 547                 .clkid = MXC_ESDHC_CLK,
 548                 .cfg = {
 549                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
 550                         .max_bus_width = 4,
 551                 },
 552                 .cd_gpio = TX6UL_SD1_CD_GPIO,
 553         },
 554 };
 555
 556 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
 557 {
 558         return container_of(cfg, struct tx6_esdhc_cfg, cfg);
 559 }
 560
 561 int board_mmc_getcd(struct mmc *mmc)
 562 {
 563         struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
 564
 565         if (cfg->cd_gpio < 0)
 566                 return 1;
 567
 568         debug("SD card %d is %spresent (GPIO %d)\n",
 569                 cfg - tx6ul_esdhc_cfg,
 570                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
 571                 cfg->cd_gpio);
 572         return !gpio_get_value(cfg->cd_gpio);
 573 }
 574
 575 int board_mmc_init(bd_t *bis)
 576 {
 577         int i;
 578
 579         debug("%s@%d: \n", __func__, __LINE__);
 580
 581         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
 582                 struct mmc *mmc;
 583                 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
 584                 int ret;
 585
 586                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
 587                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
 588
 589                 if (cfg->cd_gpio >= 0) {
 590                         ret = gpio_request_one(cfg->cd_gpio,
 591                                         GPIOFLAG_INPUT, "MMC CD");
 592                         if (ret) {
 593                                 printf("Error %d requesting GPIO%d_%d\n",
 594                                         ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
 595                                 continue;
 596                         }
 597                 }
 598
 599                 debug("%s: Initializing MMC slot %d\n", __func__, i);
 600                 fsl_esdhc_initialize(bis, &cfg->cfg);
 601
 602                 mmc = find_mmc_device(i);
 603                 if (mmc == NULL)
 604                         continue;
 605                 if (board_mmc_getcd(mmc))
 606                         mmc_init(mmc);
 607         }
 608         return 0;
 609 }
 610 #endif /* CONFIG_CMD_MMC */
 611
 612 #ifdef CONFIG_FEC_MXC
 613
 614 #ifndef ETH_ALEN
 615 #define ETH_ALEN 6
 616 #endif
 617
 618 int board_eth_init(bd_t *bis)
 619 {
 620         int ret;
 621
 622         debug("%s@%d: \n", __func__, __LINE__);
 623
 624         /* delay at least 21ms for the PHY internal POR signal to deassert */
 625         udelay(22000);
 626
 627         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
 628                                         ARRAY_SIZE(tx6ul_enet1_pads));
 629
 630         /* Deassert RESET to the external phy */
 631         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
 632
 633         if (getenv("ethaddr")) {
 634                 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
 635                 if (ret) {
 636                         printf("failed to initialize FEC0: %d\n", ret);
 637                         return ret;
 638                 }
 639         }
 640         if (getenv("eth1addr")) {
 641                 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
 642                 if (ret) {
 643                         printf("failed to initialize FEC1: %d\n", ret);
 644                         return ret;
 645                 }
 646         }
 647         return 0;
 648 }
 649
 650 static void tx6_init_mac(void)
 651 {
 652         u8 mac[ETH_ALEN];
 653
 654         imx_get_mac_from_fuse(0, mac);
 655         if (!is_valid_ethaddr(mac)) {
 656                 printf("No valid MAC address programmed\n");
 657                 return;
 658         }
 659
 660         printf("MAC addr from fuse: %pM\n", mac);
 661         eth_setenv_enetaddr("ethaddr", mac);
 662
 663         imx_get_mac_from_fuse(1, mac);
 664         eth_setenv_enetaddr("eth1addr", mac);
 665 }
 666 #else
 667 static inline void tx6_init_mac(void)
 668 {
 669 }
 670 #endif /* CONFIG_FEC_MXC */
 671
 672 enum {
 673         LED_STATE_INIT = -1,
 674         LED_STATE_OFF,
 675         LED_STATE_ON,
 676 };
 677
 678 static inline int calc_blink_rate(void)
 679 {
 680         if (!tx6_temp_check_enabled)
 681                 return CONFIG_SYS_HZ;
 682
 683         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
 684                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
 685                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
 686 }
 687
 688 void show_activity(int arg)
 689 {
 690         static int led_state = LED_STATE_INIT;
 691         static int blink_rate;
 692         static ulong last;
 693
 694         if (led_state == LED_STATE_INIT) {
 695                 last = get_timer(0);
 696                 gpio_set_value(TX6UL_LED_GPIO, 1);
 697                 led_state = LED_STATE_ON;
 698                 blink_rate = calc_blink_rate();
 699         } else {
 700                 if (get_timer(last) > blink_rate) {
 701                         blink_rate = calc_blink_rate();
 702                         last = get_timer_masked();
 703                         if (led_state == LED_STATE_ON) {
 704                                 gpio_set_value(TX6UL_LED_GPIO, 0);
 705                         } else {
 706                                 gpio_set_value(TX6UL_LED_GPIO, 1);
 707                         }
 708                         led_state = 1 - led_state;
 709                 }
 710         }
 711 }
 712
 713 static const iomux_v3_cfg_t stk5_pads[] = {
 714         /* SW controlled LED on STK5 baseboard */
 715         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
 716
 717         /* I2C bus on DIMM pins 40/41 */
 718         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 719         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
 720
 721         /* TSC200x PEN IRQ */
 722         MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
 723 #if 0
 724         /* EDT-FT5x06 Polytouch panel */
 725         MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
 726         MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
 727         MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
 728
 729         /* USBH1 */
 730         MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
 731         MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
 732         /* USBOTG */
 733         MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
 734         MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
 735         MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
 736 #endif
 737 };
 738
 739 static const struct gpio stk5_gpios[] = {
 740         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
 741
 742         { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
 743         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
 744         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
 745         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
 746         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
 747 };
 748
 749 #ifdef CONFIG_LCD
 750 static u16 tx6_cmap[256];
 751 vidinfo_t panel_info = {
 752         /* set to max. size supported by SoC */
 753         .vl_col = 4096,
 754         .vl_row = 1024,
 755
 756         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
 757         .cmap = tx6_cmap,
 758 };
 759
 760 static struct fb_videomode tx6_fb_modes[] = {
 761 #ifndef CONFIG_SYS_LVDS_IF
 762         {
 763                 /* Standard VGA timing */
 764                 .name           = "VGA",
 765                 .refresh        = 60,
 766                 .xres           = 640,
 767                 .yres           = 480,
 768                 .pixclock       = KHZ2PICOS(25175),
 769                 .left_margin    = 48,
 770                 .hsync_len      = 96,
 771                 .right_margin   = 16,
 772                 .upper_margin   = 31,
 773                 .vsync_len      = 2,
 774                 .lower_margin   = 12,
 775                 .sync           = FB_SYNC_CLK_LAT_FALL,
 776         },
 777         {
 778                 /* Emerging ETV570 640 x 480 display. Syncs low active,
 779                  * DE high active, 115.2 mm x 86.4 mm display area
 780                  * VGA compatible timing
 781                  */
 782                 .name           = "ETV570",
 783                 .refresh        = 60,
 784                 .xres           = 640,
 785                 .yres           = 480,
 786                 .pixclock       = KHZ2PICOS(25175),
 787                 .left_margin    = 114,
 788                 .hsync_len      = 30,
 789                 .right_margin   = 16,
 790                 .upper_margin   = 32,
 791                 .vsync_len      = 3,
 792                 .lower_margin   = 10,
 793                 .sync           = FB_SYNC_CLK_LAT_FALL,
 794         },
 795         {
 796                 /* Emerging ET0350G0DH6 320 x 240 display.
 797                  * 70.08 mm x 52.56 mm display area.
 798                  */
 799                 .name           = "ET0350",
 800                 .refresh        = 60,
 801                 .xres           = 320,
 802                 .yres           = 240,
 803                 .pixclock       = KHZ2PICOS(6500),
 804                 .left_margin    = 68 - 34,
 805                 .hsync_len      = 34,
 806                 .right_margin   = 20,
 807                 .upper_margin   = 18 - 3,
 808                 .vsync_len      = 3,
 809                 .lower_margin   = 4,
 810                 .sync           = FB_SYNC_CLK_LAT_FALL,
 811         },
 812         {
 813                 /* Emerging ET0430G0DH6 480 x 272 display.
 814                  * 95.04 mm x 53.856 mm display area.
 815                  */
 816                 .name           = "ET0430",
 817                 .refresh        = 60,
 818                 .xres           = 480,
 819                 .yres           = 272,
 820                 .pixclock       = KHZ2PICOS(9000),
 821                 .left_margin    = 2,
 822                 .hsync_len      = 41,
 823                 .right_margin   = 2,
 824                 .upper_margin   = 2,
 825                 .vsync_len      = 10,
 826                 .lower_margin   = 2,
 827         },
 828         {
 829                 /* Emerging ET0500G0DH6 800 x 480 display.
 830                  * 109.6 mm x 66.4 mm display area.
 831                  */
 832                 .name           = "ET0500",
 833                 .refresh        = 60,
 834                 .xres           = 800,
 835                 .yres           = 480,
 836                 .pixclock       = KHZ2PICOS(33260),
 837                 .left_margin    = 216 - 128,
 838                 .hsync_len      = 128,
 839                 .right_margin   = 1056 - 800 - 216,
 840                 .upper_margin   = 35 - 2,
 841                 .vsync_len      = 2,
 842                 .lower_margin   = 525 - 480 - 35,
 843                 .sync           = FB_SYNC_CLK_LAT_FALL,
 844         },
 845         {
 846                 /* Emerging ETQ570G0DH6 320 x 240 display.
 847                  * 115.2 mm x 86.4 mm display area.
 848                  */
 849                 .name           = "ETQ570",
 850                 .refresh        = 60,
 851                 .xres           = 320,
 852                 .yres           = 240,
 853                 .pixclock       = KHZ2PICOS(6400),
 854                 .left_margin    = 38,
 855                 .hsync_len      = 30,
 856                 .right_margin   = 30,
 857                 .upper_margin   = 16, /* 15 according to datasheet */
 858                 .vsync_len      = 3, /* TVP -> 1>x>5 */
 859                 .lower_margin   = 4, /* 4.5 according to datasheet */
 860                 .sync           = FB_SYNC_CLK_LAT_FALL,
 861         },
 862         {
 863                 /* Emerging ET0700G0DH6 800 x 480 display.
 864                  * 152.4 mm x 91.44 mm display area.
 865                  */
 866                 .name           = "ET0700",
 867                 .refresh        = 60,
 868                 .xres           = 800,
 869                 .yres           = 480,
 870                 .pixclock       = KHZ2PICOS(33260),
 871                 .left_margin    = 216 - 128,
 872                 .hsync_len      = 128,
 873                 .right_margin   = 1056 - 800 - 216,
 874                 .upper_margin   = 35 - 2,
 875                 .vsync_len      = 2,
 876                 .lower_margin   = 525 - 480 - 35,
 877                 .sync           = FB_SYNC_CLK_LAT_FALL,
 878         },
 879         {
 880                 /* Emerging ET070001DM6 800 x 480 display.
 881                  * 152.4 mm x 91.44 mm display area.
 882                  */
 883                 .name           = "ET070001DM6",
 884                 .refresh        = 60,
 885                 .xres           = 800,
 886                 .yres           = 480,
 887                 .pixclock       = KHZ2PICOS(33260),
 888                 .left_margin    = 216 - 128,
 889                 .hsync_len      = 128,
 890                 .right_margin   = 1056 - 800 - 216,
 891                 .upper_margin   = 35 - 2,
 892                 .vsync_len      = 2,
 893                 .lower_margin   = 525 - 480 - 35,
 894                 .sync           = 0,
 895         },
 896 #else
 897         {
 898                 /* HannStar HSD100PXN1
 899                  * 202.7m mm x 152.06 mm display area.
 900                  */
 901                 .name           = "HSD100PXN1",
 902                 .refresh        = 60,
 903                 .xres           = 1024,
 904                 .yres           = 768,
 905                 .pixclock       = KHZ2PICOS(65000),
 906                 .left_margin    = 0,
 907                 .hsync_len      = 0,
 908                 .right_margin   = 320,
 909                 .upper_margin   = 0,
 910                 .vsync_len      = 0,
 911                 .lower_margin   = 38,
 912                 .sync           = FB_SYNC_CLK_LAT_FALL,
 913         },
 914 #endif
 915         {
 916                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
 917                 .refresh        = 60,
 918                 .left_margin    = 48,
 919                 .hsync_len      = 96,
 920                 .right_margin   = 16,
 921                 .upper_margin   = 31,
 922                 .vsync_len      = 2,
 923                 .lower_margin   = 12,
 924                 .sync           = FB_SYNC_CLK_LAT_FALL,
 925         },
 926 };
 927
 928 static int lcd_enabled = 1;
 929 static int lcd_bl_polarity;
 930
 931 static int lcd_backlight_polarity(void)
 932 {
 933         return lcd_bl_polarity;
 934 }
 935
 936 void lcd_enable(void)
 937 {
 938         /* HACK ALERT:
 939          * global variable from common/lcd.c
 940          * Set to 0 here to prevent messages from going to LCD
 941          * rather than serial console
 942          */
 943         lcd_is_enabled = 0;
 944
 945         if (lcd_enabled) {
 946                 karo_load_splashimage(1);
 947
 948                 debug("Switching LCD on\n");
 949                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
 950                 udelay(100);
 951                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
 952                 udelay(300000);
 953                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
 954                         lcd_backlight_polarity());
 955         }
 956 }
 957
 958 void lcd_disable(void)
 959 {
 960         if (lcd_enabled) {
 961                 printf("Disabling LCD\n");
 962                 panel_info.vl_row = 0;
 963                 lcd_enabled = 0;
 964         }
 965 }
 966
 967 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
 968 #if 1
 969         /* LCD RESET */
 970         MX6_PAD_LCD_RESET__LCDIF_RESET,
 971         /* LCD POWER_ENABLE */
 972         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 973         /* LCD Backlight (PWM) */
 974         MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
 975 #endif
 976 #ifdef CONFIG_LCD
 977         /* Display */
 978         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
 979         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
 980         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
 981         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
 982         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
 983         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
 984         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
 985         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
 986         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
 987         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
 988         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
 989         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
 990         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
 991         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
 992         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
 993         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
 994         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
 995         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
 996         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
 997         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
 998         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
 999         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1000         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1001         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1002         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1003         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1004         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1005         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1006 #endif
1007 };
1008
1009 static const struct gpio stk5_lcd_gpios[] = {
1010         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1011         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1012         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1013 };
1014
1015 void lcd_ctrl_init(void *lcdbase)
1016 {
1017         int color_depth = 24;
1018         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1019         const char *vm;
1020         unsigned long val;
1021         int refresh = 60;
1022         struct fb_videomode *p = &tx6_fb_modes[0];
1023         struct fb_videomode fb_mode;
1024         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1025
1026         if (!lcd_enabled) {
1027                 debug("LCD disabled\n");
1028                 return;
1029         }
1030
1031         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1032                 lcd_disable();
1033                 setenv("splashimage", NULL);
1034                 return;
1035         }
1036
1037         karo_fdt_move_fdt();
1038         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1039
1040         if (video_mode == NULL) {
1041                 lcd_disable();
1042                 return;
1043         }
1044         vm = video_mode;
1045         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1046                 p = &fb_mode;
1047                 debug("Using video mode from FDT\n");
1048                 vm += strlen(vm);
1049                 if (fb_mode.xres > panel_info.vl_col ||
1050                         fb_mode.yres > panel_info.vl_row) {
1051                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1052                                 fb_mode.xres, fb_mode.yres,
1053                                 panel_info.vl_col, panel_info.vl_row);
1054                         lcd_enabled = 0;
1055                         return;
1056                 }
1057         }
1058         if (p->name != NULL)
1059                 debug("Trying compiled-in video modes\n");
1060         while (p->name != NULL) {
1061                 if (strcmp(p->name, vm) == 0) {
1062                         debug("Using video mode: '%s'\n", p->name);
1063                         vm += strlen(vm);
1064                         break;
1065                 }
1066                 p++;
1067         }
1068         if (*vm != '\0')
1069                 debug("Trying to decode video_mode: '%s'\n", vm);
1070         while (*vm != '\0') {
1071                 if (*vm >= '0' && *vm <= '9') {
1072                         char *end;
1073
1074                         val = simple_strtoul(vm, &end, 0);
1075                         if (end > vm) {
1076                                 if (!xres_set) {
1077                                         if (val > panel_info.vl_col)
1078                                                 val = panel_info.vl_col;
1079                                         p->xres = val;
1080                                         panel_info.vl_col = val;
1081                                         xres_set = 1;
1082                                 } else if (!yres_set) {
1083                                         if (val > panel_info.vl_row)
1084                                                 val = panel_info.vl_row;
1085                                         p->yres = val;
1086                                         panel_info.vl_row = val;
1087                                         yres_set = 1;
1088                                 } else if (!bpp_set) {
1089                                         switch (val) {
1090                                         case 8:
1091                                         case 16:
1092                                         case 18:
1093                                         case 24:
1094                                         case 32:
1095                                                 color_depth = val;
1096                                                 break;
1097
1098                                         default:
1099                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1100                                                         end - vm, vm, color_depth);
1101                                         }
1102                                         bpp_set = 1;
1103                                 } else if (!refresh_set) {
1104                                         refresh = val;
1105                                         refresh_set = 1;
1106                                 }
1107                         }
1108                         vm = end;
1109                 }
1110                 switch (*vm) {
1111                 case '@':
1112                         bpp_set = 1;
1113                         /* fallthru */
1114                 case '-':
1115                         yres_set = 1;
1116                         /* fallthru */
1117                 case 'x':
1118                         xres_set = 1;
1119                         /* fallthru */
1120                 case 'M':
1121                 case 'R':
1122                         vm++;
1123                         break;
1124
1125                 default:
1126                         if (*vm != '\0')
1127                                 vm++;
1128                 }
1129         }
1130         if (p->xres == 0 || p->yres == 0) {
1131                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1132                 lcd_enabled = 0;
1133                 printf("Supported video modes are:");
1134                 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1135                         printf(" %s", p->name);
1136                 }
1137                 printf("\n");
1138                 return;
1139         }
1140         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1141                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1142                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1143                 lcd_enabled = 0;
1144                 return;
1145         }
1146         panel_info.vl_col = p->xres;
1147         panel_info.vl_row = p->yres;
1148
1149         switch (color_depth) {
1150         case 8:
1151                 panel_info.vl_bpix = LCD_COLOR8;
1152                 break;
1153         case 16:
1154                 panel_info.vl_bpix = LCD_COLOR16;
1155                 break;
1156         default:
1157                 panel_info.vl_bpix = LCD_COLOR32;
1158         }
1159
1160         p->pixclock = KHZ2PICOS(refresh *
1161                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1162                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1163                                 1000);
1164         debug("Pixel clock set to %lu.%03lu MHz\n",
1165                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1166
1167         if (p != &fb_mode) {
1168                 int ret;
1169
1170                 debug("Creating new display-timing node from '%s'\n",
1171                         video_mode);
1172                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1173                 if (ret)
1174                         printf("Failed to create new display-timing node from '%s': %d\n",
1175                                 video_mode, ret);
1176         }
1177
1178         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1179         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1180                                         ARRAY_SIZE(stk5_lcd_pads));
1181
1182         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1183                 color_depth, refresh);
1184
1185         if (karo_load_splashimage(0) == 0) {
1186                 char vmode[128];
1187
1188                 /* setup env variable for mxsfb display driver */
1189                 snprintf(vmode, sizeof(vmode),
1190                         "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1191                         p->xres, p->yres, p->left_margin, p->right_margin,
1192                         p->upper_margin, p->lower_margin, p->hsync_len,
1193                         p->vsync_len, p->sync, p->pixclock, color_depth);
1194                 setenv("videomode", vmode);
1195
1196                 debug("Initializing LCD controller\n");
1197                 lcdif_clk_enable();
1198                 video_hw_init();
1199                 setenv("videomode", NULL);
1200         } else {
1201                 debug("Skipping initialization of LCD controller\n");
1202         }
1203 }
1204 #else
1205 #define lcd_enabled 0
1206 #endif /* CONFIG_LCD */
1207
1208 static void stk5_board_init(void)
1209 {
1210         int ret;
1211
1212         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1213         if (ret < 0) {
1214                 printf("Failed to request stk5_gpios: %d\n", ret);
1215                 return;
1216         }
1217         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1218 debug("%s@%d: \n", __func__, __LINE__);
1219 }
1220
1221 static void stk5v3_board_init(void)
1222 {
1223 debug("%s@%d: \n", __func__, __LINE__);
1224         stk5_board_init();
1225 debug("%s@%d: \n", __func__, __LINE__);
1226 }
1227
1228 static void stk5v5_board_init(void)
1229 {
1230         int ret;
1231
1232         stk5_board_init();
1233
1234         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1235                         "Flexcan Transceiver");
1236         if (ret) {
1237                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1238                 return;
1239         }
1240
1241         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1242                         MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1243 }
1244
1245 static void tx6ul_set_cpu_clock(void)
1246 {
1247         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1248
1249         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1250                 return;
1251
1252         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1253                 printf("%s detected; skipping cpu clock change\n",
1254                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1255                 return;
1256         }
1257         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1258                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1259                 printf("CPU clock set to %lu.%03lu MHz\n",
1260                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1261         } else {
1262                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1263         }
1264 }
1265
1266 int board_late_init(void)
1267 {
1268         int ret = 0;
1269         const char *baseboard;
1270
1271         debug("%s@%d: \n", __func__, __LINE__);
1272
1273         env_cleanup();
1274
1275         if (tx6_temp_check_enabled)
1276                 check_cpu_temperature(1);
1277
1278         tx6ul_set_cpu_clock();
1279
1280         if (had_ctrlc())
1281                 setenv_ulong("safeboot", 1);
1282         else if (wrsr & WRSR_TOUT)
1283                 setenv_ulong("wdreset", 1);
1284         else
1285                 karo_fdt_move_fdt();
1286
1287         baseboard = getenv("baseboard");
1288         if (!baseboard)
1289                 goto exit;
1290
1291         printf("Baseboard: %s\n", baseboard);
1292
1293         if (strncmp(baseboard, "stk5", 4) == 0) {
1294                 if ((strlen(baseboard) == 4) ||
1295                         strcmp(baseboard, "stk5-v3") == 0) {
1296                         stk5v3_board_init();
1297                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1298                         const char *otg_mode = getenv("otg_mode");
1299
1300                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1301                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1302                                         otg_mode, baseboard);
1303                                 setenv("otg_mode", "none");
1304                         }
1305                         stk5v5_board_init();
1306                 } else {
1307                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1308                                 baseboard + 4);
1309                 }
1310         } else {
1311                 printf("WARNING: Unsupported baseboard: '%s'\n",
1312                         baseboard);
1313                 ret = -EINVAL;
1314         }
1315
1316 exit:
1317 debug("%s@%d: \n", __func__, __LINE__);
1318         tx6_init_mac();
1319 debug("%s@%d: \n", __func__, __LINE__);
1320
1321         clear_ctrlc();
1322         return ret;
1323 }
1324
1325 #ifdef CONFIG_SERIAL_TAG
1326 void get_board_serial(struct tag_serialnr *serialnr)
1327 {
1328         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1329         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1330
1331         serialnr->low = readl(&fuse->cfg0);
1332         serialnr->high = readl(&fuse->cfg1);
1333 }
1334 #endif
1335
1336 #if defined(CONFIG_OF_BOARD_SETUP)
1337 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1338 #include <jffs2/jffs2.h>
1339 #include <mtd_node.h>
1340 static struct node_info nodes[] = {
1341         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1342 };
1343 #else
1344 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1345 #endif
1346
1347 static const char *tx6_touchpanels[] = {
1348         "ti,tsc2007",
1349         "edt,edt-ft5x06",
1350         "eeti,egalax_ts",
1351 };
1352
1353 int ft_board_setup(void *blob, bd_t *bd)
1354 {
1355         const char *baseboard = getenv("baseboard");
1356         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1357         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1358         int ret;
1359
1360         ret = fdt_increase_size(blob, 4096);
1361         if (ret) {
1362                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1363                 return ret;
1364         }
1365         if (stk5_v5)
1366                 karo_fdt_enable_node(blob, "stk5led", 0);
1367
1368         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1369
1370         karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1371                                 ARRAY_SIZE(tx6_touchpanels));
1372         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1373         karo_fdt_fixup_flexcan(blob, stk5_v5);
1374
1375         karo_fdt_update_fb_mode(blob, video_mode);
1376
1377         return 0;
1378 }
1379 #endif /* CONFIG_OF_BOARD_SETUP */