2 * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
37 #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
39 #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
40 #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
41 #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
43 #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
44 #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
46 #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
49 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
51 #define TEMPERATURE_MIN (-40)
53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
54 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
56 #define TEMPERATURE_HOT 80
59 DECLARE_GLOBAL_DATA_PTR;
61 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
64 #ifdef CONFIG_SECURE_BOOT
65 char __csf_data[0] __attribute__((section(".__csf_data")));
68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
70 #if CONFIG_MXC_UART_BASE == UART1_BASE
71 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
72 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
73 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
74 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
76 #if CONFIG_MXC_UART_BASE == UART2_BASE
77 MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
78 MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
79 MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
80 MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
82 #if CONFIG_MXC_UART_BASE == UART5_BASE
83 MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
84 MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
85 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
86 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
89 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
90 MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
91 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
92 MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
93 PAD_CTL_ODE), /* I2C SDA */
95 /* FEC PHY GPIO functions */
96 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
97 MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
98 MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
99 PAD_CTL_DSE_40ohm), /* PHY INT */
102 #define TX6_ENET_PAD_CTRL (PAD_CTL_SPEED_HIGH | \
103 PAD_CTL_DSE_48ohm | \
104 PAD_CTL_PUS_100K_UP | \
106 #define TX6_GPIO_OUT_PAD_CTRL (PAD_CTL_SPEED_LOW | \
107 PAD_CTL_DSE_60ohm | \
109 #define TX6_GPIO_IN_PAD_CTRL (PAD_CTL_SPEED_LOW | \
112 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
114 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
116 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
119 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
120 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
123 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
124 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
125 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
126 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
127 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
128 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
129 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
131 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
132 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
135 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
136 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
137 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
138 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
139 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
140 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
141 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
144 #define TX6_I2C_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
145 PAD_CTL_SPEED_MED | \
146 PAD_CTL_DSE_34ohm | \
149 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
151 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
152 MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
153 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
154 MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
157 static const struct gpio const tx6ul_gpios[] = {
158 /* These two entries are used to forcefully reinitialize the I2C bus */
159 { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
160 { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
162 { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
163 { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
164 { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
171 static void tx6_i2c_recover(void)
175 #define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
176 #define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
177 #define I2C_GPIO_BASE (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
179 if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
180 (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
183 debug("Clearing I2C bus\n");
184 if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
185 printf("I2C SCL stuck LOW\n");
188 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
189 I2C_GPIO_BASE + GPIO_DR);
190 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
191 I2C_GPIO_BASE + GPIO_DIR);
193 if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
194 printf("I2C SDA stuck LOW\n");
197 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
198 I2C_GPIO_BASE + GPIO_DIR);
199 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
200 I2C_GPIO_BASE + GPIO_DR);
201 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
202 I2C_GPIO_BASE + GPIO_DIR);
204 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
205 ARRAY_SIZE(tx6_i2c_gpio_pads));
208 for (i = 0; i < 18; i++) {
209 u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
211 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
212 writel(reg, I2C_GPIO_BASE + GPIO_DR);
215 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
220 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
222 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
223 printf("I2C bus recovery succeeded\n");
225 printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
231 /* placed in section '.data' to prevent overwriting relocation info
234 static u32 wrsr __data;
236 #define WRSR_POR (1 << 4)
237 #define WRSR_TOUT (1 << 1)
238 #define WRSR_SFTW (1 << 0)
240 static void print_reset_cause(void)
242 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
243 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
247 printf("Reset cause: ");
249 srsr = readl(&src_regs->srsr);
250 wrsr = readw(wdt_base + 4);
252 if (wrsr & WRSR_POR) {
253 printf("%sPOR", dlm);
256 if (srsr & 0x00004) {
257 printf("%sCSU", dlm);
260 if (srsr & 0x00008) {
261 printf("%sIPP USER", dlm);
264 if (srsr & 0x00010) {
265 if (wrsr & WRSR_SFTW) {
266 printf("%sSOFT", dlm);
269 if (wrsr & WRSR_TOUT) {
270 printf("%sWDOG", dlm);
274 if (srsr & 0x00020) {
275 printf("%sJTAG HIGH-Z", dlm);
278 if (srsr & 0x00040) {
279 printf("%sJTAG SW", dlm);
282 if (srsr & 0x10000) {
283 printf("%sWARM BOOT", dlm);
292 #ifdef CONFIG_IMX6_THERMAL
294 #include <imx_thermal.h>
297 static void print_temperature(void)
299 struct udevice *thermal_dev;
300 int cpu_tmp, minc, maxc, ret;
301 char const *grade_str;
302 static u32 __data thermal_calib;
304 puts("Temperature: ");
305 switch (get_cpu_temp_grade(&minc, &maxc)) {
306 case TEMP_AUTOMOTIVE:
307 grade_str = "Automotive";
309 case TEMP_INDUSTRIAL:
310 grade_str = "Industrial";
312 case TEMP_EXTCOMMERCIAL:
313 grade_str = "Extended Commercial";
316 grade_str = "Commercial";
318 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
319 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
321 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
324 printf(" at %dC", cpu_tmp);
326 puts(" - failed to read sensor data");
328 puts(" - no sensor device found");
331 if (fuse_read(1, 6, &thermal_calib) == 0) {
332 printf(" - calibration data 0x%08x\n", thermal_calib);
334 puts(" - Failed to read thermal calib fuse\n");
338 static inline void print_temperature(void)
345 u32 cpurev = get_cpu_rev();
348 switch ((cpurev >> 12) & 0xff) {
355 case MXC_CPU_MX6SOLO:
366 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
368 (cpurev & 0x000F0) >> 4,
369 (cpurev & 0x0000F) >> 0,
370 mxc_get_clock(MXC_ARM_CLK) / 1000000);
374 #ifdef CONFIG_MX6_TEMPERATURE_HOT
375 check_cpu_temperature(1);
381 /* serial port not initialized at this point */
382 int board_early_init_f(void)
387 #ifndef CONFIG_MX6_TEMPERATURE_HOT
388 static bool tx6_temp_check_enabled = true;
390 #define tx6_temp_check_enabled 0
393 static inline u8 tx6ul_mem_suffix(void)
395 #ifdef CONFIG_TX6_NAND
403 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
404 #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
405 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
406 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
407 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
408 #define VDD_HIGH_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
409 #define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3300)
410 #define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */
411 #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300)
413 static struct pmic_regs rn5t567_regs[] = {
414 { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
415 { RN5T567_DC2CTL, DC2_DC2DIS, },
416 { RN5T567_DC1DAC, VDD_CORE_VAL, },
417 { RN5T567_DC3DAC, VDD_DDR_VAL, },
418 { RN5T567_DC4DAC, VDD_HIGH_VAL, },
419 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
420 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
421 { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
422 { RN5T567_LDOEN1, 0x01f, ~0x1f, },
423 { RN5T567_LDOEN2, 0x10, ~0x30, },
424 { RN5T567_LDODIS, 0x00, },
425 { RN5T567_LDO4DAC, VDD_CSI_VAL, },
426 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
427 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
430 static int pmic_addr __maybe_unused = 0x33;
436 debug("%s@%d: \n", __func__, __LINE__);
438 printf("Board: Ka-Ro TXUL-001%c\n",
443 ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
445 printf("Failed to request tx6ul_gpios: %d\n", ret);
447 imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
449 /* Address of boot parameters */
450 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
451 gd->bd->bi_arch_number = -1;
453 if (ctrlc() || (wrsr & WRSR_TOUT)) {
454 if (wrsr & WRSR_TOUT)
455 printf("WDOG RESET detected; Skipping PMIC setup\n");
457 printf("<CTRL-C> detected; safeboot enabled\n");
458 #ifndef CONFIG_MX6_TEMPERATURE_HOT
459 tx6_temp_check_enabled = false;
464 ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
466 printf("Failed to setup PMIC voltages: %d\n", ret);
474 debug("%s@%d: \n", __func__, __LINE__);
476 /* dram_init must store complete ramsize in gd->ram_size */
477 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
478 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
482 void dram_init_banksize(void)
484 debug("%s@%d: \n", __func__, __LINE__);
486 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
487 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
489 #if CONFIG_NR_DRAM_BANKS > 1
490 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
491 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
496 #ifdef CONFIG_FSL_ESDHC
497 #define TX6_SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
498 PAD_CTL_SPEED_MED | \
499 PAD_CTL_DSE_40ohm | \
502 static const iomux_v3_cfg_t mmc0_pads[] = {
503 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
504 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
505 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
506 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
507 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
508 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
510 MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
513 #ifdef CONFIG_TX6_EMMC
514 static const iomux_v3_cfg_t mmc1_pads[] = {
515 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
516 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
517 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
518 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
519 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
520 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
522 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
527 static struct tx6_esdhc_cfg {
528 const iomux_v3_cfg_t *pads;
530 enum mxc_clock clkid;
531 struct fsl_esdhc_cfg cfg;
533 } tx6ul_esdhc_cfg[] = {
534 #ifdef CONFIG_TX6_EMMC
537 .num_pads = ARRAY_SIZE(mmc1_pads),
538 .clkid = MXC_ESDHC2_CLK,
540 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
548 .num_pads = ARRAY_SIZE(mmc0_pads),
549 .clkid = MXC_ESDHC_CLK,
551 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
554 .cd_gpio = TX6UL_SD1_CD_GPIO,
558 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
560 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
563 int board_mmc_getcd(struct mmc *mmc)
565 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
567 if (cfg->cd_gpio < 0)
570 debug("SD card %d is %spresent (GPIO %d)\n",
571 cfg - tx6ul_esdhc_cfg,
572 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
574 return !gpio_get_value(cfg->cd_gpio);
577 int board_mmc_init(bd_t *bis)
581 debug("%s@%d: \n", __func__, __LINE__);
583 for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
585 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
588 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
589 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
591 if (cfg->cd_gpio >= 0) {
592 ret = gpio_request_one(cfg->cd_gpio,
593 GPIOFLAG_INPUT, "MMC CD");
595 printf("Error %d requesting GPIO%d_%d\n",
596 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
601 debug("%s: Initializing MMC slot %d\n", __func__, i);
602 fsl_esdhc_initialize(bis, &cfg->cfg);
604 mmc = find_mmc_device(i);
607 if (board_mmc_getcd(mmc))
612 #endif /* CONFIG_CMD_MMC */
614 #ifdef CONFIG_FEC_MXC
620 int board_eth_init(bd_t *bis)
624 debug("%s@%d: \n", __func__, __LINE__);
626 /* delay at least 21ms for the PHY internal POR signal to deassert */
629 imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
630 ARRAY_SIZE(tx6ul_enet1_pads));
632 /* Deassert RESET to the external phy */
633 gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
635 if (getenv("ethaddr")) {
636 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
638 printf("failed to initialize FEC0: %d\n", ret);
642 if (getenv("eth1addr")) {
643 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
645 printf("failed to initialize FEC1: %d\n", ret);
652 static void tx6_init_mac(void)
656 imx_get_mac_from_fuse(0, mac);
657 if (!is_valid_ethaddr(mac)) {
658 printf("No valid MAC address programmed\n");
662 printf("MAC addr from fuse: %pM\n", mac);
663 eth_setenv_enetaddr("ethaddr", mac);
665 imx_get_mac_from_fuse(1, mac);
666 eth_setenv_enetaddr("eth1addr", mac);
669 static inline void tx6_init_mac(void)
672 #endif /* CONFIG_FEC_MXC */
680 static inline int calc_blink_rate(void)
682 if (!tx6_temp_check_enabled)
683 return CONFIG_SYS_HZ;
685 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
686 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
687 (TEMPERATURE_HOT - TEMPERATURE_MIN);
690 void show_activity(int arg)
692 static int led_state = LED_STATE_INIT;
693 static int blink_rate;
696 if (led_state == LED_STATE_INIT) {
698 gpio_set_value(TX6UL_LED_GPIO, 1);
699 led_state = LED_STATE_ON;
700 blink_rate = calc_blink_rate();
702 if (get_timer(last) > blink_rate) {
703 blink_rate = calc_blink_rate();
704 last = get_timer_masked();
705 if (led_state == LED_STATE_ON) {
706 gpio_set_value(TX6UL_LED_GPIO, 0);
708 gpio_set_value(TX6UL_LED_GPIO, 1);
710 led_state = 1 - led_state;
715 static const iomux_v3_cfg_t stk5_pads[] = {
716 /* SW controlled LED on STK5 baseboard */
717 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
719 /* I2C bus on DIMM pins 40/41 */
720 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
721 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
723 /* TSC200x PEN IRQ */
724 MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
726 /* EDT-FT5x06 Polytouch panel */
727 MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
728 MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
729 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
732 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
733 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
735 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
736 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
737 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
741 static const struct gpio stk5_gpios[] = {
742 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
744 { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
745 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
746 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
747 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
748 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
752 static u16 tx6_cmap[256];
753 vidinfo_t panel_info = {
754 /* set to max. size supported by SoC */
758 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
762 static struct fb_videomode tx6_fb_modes[] = {
763 #ifndef CONFIG_SYS_LVDS_IF
765 /* Standard VGA timing */
770 .pixclock = KHZ2PICOS(25175),
777 .sync = FB_SYNC_CLK_LAT_FALL,
780 /* Emerging ETV570 640 x 480 display. Syncs low active,
781 * DE high active, 115.2 mm x 86.4 mm display area
782 * VGA compatible timing
788 .pixclock = KHZ2PICOS(25175),
795 .sync = FB_SYNC_CLK_LAT_FALL,
798 /* Emerging ET0350G0DH6 320 x 240 display.
799 * 70.08 mm x 52.56 mm display area.
805 .pixclock = KHZ2PICOS(6500),
806 .left_margin = 68 - 34,
809 .upper_margin = 18 - 3,
812 .sync = FB_SYNC_CLK_LAT_FALL,
815 /* Emerging ET0430G0DH6 480 x 272 display.
816 * 95.04 mm x 53.856 mm display area.
822 .pixclock = KHZ2PICOS(9000),
831 /* Emerging ET0500G0DH6 800 x 480 display.
832 * 109.6 mm x 66.4 mm display area.
838 .pixclock = KHZ2PICOS(33260),
839 .left_margin = 216 - 128,
841 .right_margin = 1056 - 800 - 216,
842 .upper_margin = 35 - 2,
844 .lower_margin = 525 - 480 - 35,
845 .sync = FB_SYNC_CLK_LAT_FALL,
848 /* Emerging ETQ570G0DH6 320 x 240 display.
849 * 115.2 mm x 86.4 mm display area.
855 .pixclock = KHZ2PICOS(6400),
859 .upper_margin = 16, /* 15 according to datasheet */
860 .vsync_len = 3, /* TVP -> 1>x>5 */
861 .lower_margin = 4, /* 4.5 according to datasheet */
862 .sync = FB_SYNC_CLK_LAT_FALL,
865 /* Emerging ET0700G0DH6 800 x 480 display.
866 * 152.4 mm x 91.44 mm display area.
872 .pixclock = KHZ2PICOS(33260),
873 .left_margin = 216 - 128,
875 .right_margin = 1056 - 800 - 216,
876 .upper_margin = 35 - 2,
878 .lower_margin = 525 - 480 - 35,
879 .sync = FB_SYNC_CLK_LAT_FALL,
882 /* Emerging ET070001DM6 800 x 480 display.
883 * 152.4 mm x 91.44 mm display area.
885 .name = "ET070001DM6",
889 .pixclock = KHZ2PICOS(33260),
890 .left_margin = 216 - 128,
892 .right_margin = 1056 - 800 - 216,
893 .upper_margin = 35 - 2,
895 .lower_margin = 525 - 480 - 35,
900 /* HannStar HSD100PXN1
901 * 202.7m mm x 152.06 mm display area.
903 .name = "HSD100PXN1",
907 .pixclock = KHZ2PICOS(65000),
914 .sync = FB_SYNC_CLK_LAT_FALL,
918 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
926 .sync = FB_SYNC_CLK_LAT_FALL,
930 static int lcd_enabled = 1;
931 static int lcd_bl_polarity;
933 static int lcd_backlight_polarity(void)
935 return lcd_bl_polarity;
938 void lcd_enable(void)
941 * global variable from common/lcd.c
942 * Set to 0 here to prevent messages from going to LCD
943 * rather than serial console
948 karo_load_splashimage(1);
950 debug("Switching LCD on\n");
951 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
953 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
955 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
956 lcd_backlight_polarity());
960 void lcd_disable(void)
963 printf("Disabling LCD\n");
964 panel_info.vl_row = 0;
969 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
972 MX6_PAD_LCD_RESET__LCDIF_RESET,
973 /* LCD POWER_ENABLE */
974 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
975 /* LCD Backlight (PWM) */
976 MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
980 MX6_PAD_LCD_DATA00__LCDIF_DATA00,
981 MX6_PAD_LCD_DATA01__LCDIF_DATA01,
982 MX6_PAD_LCD_DATA02__LCDIF_DATA02,
983 MX6_PAD_LCD_DATA03__LCDIF_DATA03,
984 MX6_PAD_LCD_DATA04__LCDIF_DATA04,
985 MX6_PAD_LCD_DATA05__LCDIF_DATA05,
986 MX6_PAD_LCD_DATA06__LCDIF_DATA06,
987 MX6_PAD_LCD_DATA07__LCDIF_DATA07,
988 MX6_PAD_LCD_DATA08__LCDIF_DATA08,
989 MX6_PAD_LCD_DATA09__LCDIF_DATA09,
990 MX6_PAD_LCD_DATA10__LCDIF_DATA10,
991 MX6_PAD_LCD_DATA11__LCDIF_DATA11,
992 MX6_PAD_LCD_DATA12__LCDIF_DATA12,
993 MX6_PAD_LCD_DATA13__LCDIF_DATA13,
994 MX6_PAD_LCD_DATA14__LCDIF_DATA14,
995 MX6_PAD_LCD_DATA15__LCDIF_DATA15,
996 MX6_PAD_LCD_DATA16__LCDIF_DATA16,
997 MX6_PAD_LCD_DATA17__LCDIF_DATA17,
998 MX6_PAD_LCD_DATA18__LCDIF_DATA18,
999 MX6_PAD_LCD_DATA19__LCDIF_DATA19,
1000 MX6_PAD_LCD_DATA20__LCDIF_DATA20,
1001 MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1002 MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1003 MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1004 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1005 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1006 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1007 MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1011 static const struct gpio stk5_lcd_gpios[] = {
1012 { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1013 { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1014 { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1017 void lcd_ctrl_init(void *lcdbase)
1019 int color_depth = 24;
1020 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1024 struct fb_videomode *p = &tx6_fb_modes[0];
1025 struct fb_videomode fb_mode;
1026 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1029 debug("LCD disabled\n");
1033 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1035 setenv("splashimage", NULL);
1039 karo_fdt_move_fdt();
1040 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1042 if (video_mode == NULL) {
1047 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1049 debug("Using video mode from FDT\n");
1051 if (fb_mode.xres > panel_info.vl_col ||
1052 fb_mode.yres > panel_info.vl_row) {
1053 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1054 fb_mode.xres, fb_mode.yres,
1055 panel_info.vl_col, panel_info.vl_row);
1060 if (p->name != NULL)
1061 debug("Trying compiled-in video modes\n");
1062 while (p->name != NULL) {
1063 if (strcmp(p->name, vm) == 0) {
1064 debug("Using video mode: '%s'\n", p->name);
1071 debug("Trying to decode video_mode: '%s'\n", vm);
1072 while (*vm != '\0') {
1073 if (*vm >= '0' && *vm <= '9') {
1076 val = simple_strtoul(vm, &end, 0);
1079 if (val > panel_info.vl_col)
1080 val = panel_info.vl_col;
1082 panel_info.vl_col = val;
1084 } else if (!yres_set) {
1085 if (val > panel_info.vl_row)
1086 val = panel_info.vl_row;
1088 panel_info.vl_row = val;
1090 } else if (!bpp_set) {
1101 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1102 end - vm, vm, color_depth);
1105 } else if (!refresh_set) {
1132 if (p->xres == 0 || p->yres == 0) {
1133 printf("Invalid video mode: %s\n", getenv("video_mode"));
1135 printf("Supported video modes are:");
1136 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1137 printf(" %s", p->name);
1142 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1143 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1144 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1148 panel_info.vl_col = p->xres;
1149 panel_info.vl_row = p->yres;
1151 switch (color_depth) {
1153 panel_info.vl_bpix = LCD_COLOR8;
1156 panel_info.vl_bpix = LCD_COLOR16;
1159 panel_info.vl_bpix = LCD_COLOR32;
1162 p->pixclock = KHZ2PICOS(refresh *
1163 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1164 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1166 debug("Pixel clock set to %lu.%03lu MHz\n",
1167 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1169 if (p != &fb_mode) {
1172 debug("Creating new display-timing node from '%s'\n",
1174 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1176 printf("Failed to create new display-timing node from '%s': %d\n",
1180 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1181 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1182 ARRAY_SIZE(stk5_lcd_pads));
1184 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1185 color_depth, refresh);
1187 if (karo_load_splashimage(0) == 0) {
1190 /* setup env variable for mxsfb display driver */
1191 snprintf(vmode, sizeof(vmode),
1192 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1193 p->xres, p->yres, p->left_margin, p->right_margin,
1194 p->upper_margin, p->lower_margin, p->hsync_len,
1195 p->vsync_len, p->sync, p->pixclock, color_depth);
1196 setenv("videomode", vmode);
1198 debug("Initializing LCD controller\n");
1201 setenv("videomode", NULL);
1203 debug("Skipping initialization of LCD controller\n");
1207 #define lcd_enabled 0
1208 #endif /* CONFIG_LCD */
1210 static void stk5_board_init(void)
1214 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1216 printf("Failed to request stk5_gpios: %d\n", ret);
1219 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1220 debug("%s@%d: \n", __func__, __LINE__);
1223 static void stk5v3_board_init(void)
1225 debug("%s@%d: \n", __func__, __LINE__);
1227 debug("%s@%d: \n", __func__, __LINE__);
1230 static void stk5v5_board_init(void)
1236 ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1237 "Flexcan Transceiver");
1239 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1243 imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1244 MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1247 static void tx6ul_set_cpu_clock(void)
1249 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1251 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1254 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1255 printf("%s detected; skipping cpu clock change\n",
1256 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1259 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1260 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1261 printf("CPU clock set to %lu.%03lu MHz\n",
1262 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1264 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1268 int board_late_init(void)
1271 const char *baseboard;
1273 debug("%s@%d: \n", __func__, __LINE__);
1277 if (tx6_temp_check_enabled)
1278 check_cpu_temperature(1);
1280 tx6ul_set_cpu_clock();
1283 setenv_ulong("safeboot", 1);
1284 else if (wrsr & WRSR_TOUT)
1285 setenv_ulong("wdreset", 1);
1287 karo_fdt_move_fdt();
1289 baseboard = getenv("baseboard");
1293 printf("Baseboard: %s\n", baseboard);
1295 if (strncmp(baseboard, "stk5", 4) == 0) {
1296 if ((strlen(baseboard) == 4) ||
1297 strcmp(baseboard, "stk5-v3") == 0) {
1298 stk5v3_board_init();
1299 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1300 const char *otg_mode = getenv("otg_mode");
1302 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1303 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1304 otg_mode, baseboard);
1305 setenv("otg_mode", "none");
1307 stk5v5_board_init();
1309 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1313 printf("WARNING: Unsupported baseboard: '%s'\n",
1319 debug("%s@%d: \n", __func__, __LINE__);
1321 debug("%s@%d: \n", __func__, __LINE__);
1327 #ifdef CONFIG_SERIAL_TAG
1328 void get_board_serial(struct tag_serialnr *serialnr)
1330 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1331 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1333 serialnr->low = readl(&fuse->cfg0);
1334 serialnr->high = readl(&fuse->cfg1);
1338 #if defined(CONFIG_OF_BOARD_SETUP)
1339 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1340 #include <jffs2/jffs2.h>
1341 #include <mtd_node.h>
1342 static struct node_info nodes[] = {
1343 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1346 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1349 static const char *tx6_touchpanels[] = {
1355 int ft_board_setup(void *blob, bd_t *bd)
1357 const char *baseboard = getenv("baseboard");
1358 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1359 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1362 ret = fdt_increase_size(blob, 4096);
1364 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1368 karo_fdt_enable_node(blob, "stk5led", 0);
1370 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1372 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1373 ARRAY_SIZE(tx6_touchpanels));
1374 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1375 karo_fdt_fixup_flexcan(blob, stk5_v5);
1377 karo_fdt_update_fb_mode(blob, video_mode);
1381 #endif /* CONFIG_OF_BOARD_SETUP */