karo: txul: remove i2c_gpio_pads
[karo-tx-uboot.git] / board / karo / tx6 / tx6ul.c
1 /*
2  * Copyright (C) 2015 Lothar WaƟmann <LW@KARO-electronics.de>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  *
6  */
7 #include <common.h>
8 #include <errno.h>
9 #include <libfdt.h>
10 #include <fdt_support.h>
11 #include <lcd.h>
12 #include <netdev.h>
13 #include <mmc.h>
14 #include <fsl_esdhc.h>
15 #include <video_fb.h>
16 #include <ipu.h>
17 #include <mxcfb.h>
18 #include <i2c.h>
19 #include <linux/fb.h>
20 #include <asm/io.h>
21 #include <asm/gpio.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
28
29 #include "../common/karo.h"
30 #include "pmic.h"
31
32 #define __data __attribute__((section(".data")))
33
34 #define TX6UL_FEC_RST_GPIO              IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO              IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO              IMX_GPIO_NR(5, 5)
37
38 #define TX6UL_FEC2_RST_GPIO             IMX_GPIO_NR(4, 28)
39 #define TX6UL_FEC2_INT_GPIO             IMX_GPIO_NR(4, 27)
40
41 #define TX6UL_LED_GPIO                  IMX_GPIO_NR(5, 9)
42
43 #define TX6UL_LCD_PWR_GPIO              IMX_GPIO_NR(5, 4)
44 #define TX6UL_LCD_RST_GPIO              IMX_GPIO_NR(3, 4)
45 #define TX6UL_LCD_BACKLIGHT_GPIO        IMX_GPIO_NR(4, 16)
46
47 #ifdef CONFIG_SYS_I2C_SOFT
48 #define TX6UL_I2C1_SCL_GPIO             CONFIG_SOFT_I2C_GPIO_SCL
49 #define TX6UL_I2C1_SDA_GPIO             CONFIG_SOFT_I2C_GPIO_SDA
50 #endif
51
52 #define TX6UL_SD1_CD_GPIO               IMX_GPIO_NR(4, 14)
53
54 #ifdef CONFIG_MX6_TEMPERATURE_MIN
55 #define TEMPERATURE_MIN                 CONFIG_MX6_TEMPERATURE_MIN
56 #else
57 #define TEMPERATURE_MIN                 (-40)
58 #endif
59 #ifdef CONFIG_MX6_TEMPERATURE_HOT
60 #define TEMPERATURE_HOT                 CONFIG_MX6_TEMPERATURE_HOT
61 #else
62 #define TEMPERATURE_HOT                 80
63 #endif
64
65 DECLARE_GLOBAL_DATA_PTR;
66
67 #define MUX_CFG_SION                    IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
68
69 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
70 #ifdef CONFIG_SECURE_BOOT
71 char __csf_data[0] __attribute__((section(".__csf_data")));
72 #endif
73
74 #define TX6UL_DEFAULT_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |      \
75                                         PAD_CTL_SPEED_MED |             \
76                                         PAD_CTL_DSE_40ohm |             \
77                                         PAD_CTL_SRE_FAST)
78 #define TX6UL_I2C_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |       \
79                                         PAD_CTL_ODE |                   \
80                                         PAD_CTL_HYS |                   \
81                                         PAD_CTL_SPEED_LOW |             \
82                                         PAD_CTL_DSE_34ohm |             \
83                                         PAD_CTL_SRE_FAST)
84 #define TX6UL_ENET_PAD_CTRL     MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |       \
85                                         PAD_CTL_DSE_120ohm |            \
86                                         PAD_CTL_PUS_100K_UP |           \
87                                         PAD_CTL_SRE_FAST)
88 #define TX6UL_GPIO_OUT_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
89                                         PAD_CTL_DSE_60ohm |             \
90                                         PAD_CTL_SRE_SLOW)
91 #define TX6UL_GPIO_IN_PAD_CTRL  MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |        \
92                                         PAD_CTL_PUS_47K_UP)
93
94
95 static const iomux_v3_cfg_t const tx6ul_pads[] = {
96         /* UART pads */
97 #if CONFIG_MXC_UART_BASE == UART1_BASE
98         MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
99         MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
100         MX6_PAD_UART1_RTS_B__UART1_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
101         MX6_PAD_UART1_CTS_B__UART1_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
102 #endif
103 #if CONFIG_MXC_UART_BASE == UART2_BASE
104         MX6_PAD_UART2_TX_DATA__UART2_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
105         MX6_PAD_UART2_RX_DATA__UART2_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
106         MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
107         MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
108 #endif
109 #if CONFIG_MXC_UART_BASE == UART5_BASE
110         MX6_PAD_GPIO1_IO04__UART5_DCE_TX | TX6UL_DEFAULT_PAD_CTRL,
111         MX6_PAD_GPIO1_IO05__UART5_DCE_RX | TX6UL_DEFAULT_PAD_CTRL,
112         MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | TX6UL_DEFAULT_PAD_CTRL,
113         MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | TX6UL_DEFAULT_PAD_CTRL,
114 #endif
115         /* FEC PHY GPIO functions */
116         MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY POWER */
117         MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | TX6UL_GPIO_OUT_PAD_CTRL, /* PHY RESET */
118         MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | TX6UL_GPIO_IN_PAD_CTRL, /* PHY INT */
119 };
120
121 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
122         /* FEC functions */
123         MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm |
124                                                      PAD_CTL_SPEED_LOW),
125         MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
126                                                       PAD_CTL_DSE_120ohm |
127                                                       PAD_CTL_SPEED_LOW),
128         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
129                                                      PAD_CTL_DSE_80ohm |
130                                                      PAD_CTL_SRE_SLOW),
131
132         MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | TX6UL_ENET_PAD_CTRL,
133         MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | TX6UL_ENET_PAD_CTRL,
134         MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | TX6UL_ENET_PAD_CTRL,
135         MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | TX6UL_ENET_PAD_CTRL,
136         MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | TX6UL_ENET_PAD_CTRL,
137         MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | TX6UL_ENET_PAD_CTRL,
138         MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | TX6UL_ENET_PAD_CTRL,
139 };
140
141 static const iomux_v3_cfg_t const tx6ul_enet2_pads[] = {
142         MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(PAD_CTL_SPEED_LOW |
143                                                             PAD_CTL_DSE_80ohm |
144                                                             PAD_CTL_SRE_SLOW),
145         MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | TX6UL_ENET_PAD_CTRL,
146         MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | TX6UL_ENET_PAD_CTRL,
147         MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | TX6UL_ENET_PAD_CTRL,
148         MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | TX6UL_ENET_PAD_CTRL,
149         MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | TX6UL_ENET_PAD_CTRL,
150         MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | TX6UL_ENET_PAD_CTRL,
151         MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | TX6UL_ENET_PAD_CTRL,
152 };
153
154 static const iomux_v3_cfg_t const tx6ul_i2c_pads[] = {
155         /* internal I2C */
156         MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
157                         TX6UL_I2C_PAD_CTRL, /* I2C SCL */
158         MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
159                         TX6UL_I2C_PAD_CTRL, /* I2C SDA */
160 };
161
162 static const struct gpio const tx6ul_gpios[] = {
163 #ifdef CONFIG_SYS_I2C_SOFT
164         /* These two entries are used to forcefully reinitialize the I2C bus */
165         { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
166         { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
167 #endif
168         { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
169         { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
170         { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
171 };
172
173 static const struct gpio const tx6ul_fec2_gpios[] = {
174         { TX6UL_FEC2_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC2 PHY RESET", },
175         { TX6UL_FEC2_INT_GPIO, GPIOFLAG_INPUT, "FEC2 PHY INT", },
176 };
177
178 #define GPIO_DR 0
179 #define GPIO_DIR 4
180 #define GPIO_PSR 8
181
182 /* run with default environment */
183 #if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
184 #define SCL_BANK        (TX6UL_I2C1_SCL_GPIO / 32)
185 #define SDA_BANK        (TX6UL_I2C1_SDA_GPIO / 32)
186 #define SCL_BIT         (1 << (TX6UL_I2C1_SCL_GPIO % 32))
187 #define SDA_BIT         (1 << (TX6UL_I2C1_SDA_GPIO % 32))
188
189 static void * const gpio_ports[] = {
190         (void *)GPIO1_BASE_ADDR,
191         (void *)GPIO2_BASE_ADDR,
192         (void *)GPIO3_BASE_ADDR,
193         (void *)GPIO4_BASE_ADDR,
194         (void *)GPIO5_BASE_ADDR,
195 };
196
197 static void tx6ul_i2c_recover(void)
198 {
199         int i;
200         int bad = 0;
201         struct gpio_regs *scl_regs = gpio_ports[SCL_BANK];
202         struct gpio_regs *sda_regs = gpio_ports[SDA_BANK];
203
204         if ((readl(&scl_regs->gpio_psr) & SCL_BIT) &&
205             (readl(&sda_regs->gpio_psr) & SDA_BIT))
206                 return;
207
208         debug("Clearing I2C bus\n");
209         if (!(readl(&scl_regs->gpio_psr) & SCL_BIT)) {
210                 printf("I2C SCL stuck LOW\n");
211                 bad++;
212
213                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
214                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
215
216                 imx_iomux_v3_setup_pad(MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 |
217                                        MUX_CFG_SION | TX6UL_GPIO_OUT_PAD_CTRL);
218         }
219         if (!(readl(&sda_regs->gpio_psr) & SDA_BIT)) {
220                 printf("I2C SDA stuck LOW\n");
221                 bad++;
222
223                 clrbits_le32(&sda_regs->gpio_dir, SDA_BIT);
224                 setbits_le32(&scl_regs->gpio_dr, SCL_BIT);
225                 setbits_le32(&scl_regs->gpio_dir, SCL_BIT);
226
227                 udelay(5);
228
229                 for (i = 0; i < 18; i++) {
230                         u32 reg = readl(&scl_regs->gpio_dr) ^ SCL_BIT;
231
232                         debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
233                         writel(reg, &scl_regs->gpio_dr);
234                         udelay(5);
235                         if (reg & SCL_BIT) {
236                                 if (readl(&sda_regs->gpio_psr) & SDA_BIT)
237                                         break;
238                                 if (!(readl(&scl_regs->gpio_psr) & SCL_BIT))
239                                         break;
240                                 break;
241                         }
242                 }
243         }
244         if (bad) {
245                 bool scl = !!(readl(&scl_regs->gpio_psr) & SCL_BIT);
246                 bool sda = !!(readl(&sda_regs->gpio_psr) & SDA_BIT);
247
248                 if (scl && sda) {
249                         printf("I2C bus recovery succeeded\n");
250                 } else {
251                         printf("I2C bus recovery FAILED: SCL: %d SDA: %d\n",
252                                scl, sda);
253                 }
254                 imx_iomux_v3_setup_multiple_pads(tx6ul_i2c_pads,
255                                                  ARRAY_SIZE(tx6ul_i2c_pads));
256         }
257 }
258 #else
259 static inline void tx6ul_i2c_recover(void)
260 {
261 }
262 #endif
263
264 /* placed in section '.data' to prevent overwriting relocation info
265  * overlayed with bss
266  */
267 static u32 wrsr __data;
268
269 #define WRSR_POR                        (1 << 4)
270 #define WRSR_TOUT                       (1 << 1)
271 #define WRSR_SFTW                       (1 << 0)
272
273 static void print_reset_cause(void)
274 {
275         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
276         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
277         u32 srsr;
278         char *dlm = "";
279
280         printf("Reset cause: ");
281
282         srsr = readl(&src_regs->srsr);
283         wrsr = readw(wdt_base + 4);
284
285         if (wrsr & WRSR_POR) {
286                 printf("%sPOR", dlm);
287                 dlm = " | ";
288         }
289         if (srsr & 0x00004) {
290                 printf("%sCSU", dlm);
291                 dlm = " | ";
292         }
293         if (srsr & 0x00008) {
294                 printf("%sIPP USER", dlm);
295                 dlm = " | ";
296         }
297         if (srsr & 0x00010) {
298                 if (wrsr & WRSR_SFTW) {
299                         printf("%sSOFT", dlm);
300                         dlm = " | ";
301                 }
302                 if (wrsr & WRSR_TOUT) {
303                         printf("%sWDOG", dlm);
304                         dlm = " | ";
305                 }
306         }
307         if (srsr & 0x00020) {
308                 printf("%sJTAG HIGH-Z", dlm);
309                 dlm = " | ";
310         }
311         if (srsr & 0x00040) {
312                 printf("%sJTAG SW", dlm);
313                 dlm = " | ";
314         }
315         if (srsr & 0x10000) {
316                 printf("%sWARM BOOT", dlm);
317                 dlm = " | ";
318         }
319         if (dlm[0] == '\0')
320                 printf("unknown");
321
322         printf("\n");
323 }
324
325 #ifdef CONFIG_IMX6_THERMAL
326 #include <thermal.h>
327 #include <imx_thermal.h>
328 #include <fuse.h>
329
330 static void print_temperature(void)
331 {
332         struct udevice *thermal_dev;
333         int cpu_tmp, minc, maxc, ret;
334         char const *grade_str;
335         static u32 __data thermal_calib;
336
337         puts("Temperature: ");
338         switch (get_cpu_temp_grade(&minc, &maxc)) {
339         case TEMP_AUTOMOTIVE:
340                 grade_str = "Automotive";
341                 break;
342         case TEMP_INDUSTRIAL:
343                 grade_str = "Industrial";
344                 break;
345         case TEMP_EXTCOMMERCIAL:
346                 grade_str = "Extended Commercial";
347                 break;
348         default:
349                 grade_str = "Commercial";
350         }
351         printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
352         ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
353         if (ret == 0) {
354                 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
355
356                 if (ret == 0)
357                         printf(" at %dC", cpu_tmp);
358                 else
359                         puts(" - failed to read sensor data");
360         } else {
361                 puts(" - no sensor device found");
362         }
363
364         if (fuse_read(1, 6, &thermal_calib) == 0) {
365                 printf(" - calibration data 0x%08x\n", thermal_calib);
366         } else {
367                 puts(" - Failed to read thermal calib fuse\n");
368         }
369 }
370 #else
371 static inline void print_temperature(void)
372 {
373 }
374 #endif
375
376 int checkboard(void)
377 {
378         u32 cpurev = get_cpu_rev();
379         char *cpu_str = "?";
380
381         if (is_cpu_type(MXC_CPU_MX6SL))
382                 cpu_str = "SL";
383         else if (is_cpu_type(MXC_CPU_MX6DL))
384                 cpu_str = "DL";
385         else if (is_cpu_type(MXC_CPU_MX6SOLO))
386                 cpu_str = "SOLO";
387         else if (is_cpu_type(MXC_CPU_MX6Q))
388                 cpu_str = "Q";
389         else if (is_cpu_type(MXC_CPU_MX6UL))
390                 cpu_str = "UL";
391         else if (is_cpu_type(MXC_CPU_MX6ULL))
392                 cpu_str = "ULL";
393
394         printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
395                 cpu_str,
396                 (cpurev & 0x000F0) >> 4,
397                 (cpurev & 0x0000F) >> 0,
398                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
399
400         print_temperature();
401         print_reset_cause();
402 #ifdef CONFIG_MX6_TEMPERATURE_HOT
403         check_cpu_temperature(1);
404 #endif
405         tx6ul_i2c_recover();
406         return 0;
407 }
408
409 /* serial port not initialized at this point */
410 int board_early_init_f(void)
411 {
412         return 0;
413 }
414
415 #ifndef CONFIG_MX6_TEMPERATURE_HOT
416 static bool tx6ul_temp_check_enabled = true;
417 #else
418 #define tx6ul_temp_check_enabled        0
419 #endif
420
421 static inline u8 tx6ul_mem_suffix(void)
422 {
423         return '0' + CONFIG_SYS_SDRAM_CHIP_SIZE / 1024 * 2 +
424                 IS_ENABLED(CONFIG_TX6_EMMC);
425 }
426
427 #ifdef CONFIG_RN5T567
428 /* PMIC settings */
429 #define VDD_RTC_VAL             rn5t_mV_to_regval_rtc(3000)
430 #define VDD_CORE_VAL            rn5t_mV_to_regval(1300)         /* DCDC1 */
431 #define VDD_CORE_VAL_LP         rn5t_mV_to_regval(900)
432 #define VDD_DDR_VAL             rn5t_mV_to_regval(1350)         /* DCDC3 */
433 #define VDD_DDR_VAL_LP          rn5t_mV_to_regval(1350)
434 #define VDD_IO_EXT_VAL          rn5t_mV_to_regval(3300)         /* DCDC4 */
435 #define VDD_IO_EXT_VAL_LP       rn5t_mV_to_regval(3300)
436 #define VDD_IO_INT_VAL          rn5t_mV_to_regval2(3300)        /* LDO1 */
437 #define VDD_IO_INT_VAL_LP       rn5t_mV_to_regval2(3300)
438 #define VDD_ADC_VAL             rn5t_mV_to_regval2(3300)        /* LDO2 */
439 #define VDD_ADC_VAL_LP          rn5t_mV_to_regval2(3300)
440 #define VDD_PMIC_VAL            rn5t_mV_to_regval2(2500)        /* LDO3 */
441 #define VDD_PMIC_VAL_LP         rn5t_mV_to_regval2(2500)
442 #define VDD_CSI_VAL             rn5t_mV_to_regval2(1800)        /* LDO4 */
443 #define VDD_CSI_VAL_LP          rn5t_mV_to_regval2(1800)
444
445 static struct pmic_regs rn5t567_regs[] = {
446         { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
447         { RN5T567_DC1DAC, VDD_CORE_VAL, },
448         { RN5T567_DC3DAC, VDD_DDR_VAL, },
449         { RN5T567_DC4DAC, VDD_IO_EXT_VAL, },
450         { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
451         { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
452         { RN5T567_DC4DAC_SLP, VDD_IO_EXT_VAL_LP, },
453         { RN5T567_DC1CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
454         { RN5T567_DC2CTL, DCnCTL_DCnDIS, },
455         { RN5T567_DC3CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
456         { RN5T567_DC4CTL, DCnCTL_DCnEN | DCnMODE_SLP(DCnMODE_PSM), },
457         { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
458         { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
459         { RN5T567_LDO1DAC, VDD_IO_INT_VAL, },
460         { RN5T567_LDO2DAC, VDD_ADC_VAL, },
461         { RN5T567_LDO3DAC, VDD_PMIC_VAL, },
462         { RN5T567_LDO4DAC, VDD_CSI_VAL, },
463         { RN5T567_LDOEN1, 0x0f, ~0x1f, },
464         { RN5T567_LDOEN2, 0x10, ~0x30, },
465         { RN5T567_LDODIS, 0x10, ~0x1f, },
466         { RN5T567_INTPOL, 0, },
467         { RN5T567_INTEN, 0x3, },
468         { RN5T567_IREN, 0xf, },
469         { RN5T567_EN_GPIR, 0, },
470 };
471
472 static int pmic_addr = 0x33;
473 #endif
474
475 int board_init(void)
476 {
477         int ret;
478         u32 cpurev = get_cpu_rev();
479         char f = '?';
480
481         if (is_cpu_type(MXC_CPU_MX6UL))
482                 f = ((cpurev & 0xf0) > 0x10) ? '5' : '0';
483         else if (is_cpu_type(MXC_CPU_MX6ULL))
484                 f = '8';
485
486         debug("%s@%d: cpurev=%08x\n", __func__, __LINE__, cpurev);
487
488         printf("Board: Ka-Ro TXUL-%c01%c\n", f, tx6ul_mem_suffix());
489
490         get_hab_status();
491
492         ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
493         if (ret < 0)
494                 printf("Failed to request tx6ul_gpios: %d\n", ret);
495
496         imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
497
498         /* Address of boot parameters */
499         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
500         gd->bd->bi_arch_number = -1;
501
502         if (ctrlc() || (wrsr & WRSR_TOUT)) {
503                 if (wrsr & WRSR_TOUT)
504                         printf("WDOG RESET detected; Skipping PMIC setup\n");
505                 else
506                         printf("<CTRL-C> detected; safeboot enabled\n");
507 #ifndef CONFIG_MX6_TEMPERATURE_HOT
508                 tx6ul_temp_check_enabled = false;
509 #endif
510                 return 0;
511         }
512
513         ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
514         if (ret) {
515                 printf("Failed to setup PMIC voltages: %d\n", ret);
516                 hang();
517         }
518         return 0;
519 }
520
521 int dram_init(void)
522 {
523         debug("%s@%d: \n", __func__, __LINE__);
524
525         /* dram_init must store complete ramsize in gd->ram_size */
526         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
527                                     PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
528         return 0;
529 }
530
531 void dram_init_banksize(void)
532 {
533         debug("%s@%d: \n", __func__, __LINE__);
534
535         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
536         gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
537                                                PHYS_SDRAM_1_SIZE);
538 #if CONFIG_NR_DRAM_BANKS > 1
539         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
540         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
541                                                PHYS_SDRAM_2_SIZE);
542 #endif
543 }
544
545 #ifdef  CONFIG_FSL_ESDHC
546 #define TX6UL_SD_PAD_CTRL       MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |       \
547                                         PAD_CTL_SPEED_MED |             \
548                                         PAD_CTL_DSE_40ohm |             \
549                                         PAD_CTL_SRE_FAST)
550
551 static const iomux_v3_cfg_t mmc0_pads[] = {
552         MX6_PAD_SD1_CMD__USDHC1_CMD | TX6UL_SD_PAD_CTRL,
553         MX6_PAD_SD1_CLK__USDHC1_CLK | TX6UL_SD_PAD_CTRL,
554         MX6_PAD_SD1_DATA0__USDHC1_DATA0 | TX6UL_SD_PAD_CTRL,
555         MX6_PAD_SD1_DATA1__USDHC1_DATA1 | TX6UL_SD_PAD_CTRL,
556         MX6_PAD_SD1_DATA2__USDHC1_DATA2 | TX6UL_SD_PAD_CTRL,
557         MX6_PAD_SD1_DATA3__USDHC1_DATA3 | TX6UL_SD_PAD_CTRL,
558         /* SD1 CD */
559         MX6_PAD_NAND_CE1_B__GPIO4_IO14 | TX6UL_SD_PAD_CTRL,
560 };
561
562 #ifdef CONFIG_TX6_EMMC
563 static const iomux_v3_cfg_t mmc1_pads[] = {
564         MX6_PAD_NAND_WE_B__USDHC2_CMD | TX6UL_SD_PAD_CTRL,
565         MX6_PAD_NAND_RE_B__USDHC2_CLK | TX6UL_SD_PAD_CTRL,
566         MX6_PAD_NAND_DATA00__USDHC2_DATA0 | TX6UL_SD_PAD_CTRL,
567         MX6_PAD_NAND_DATA01__USDHC2_DATA1 | TX6UL_SD_PAD_CTRL,
568         MX6_PAD_NAND_DATA02__USDHC2_DATA2 | TX6UL_SD_PAD_CTRL,
569         MX6_PAD_NAND_DATA03__USDHC2_DATA3 | TX6UL_SD_PAD_CTRL,
570         /* eMMC RESET */
571         MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
572                                                         PAD_CTL_DSE_40ohm),
573 };
574 #endif
575
576 static struct tx6ul_esdhc_cfg {
577         const iomux_v3_cfg_t *pads;
578         int num_pads;
579         enum mxc_clock clkid;
580         struct fsl_esdhc_cfg cfg;
581         int cd_gpio;
582 } tx6ul_esdhc_cfg[] = {
583 #ifdef CONFIG_TX6_EMMC
584         {
585                 .pads = mmc1_pads,
586                 .num_pads = ARRAY_SIZE(mmc1_pads),
587                 .clkid = MXC_ESDHC2_CLK,
588                 .cfg = {
589                         .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
590                         .max_bus_width = 4,
591                 },
592                 .cd_gpio = -EINVAL,
593         },
594 #endif
595         {
596                 .pads = mmc0_pads,
597                 .num_pads = ARRAY_SIZE(mmc0_pads),
598                 .clkid = MXC_ESDHC_CLK,
599                 .cfg = {
600                         .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
601                         .max_bus_width = 4,
602                 },
603                 .cd_gpio = TX6UL_SD1_CD_GPIO,
604         },
605 };
606
607 static inline struct tx6ul_esdhc_cfg *to_tx6ul_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
608 {
609         return container_of(cfg, struct tx6ul_esdhc_cfg, cfg);
610 }
611
612 int board_mmc_getcd(struct mmc *mmc)
613 {
614         struct tx6ul_esdhc_cfg *cfg = to_tx6ul_esdhc_cfg(mmc->priv);
615
616         if (cfg->cd_gpio < 0)
617                 return 1;
618
619         debug("SD card %d is %spresent (GPIO %d)\n",
620               cfg - tx6ul_esdhc_cfg,
621               gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
622               cfg->cd_gpio);
623         return !gpio_get_value(cfg->cd_gpio);
624 }
625
626 int board_mmc_init(bd_t *bis)
627 {
628         int i;
629
630         debug("%s@%d: \n", __func__, __LINE__);
631
632 #ifndef CONFIG_ENV_IS_IN_MMC
633         if (!(gd->flags & GD_FLG_ENV_READY)) {
634                 printf("deferred ...");
635                 return 0;
636         }
637 #endif
638         for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
639                 struct mmc *mmc;
640                 struct tx6ul_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
641                 int ret;
642
643                 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
644                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
645
646                 if (cfg->cd_gpio >= 0) {
647                         ret = gpio_request_one(cfg->cd_gpio,
648                                                GPIOFLAG_INPUT, "MMC CD");
649                         if (ret) {
650                                 printf("Error %d requesting GPIO%d_%d\n",
651                                        ret, cfg->cd_gpio / 32,
652                                        cfg->cd_gpio % 32);
653                                 continue;
654                         }
655                 }
656
657                 debug("%s: Initializing MMC slot %d\n", __func__, i);
658                 fsl_esdhc_initialize(bis, &cfg->cfg);
659
660                 mmc = find_mmc_device(i);
661                 if (mmc == NULL)
662                         continue;
663                 if (board_mmc_getcd(mmc))
664                         mmc_init(mmc);
665         }
666         return 0;
667 }
668 #endif /* CONFIG_FSL_ESDHC */
669
670 enum {
671         LED_STATE_INIT = -1,
672         LED_STATE_OFF,
673         LED_STATE_ON,
674         LED_STATE_ERR,
675 };
676
677 static inline int calc_blink_rate(void)
678 {
679         if (!tx6ul_temp_check_enabled)
680                 return CONFIG_SYS_HZ;
681
682         return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
683                 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
684                 (TEMPERATURE_HOT - TEMPERATURE_MIN);
685 }
686
687 void show_activity(int arg)
688 {
689         static int led_state = LED_STATE_INIT;
690         static int blink_rate;
691         static ulong last;
692         int ret;
693
694         switch (led_state) {
695         case LED_STATE_ERR:
696                 return;
697
698         case LED_STATE_INIT:
699                 last = get_timer(0);
700                 ret = gpio_set_value(TX6UL_LED_GPIO, 1);
701                 if (ret)
702                         led_state = LED_STATE_ERR;
703                 else
704                         led_state = LED_STATE_ON;
705                 blink_rate = calc_blink_rate();
706                 break;
707
708         case LED_STATE_ON:
709         case LED_STATE_OFF:
710                 if (get_timer(last) > blink_rate) {
711                         blink_rate = calc_blink_rate();
712                         last = get_timer_masked();
713                         if (led_state == LED_STATE_ON) {
714                                 gpio_set_value(TX6UL_LED_GPIO, 0);
715                         } else {
716                                 gpio_set_value(TX6UL_LED_GPIO, 1);
717                         }
718                         led_state = 1 - led_state;
719                 }
720                 break;
721         }
722 }
723
724 static const iomux_v3_cfg_t stk5_jtag_pads[] = {
725         MX6_PAD_JTAG_MOD__SJC_MOD | TX6UL_GPIO_IN_PAD_CTRL,
726         MX6_PAD_JTAG_TCK__SJC_TCK | TX6UL_GPIO_IN_PAD_CTRL,
727         MX6_PAD_JTAG_TRST_B__SJC_TRSTB | TX6UL_GPIO_IN_PAD_CTRL,
728         MX6_PAD_JTAG_TDI__SJC_TDI | TX6UL_GPIO_IN_PAD_CTRL,
729         MX6_PAD_JTAG_TDO__SJC_TDO | TX6UL_GPIO_OUT_PAD_CTRL,
730         MX6_PAD_JTAG_TMS__SJC_TMS | TX6UL_GPIO_IN_PAD_CTRL,
731 };
732
733 static const iomux_v3_cfg_t stk5_pads[] = {
734         /* SW controlled LED on STK5 baseboard */
735         MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
736
737         /* I2C bus on DIMM pins 40/41 */
738         MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
739         MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | TX6UL_I2C_PAD_CTRL,
740
741         /* TSC200x PEN IRQ */
742         MX6_PAD_JTAG_TMS__GPIO1_IO11 | TX6UL_GPIO_IN_PAD_CTRL,
743
744         /* EDT-FT5x06 Polytouch panel */
745         MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | TX6UL_GPIO_IN_PAD_CTRL, /* IRQ */
746         MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 | TX6UL_GPIO_OUT_PAD_CTRL, /* RESET */
747         MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | TX6UL_GPIO_OUT_PAD_CTRL, /* WAKE */
748
749         /* USBH1 */
750         MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
751         MX6_PAD_GPIO1_IO03__USB_OTG2_OC | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
752
753         /* USBOTG */
754         MX6_PAD_UART3_CTS_B__GPIO1_IO26 | TX6UL_GPIO_OUT_PAD_CTRL, /* VBUSEN */
755         MX6_PAD_UART3_RTS_B__GPIO1_IO27 | TX6UL_GPIO_IN_PAD_CTRL, /* OC */
756 };
757
758 static const struct gpio stk5_gpios[] = {
759         { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
760
761         { IMX_GPIO_NR(1, 27), GPIOFLAG_INPUT, "USBOTG OC", },
762         { IMX_GPIO_NR(1, 26), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
763 };
764
765 #ifdef CONFIG_LCD
766 vidinfo_t panel_info = {
767         /* set to max. size supported by SoC */
768         .vl_col = 4096,
769         .vl_row = 1024,
770
771         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
772 };
773
774 static struct fb_videomode tx6ul_fb_modes[] = {
775 #ifndef CONFIG_SYS_LVDS_IF
776         {
777                 /* Standard VGA timing */
778                 .name           = "VGA",
779                 .refresh        = 60,
780                 .xres           = 640,
781                 .yres           = 480,
782                 .pixclock       = KHZ2PICOS(25175),
783                 .left_margin    = 48,
784                 .hsync_len      = 96,
785                 .right_margin   = 16,
786                 .upper_margin   = 31,
787                 .vsync_len      = 2,
788                 .lower_margin   = 12,
789                 .sync           = FB_SYNC_CLK_LAT_FALL,
790         },
791         {
792                 /* Emerging ETV570 640 x 480 display. Syncs low active,
793                  * DE high active, 115.2 mm x 86.4 mm display area
794                  * VGA compatible timing
795                  */
796                 .name           = "ETV570",
797                 .refresh        = 60,
798                 .xres           = 640,
799                 .yres           = 480,
800                 .pixclock       = KHZ2PICOS(25175),
801                 .left_margin    = 114,
802                 .hsync_len      = 30,
803                 .right_margin   = 16,
804                 .upper_margin   = 32,
805                 .vsync_len      = 3,
806                 .lower_margin   = 10,
807                 .sync           = FB_SYNC_CLK_LAT_FALL,
808         },
809         {
810                 /* Emerging ET0350G0DH6 320 x 240 display.
811                  * 70.08 mm x 52.56 mm display area.
812                  */
813                 .name           = "ET0350",
814                 .refresh        = 60,
815                 .xres           = 320,
816                 .yres           = 240,
817                 .pixclock       = KHZ2PICOS(6500),
818                 .left_margin    = 68 - 34,
819                 .hsync_len      = 34,
820                 .right_margin   = 20,
821                 .upper_margin   = 18 - 3,
822                 .vsync_len      = 3,
823                 .lower_margin   = 4,
824                 .sync           = FB_SYNC_CLK_LAT_FALL,
825         },
826         {
827                 /* Emerging ET0430G0DH6 480 x 272 display.
828                  * 95.04 mm x 53.856 mm display area.
829                  */
830                 .name           = "ET0430",
831                 .refresh        = 60,
832                 .xres           = 480,
833                 .yres           = 272,
834                 .pixclock       = KHZ2PICOS(9000),
835                 .left_margin    = 2,
836                 .hsync_len      = 41,
837                 .right_margin   = 2,
838                 .upper_margin   = 2,
839                 .vsync_len      = 10,
840                 .lower_margin   = 2,
841         },
842         {
843                 /* Emerging ET0500G0DH6 800 x 480 display.
844                  * 109.6 mm x 66.4 mm display area.
845                  */
846                 .name           = "ET0500",
847                 .refresh        = 60,
848                 .xres           = 800,
849                 .yres           = 480,
850                 .pixclock       = KHZ2PICOS(33260),
851                 .left_margin    = 216 - 128,
852                 .hsync_len      = 128,
853                 .right_margin   = 1056 - 800 - 216,
854                 .upper_margin   = 35 - 2,
855                 .vsync_len      = 2,
856                 .lower_margin   = 525 - 480 - 35,
857                 .sync           = FB_SYNC_CLK_LAT_FALL,
858         },
859         {
860                 /* Emerging ETQ570G0DH6 320 x 240 display.
861                  * 115.2 mm x 86.4 mm display area.
862                  */
863                 .name           = "ETQ570",
864                 .refresh        = 60,
865                 .xres           = 320,
866                 .yres           = 240,
867                 .pixclock       = KHZ2PICOS(6400),
868                 .left_margin    = 38,
869                 .hsync_len      = 30,
870                 .right_margin   = 30,
871                 .upper_margin   = 16, /* 15 according to datasheet */
872                 .vsync_len      = 3, /* TVP -> 1>x>5 */
873                 .lower_margin   = 4, /* 4.5 according to datasheet */
874                 .sync           = FB_SYNC_CLK_LAT_FALL,
875         },
876         {
877                 /* Emerging ET0700G0DH6 800 x 480 display.
878                  * 152.4 mm x 91.44 mm display area.
879                  */
880                 .name           = "ET0700",
881                 .refresh        = 60,
882                 .xres           = 800,
883                 .yres           = 480,
884                 .pixclock       = KHZ2PICOS(33260),
885                 .left_margin    = 216 - 128,
886                 .hsync_len      = 128,
887                 .right_margin   = 1056 - 800 - 216,
888                 .upper_margin   = 35 - 2,
889                 .vsync_len      = 2,
890                 .lower_margin   = 525 - 480 - 35,
891                 .sync           = FB_SYNC_CLK_LAT_FALL,
892         },
893         {
894                 /* Emerging ET070001DM6 800 x 480 display.
895                  * 152.4 mm x 91.44 mm display area.
896                  */
897                 .name           = "ET070001DM6",
898                 .refresh        = 60,
899                 .xres           = 800,
900                 .yres           = 480,
901                 .pixclock       = KHZ2PICOS(33260),
902                 .left_margin    = 216 - 128,
903                 .hsync_len      = 128,
904                 .right_margin   = 1056 - 800 - 216,
905                 .upper_margin   = 35 - 2,
906                 .vsync_len      = 2,
907                 .lower_margin   = 525 - 480 - 35,
908                 .sync           = 0,
909         },
910 #else
911         {
912                 /* HannStar HSD100PXN1
913                  * 202.7m mm x 152.06 mm display area.
914                  */
915                 .name           = "HSD100PXN1",
916                 .refresh        = 60,
917                 .xres           = 1024,
918                 .yres           = 768,
919                 .pixclock       = KHZ2PICOS(65000),
920                 .left_margin    = 0,
921                 .hsync_len      = 0,
922                 .right_margin   = 320,
923                 .upper_margin   = 0,
924                 .vsync_len      = 0,
925                 .lower_margin   = 38,
926                 .sync           = FB_SYNC_CLK_LAT_FALL,
927         },
928 #endif
929         {
930                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
931                 .refresh        = 60,
932                 .left_margin    = 48,
933                 .hsync_len      = 96,
934                 .right_margin   = 16,
935                 .upper_margin   = 31,
936                 .vsync_len      = 2,
937                 .lower_margin   = 12,
938                 .sync           = FB_SYNC_CLK_LAT_FALL,
939         },
940 };
941
942 static int lcd_enabled = 1;
943 static int lcd_bl_polarity;
944
945 static int lcd_backlight_polarity(void)
946 {
947         return lcd_bl_polarity;
948 }
949
950 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
951 #ifdef CONFIG_LCD
952         /* LCD RESET */
953         MX6_PAD_LCD_RESET__GPIO3_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
954         /* LCD POWER_ENABLE */
955         MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | TX6UL_GPIO_OUT_PAD_CTRL,
956         /* LCD Backlight (PWM) */
957         MX6_PAD_NAND_DQS__GPIO4_IO16 | TX6UL_GPIO_OUT_PAD_CTRL,
958         /* Display */
959         MX6_PAD_LCD_DATA00__LCDIF_DATA00,
960         MX6_PAD_LCD_DATA01__LCDIF_DATA01,
961         MX6_PAD_LCD_DATA02__LCDIF_DATA02,
962         MX6_PAD_LCD_DATA03__LCDIF_DATA03,
963         MX6_PAD_LCD_DATA04__LCDIF_DATA04,
964         MX6_PAD_LCD_DATA05__LCDIF_DATA05,
965         MX6_PAD_LCD_DATA06__LCDIF_DATA06,
966         MX6_PAD_LCD_DATA07__LCDIF_DATA07,
967         MX6_PAD_LCD_DATA08__LCDIF_DATA08,
968         MX6_PAD_LCD_DATA09__LCDIF_DATA09,
969         MX6_PAD_LCD_DATA10__LCDIF_DATA10,
970         MX6_PAD_LCD_DATA11__LCDIF_DATA11,
971         MX6_PAD_LCD_DATA12__LCDIF_DATA12,
972         MX6_PAD_LCD_DATA13__LCDIF_DATA13,
973         MX6_PAD_LCD_DATA14__LCDIF_DATA14,
974         MX6_PAD_LCD_DATA15__LCDIF_DATA15,
975         MX6_PAD_LCD_DATA16__LCDIF_DATA16,
976         MX6_PAD_LCD_DATA17__LCDIF_DATA17,
977         MX6_PAD_LCD_DATA18__LCDIF_DATA18,
978         MX6_PAD_LCD_DATA19__LCDIF_DATA19,
979         MX6_PAD_LCD_DATA20__LCDIF_DATA20,
980         MX6_PAD_LCD_DATA21__LCDIF_DATA21,
981         MX6_PAD_LCD_DATA22__LCDIF_DATA22,
982         MX6_PAD_LCD_DATA23__LCDIF_DATA23,
983         MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
984         MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
985         MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
986         MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
987 #endif
988 };
989
990 static const struct gpio stk5_lcd_gpios[] = {
991         { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
992         { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
993         { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
994 };
995
996 /* run with valid env from NAND/eMMC */
997 void lcd_enable(void)
998 {
999         /* HACK ALERT:
1000          * global variable from common/lcd.c
1001          * Set to 0 here to prevent messages from going to LCD
1002          * rather than serial console
1003          */
1004         lcd_is_enabled = 0;
1005
1006         if (lcd_enabled) {
1007                 karo_load_splashimage(1);
1008
1009                 debug("Switching LCD on\n");
1010                 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
1011                 udelay(100);
1012                 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
1013                 udelay(300000);
1014                 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
1015                                lcd_backlight_polarity());
1016         }
1017 }
1018
1019 static void lcd_disable(void)
1020 {
1021         if (lcd_enabled) {
1022                 printf("Disabling LCD\n");
1023                 panel_info.vl_row = 0;
1024                 lcd_enabled = 0;
1025         }
1026 }
1027
1028 void lcd_ctrl_init(void *lcdbase)
1029 {
1030         int color_depth = 24;
1031         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1032         const char *vm;
1033         unsigned long val;
1034         int refresh = 60;
1035         struct fb_videomode *p = &tx6ul_fb_modes[0];
1036         struct fb_videomode fb_mode;
1037         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1038
1039         if (!lcd_enabled) {
1040                 debug("LCD disabled\n");
1041                 return;
1042         }
1043
1044         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1045                 lcd_disable();
1046                 setenv("splashimage", NULL);
1047                 return;
1048         }
1049
1050         karo_fdt_move_fdt();
1051         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1052
1053         if (video_mode == NULL) {
1054                 lcd_disable();
1055                 return;
1056         }
1057         vm = video_mode;
1058         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1059                 p = &fb_mode;
1060                 debug("Using video mode from FDT\n");
1061                 vm += strlen(vm);
1062                 if (fb_mode.xres > panel_info.vl_col ||
1063                         fb_mode.yres > panel_info.vl_row) {
1064                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1065                                fb_mode.xres, fb_mode.yres,
1066                                panel_info.vl_col, panel_info.vl_row);
1067                         lcd_enabled = 0;
1068                         return;
1069                 }
1070         }
1071         if (p->name != NULL)
1072                 debug("Trying compiled-in video modes\n");
1073         while (p->name != NULL) {
1074                 if (strcmp(p->name, vm) == 0) {
1075                         debug("Using video mode: '%s'\n", p->name);
1076                         vm += strlen(vm);
1077                         break;
1078                 }
1079                 p++;
1080         }
1081         if (*vm != '\0')
1082                 debug("Trying to decode video_mode: '%s'\n", vm);
1083         while (*vm != '\0') {
1084                 if (*vm >= '0' && *vm <= '9') {
1085                         char *end;
1086
1087                         val = simple_strtoul(vm, &end, 0);
1088                         if (end > vm) {
1089                                 if (!xres_set) {
1090                                         if (val > panel_info.vl_col)
1091                                                 val = panel_info.vl_col;
1092                                         p->xres = val;
1093                                         panel_info.vl_col = val;
1094                                         xres_set = 1;
1095                                 } else if (!yres_set) {
1096                                         if (val > panel_info.vl_row)
1097                                                 val = panel_info.vl_row;
1098                                         p->yres = val;
1099                                         panel_info.vl_row = val;
1100                                         yres_set = 1;
1101                                 } else if (!bpp_set) {
1102                                         switch (val) {
1103                                         case 8:
1104                                         case 16:
1105                                         case 18:
1106                                         case 24:
1107                                         case 32:
1108                                                 color_depth = val;
1109                                                 break;
1110
1111                                         default:
1112                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1113                                                        end - vm, vm,
1114                                                        color_depth);
1115                                         }
1116                                         bpp_set = 1;
1117                                 } else if (!refresh_set) {
1118                                         refresh = val;
1119                                         refresh_set = 1;
1120                                 }
1121                         }
1122                         vm = end;
1123                 }
1124                 switch (*vm) {
1125                 case '@':
1126                         bpp_set = 1;
1127                         /* fallthru */
1128                 case '-':
1129                         yres_set = 1;
1130                         /* fallthru */
1131                 case 'x':
1132                         xres_set = 1;
1133                         /* fallthru */
1134                 case 'M':
1135                 case 'R':
1136                         vm++;
1137                         break;
1138
1139                 default:
1140                         if (*vm != '\0')
1141                                 vm++;
1142                 }
1143         }
1144         if (p->xres == 0 || p->yres == 0) {
1145                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1146                 lcd_enabled = 0;
1147                 printf("Supported video modes are:");
1148                 for (p = &tx6ul_fb_modes[0]; p->name != NULL; p++) {
1149                         printf(" %s", p->name);
1150                 }
1151                 printf("\n");
1152                 return;
1153         }
1154         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1155                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1156                        p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1157                 lcd_enabled = 0;
1158                 return;
1159         }
1160         panel_info.vl_col = p->xres;
1161         panel_info.vl_row = p->yres;
1162
1163         switch (color_depth) {
1164         case 8:
1165                 panel_info.vl_bpix = LCD_COLOR8;
1166                 break;
1167         case 16:
1168                 panel_info.vl_bpix = LCD_COLOR16;
1169                 break;
1170         default:
1171                 panel_info.vl_bpix = LCD_COLOR32;
1172         }
1173
1174         p->pixclock = KHZ2PICOS(refresh *
1175                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1176                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1177                                 1000);
1178         debug("Pixel clock set to %lu.%03lu MHz\n",
1179               PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1180
1181         if (p != &fb_mode) {
1182                 int ret;
1183
1184                 debug("Creating new display-timing node from '%s'\n",
1185                       video_mode);
1186                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1187                 if (ret)
1188                         printf("Failed to create new display-timing node from '%s': %d\n",
1189                                video_mode, ret);
1190         }
1191
1192         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1193         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1194                                          ARRAY_SIZE(stk5_lcd_pads));
1195
1196         debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1197               color_depth, refresh);
1198
1199         if (karo_load_splashimage(0) == 0) {
1200                 char vmode[128];
1201
1202                 /* setup env variable for mxsfb display driver */
1203                 snprintf(vmode, sizeof(vmode),
1204                          "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1205                          p->xres, p->yres, p->left_margin, p->right_margin,
1206                          p->upper_margin, p->lower_margin, p->hsync_len,
1207                          p->vsync_len, p->sync, p->pixclock, color_depth);
1208                 setenv("videomode", vmode);
1209
1210                 debug("Initializing LCD controller\n");
1211                 lcdif_clk_enable();
1212                 video_hw_init();
1213                 setenv("videomode", NULL);
1214         } else {
1215                 debug("Skipping initialization of LCD controller\n");
1216         }
1217 }
1218 #else
1219 #define lcd_enabled 0
1220 #endif /* CONFIG_LCD */
1221
1222 #ifndef CONFIG_ENV_IS_IN_MMC
1223 static void tx6ul_mmc_init(void)
1224 {
1225         puts("MMC:   ");
1226         if (board_mmc_init(gd->bd) < 0)
1227                 cpu_mmc_init(gd->bd);
1228         print_mmc_devices(',');
1229 }
1230 #else
1231 static inline void tx6ul_mmc_init(void)
1232 {
1233 }
1234 #endif
1235
1236 static void stk5_board_init(void)
1237 {
1238         int ret;
1239
1240         ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1241         if (ret < 0) {
1242                 printf("Failed to request stk5_gpios: %d\n", ret);
1243                 return;
1244         }
1245
1246         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1247         if (getenv_yesno("jtag_enable") != 0) {
1248                 /* true if unset or set to one of: 'yYtT1' */
1249                 imx_iomux_v3_setup_multiple_pads(stk5_jtag_pads, ARRAY_SIZE(stk5_jtag_pads));
1250         }
1251
1252         debug("%s@%d: \n", __func__, __LINE__);
1253 }
1254
1255 static void stk5v3_board_init(void)
1256 {
1257         debug("%s@%d: \n", __func__, __LINE__);
1258         stk5_board_init();
1259         debug("%s@%d: \n", __func__, __LINE__);
1260         tx6ul_mmc_init();
1261 }
1262
1263 static void stk5v5_board_init(void)
1264 {
1265         int ret;
1266
1267         stk5_board_init();
1268         tx6ul_mmc_init();
1269
1270         ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1271                                "Flexcan Transceiver");
1272         if (ret) {
1273                 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1274                 return;
1275         }
1276
1277         imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1278                                TX6UL_GPIO_OUT_PAD_CTRL);
1279 }
1280
1281 static void tx6ul_set_cpu_clock(void)
1282 {
1283         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1284
1285         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1286                 return;
1287
1288         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1289                 printf("%s detected; skipping cpu clock change\n",
1290                        (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1291                 return;
1292         }
1293         if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1294                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1295                 printf("CPU clock set to %lu.%03lu MHz\n",
1296                        cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1297         } else {
1298                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1299         }
1300 }
1301
1302 int board_late_init(void)
1303 {
1304         const char *baseboard;
1305
1306         debug("%s@%d: \n", __func__, __LINE__);
1307
1308         env_cleanup();
1309
1310         if (tx6ul_temp_check_enabled)
1311                 check_cpu_temperature(1);
1312
1313         tx6ul_set_cpu_clock();
1314
1315         if (had_ctrlc())
1316                 setenv_ulong("safeboot", 1);
1317         else if (wrsr & WRSR_TOUT)
1318                 setenv_ulong("wdreset", 1);
1319         else
1320                 karo_fdt_move_fdt();
1321
1322         baseboard = getenv("baseboard");
1323         if (!baseboard)
1324                 goto exit;
1325
1326         printf("Baseboard: %s\n", baseboard);
1327
1328         if (strncmp(baseboard, "stk5", 4) == 0) {
1329                 if ((strlen(baseboard) == 4) ||
1330                         strcmp(baseboard, "stk5-v3") == 0) {
1331                         stk5v3_board_init();
1332                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1333                         const char *otg_mode = getenv("otg_mode");
1334
1335                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1336                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1337                                        otg_mode, baseboard);
1338                                 setenv("otg_mode", "none");
1339                         }
1340                         stk5v5_board_init();
1341                 } else {
1342                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1343                                 baseboard + 4);
1344                 }
1345         } else if (strncmp(baseboard, "ulmb-", 5) == 0) {
1346                         const char *otg_mode = getenv("otg_mode");
1347
1348                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1349                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1350                                        otg_mode, baseboard);
1351                                 setenv("otg_mode", "none");
1352                         }
1353                         stk5_board_init();
1354         } else {
1355                 printf("WARNING: Unsupported baseboard: '%s'\n",
1356                         baseboard);
1357                 if (!had_ctrlc())
1358                         return -EINVAL;
1359         }
1360
1361 exit:
1362         debug("%s@%d: \n", __func__, __LINE__);
1363
1364         clear_ctrlc();
1365         return 0;
1366 }
1367
1368 #ifdef CONFIG_FEC_MXC
1369
1370 #ifndef ETH_ALEN
1371 #define ETH_ALEN 6
1372 #endif
1373
1374 static void tx6ul_init_mac(void)
1375 {
1376         u8 mac[ETH_ALEN];
1377         const char *baseboard = getenv("baseboard");
1378
1379         imx_get_mac_from_fuse(0, mac);
1380         if (!is_valid_ethaddr(mac)) {
1381                 printf("No valid MAC address programmed\n");
1382                 return;
1383         }
1384         printf("MAC addr from fuse: %pM\n", mac);
1385         if (!getenv("ethaddr"))
1386                 eth_setenv_enetaddr("ethaddr", mac);
1387
1388         if (!baseboard || strncmp(baseboard, "stk5", 4) == 0) {
1389                 setenv("eth1addr", NULL);
1390                 return;
1391         }
1392         if (getenv("eth1addr"))
1393                 return;
1394         imx_get_mac_from_fuse(1, mac);
1395         eth_setenv_enetaddr("eth1addr", mac);
1396 }
1397
1398 int board_eth_init(bd_t *bis)
1399 {
1400         int ret;
1401
1402         tx6ul_init_mac();
1403
1404         /* delay at least 21ms for the PHY internal POR signal to deassert */
1405         udelay(22000);
1406
1407         imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
1408                                          ARRAY_SIZE(tx6ul_enet1_pads));
1409
1410         /* Deassert RESET to the external phys */
1411         gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
1412
1413         if (getenv("ethaddr")) {
1414                 ret = fecmxc_initialize_multi(bis, 0, 0, ENET_BASE_ADDR);
1415                 if (ret) {
1416                         printf("failed to initialize FEC0: %d\n", ret);
1417                         return ret;
1418                 }
1419         }
1420         if (getenv("eth1addr")) {
1421                 ret = gpio_request_array(tx6ul_fec2_gpios,
1422                                          ARRAY_SIZE(tx6ul_fec2_gpios));
1423                 if (ret < 0) {
1424                         printf("Failed to request tx6ul_fec2_gpios: %d\n", ret);
1425                 }
1426                 imx_iomux_v3_setup_multiple_pads(tx6ul_enet2_pads,
1427                                                  ARRAY_SIZE(tx6ul_enet2_pads));
1428
1429                 writel(0x00100000, 0x020c80e4); /* assert ENET2_125M_EN */
1430
1431                 /* Minimum PHY reset duration */
1432                 udelay(100);
1433                 gpio_set_value(TX6UL_FEC2_RST_GPIO, 1);
1434                 /* Wait for PHY internal POR to finish */
1435                 udelay(22000);
1436
1437                 ret = fecmxc_initialize_multi(bis, 1, 2, ENET2_BASE_ADDR);
1438                 if (ret) {
1439                         printf("failed to initialize FEC1: %d\n", ret);
1440                         return ret;
1441                 }
1442         }
1443         return 0;
1444 }
1445 #endif /* CONFIG_FEC_MXC */
1446
1447 #ifdef CONFIG_SERIAL_TAG
1448 void get_board_serial(struct tag_serialnr *serialnr)
1449 {
1450         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1451         struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1452
1453         serialnr->low = readl(&fuse->cfg0);
1454         serialnr->high = readl(&fuse->cfg1);
1455 }
1456 #endif
1457
1458 #if defined(CONFIG_OF_BOARD_SETUP)
1459 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1460 #include <jffs2/jffs2.h>
1461 #include <mtd_node.h>
1462 static struct node_info nodes[] = {
1463         { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1464 };
1465 #else
1466 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1467 #endif
1468
1469 static const char *tx6ul_touchpanels[] = {
1470         "ti,tsc2007",
1471         "edt,edt-ft5x06",
1472         "eeti,egalax_ts",
1473 };
1474
1475 int ft_board_setup(void *blob, bd_t *bd)
1476 {
1477         const char *baseboard = getenv("baseboard");
1478         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1479         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1480         int ret;
1481
1482         ret = fdt_increase_size(blob, 4096);
1483         if (ret) {
1484                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1485                 return ret;
1486         }
1487         if (stk5_v5)
1488                 karo_fdt_enable_node(blob, "stk5led", 0);
1489
1490         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1491
1492         karo_fdt_fixup_touchpanel(blob, tx6ul_touchpanels,
1493                                   ARRAY_SIZE(tx6ul_touchpanels));
1494         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1495         karo_fdt_fixup_flexcan(blob, stk5_v5);
1496
1497         karo_fdt_update_fb_mode(blob, video_mode, "/lcd-panel");
1498
1499         return 0;
1500 }
1501 #endif /* CONFIG_OF_BOARD_SETUP */