board/kmc/kzm9g/kzm9g.c

   1 /*
   2  * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   3  * (C) Copyright 2012 Renesas Solutions Corp.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/gpio.h>
  28 #include <netdev.h>
  29 #include <i2c.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #define CS0BCR_D (0x06C00400)
  34 #define CS4BCR_D (0x16c90400)
  35 #define CS0WCR_D (0x55062C42)
  36 #define CS4WCR_D (0x1e071dc3)
  37
  38 #define CMNCR_BROMMD0   (1 << 21)
  39 #define CMNCR_BROMMD1   (1 << 22)
  40 #define CMNCR_BROMMD    (CMNCR_BROMMD0|CMNCR_BROMMD1)
  41 #define VCLKCR1_D       (0x27)
  42
  43 #define SMSTPCR1_CMT0   (1 << 24)
  44 #define SMSTPCR1_I2C0   (1 << 16)
  45 #define SMSTPCR3_USB    (1 << 22)
  46 #define SMSTPCR3_I2C1   (1 << 23)
  47
  48 #define PORT32CR (0xE6051020)
  49 #define PORT33CR (0xE6051021)
  50 #define PORT34CR (0xE6051022)
  51 #define PORT35CR (0xE6051023)
  52
  53 static int cmp_loop(u32 *addr, u32 data, u32 cmp)
  54 {
  55         int err = -1;
  56         int timeout = 100;
  57         u32 value;
  58
  59         while (timeout > 0) {
  60                 value = readl(addr);
  61                 if ((value & data) == cmp) {
  62                         err = 0;
  63                         break;
  64                 }
  65                 timeout--;
  66         }
  67
  68         return err;
  69 }
  70
  71 /* SBSC Init function */
  72 static void sbsc_init(struct sh73a0_sbsc *sbsc)
  73 {
  74         writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
  75         writel(0x5, &sbsc->sdgencnt);
  76         cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
  77
  78         writel(0xacc90159, &sbsc->sdcr0);
  79         writel(0x00010059, &sbsc->sdcr1);
  80         writel(0x50874114, &sbsc->sdwcrc0);
  81         writel(0x33199b37, &sbsc->sdwcrc1);
  82         writel(0x008f2313, &sbsc->sdwcrc2);
  83         writel(0x31020707, &sbsc->sdwcr00);
  84         writel(0x0017040a, &sbsc->sdwcr01);
  85         writel(0x31020707, &sbsc->sdwcr10);
  86         writel(0x0017040a, &sbsc->sdwcr11);
  87         writel(0x05555555, &sbsc->sddrvcr0);
  88         writel(0x30000000, &sbsc->sdwcr2);
  89
  90         writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
  91         cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
  92
  93         writel(0x00002710, &sbsc->sdgencnt);
  94         cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
  95
  96         writel(0x0000003f, &sbsc->sdmracr0);
  97         writel(0x0, SDMRA1A);
  98         writel(0x000001f4, &sbsc->sdgencnt);
  99         cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
 100
 101         writel(0x0000ff0a, &sbsc->sdmracr0);
 102         if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
 103                 writel(0x0, SDMRA3A);
 104         else
 105                 writel(0x0, SDMRA3B);
 106
 107         writel(0x00000032, &sbsc->sdgencnt);
 108         cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
 109
 110         if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
 111                 writel(0x00002201, &sbsc->sdmracr0);
 112                 writel(0x0, SDMRA1A);
 113                 writel(0x00000402, &sbsc->sdmracr0);
 114                 writel(0x0, SDMRA1A);
 115                 writel(0x00000403, &sbsc->sdmracr0);
 116                 writel(0x0, SDMRA1A);
 117                 writel(0x0, SDMRA2A);
 118         } else {
 119                 writel(0x00002201, &sbsc->sdmracr0);
 120                 writel(0x0, SDMRA1B);
 121                 writel(0x00000402, &sbsc->sdmracr0);
 122                 writel(0x0, SDMRA1B);
 123                 writel(0x00000403, &sbsc->sdmracr0);
 124                 writel(0x0, SDMRA1B);
 125                 writel(0x0, SDMRA2B);
 126         }
 127
 128         writel(0x88800004, &sbsc->sdmrtmpcr);
 129         writel(0x00000004, &sbsc->sdmrtmpmsk);
 130         writel(0xa55a0032, &sbsc->rtcor);
 131         writel(0xa55a000c, &sbsc->rtcorh);
 132         writel(0xa55a2048, &sbsc->rtcsr);
 133         writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
 134         writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
 135         writel(0xfff20000, &sbsc->zqccr);
 136
 137         /* SCBS2 only */
 138         if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
 139                 writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
 140                 writel(0xa5390000, &sbsc->dphycnt1);
 141                 writel(0x00001200, &sbsc->dphycnt0);
 142                 writel(0x07ce0000, &sbsc->dphycnt1);
 143                 writel(0x00001247, &sbsc->dphycnt0);
 144                 cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
 145                 writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
 146         }
 147 }
 148
 149 void s_init(void)
 150 {
 151         struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
 152         struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
 153         struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
 154                 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
 155         struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
 156         struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
 157         struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
 158         struct sh73a0_hpb_bscr *hpb_bscr =
 159                 (struct sh73a0_hpb_bscr *)HPBSCR_BASE;
 160
 161         /* Watchdog init */
 162         writew(0xA507, &rwdt->rwtcsra0);
 163
 164         /* Secure control register Init */
 165         #define LIFEC_SEC_SRC_BIT       (1 << 15)
 166         writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
 167
 168         clrbits_le32(&cpg->smstpcr3, (1 << 15));
 169         clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
 170         clrbits_le32(&cpg->smstpcr2, (1 << 18));
 171         clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
 172         writel(0x0, &cpg->pllecr);
 173
 174         cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
 175         cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
 176
 177         writel(0x2D000000, &cpg->pll0cr);
 178         writel(0x17100000, &cpg->pll1cr);
 179         writel(0x96235880, &cpg->frqcrb);
 180         cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
 181
 182         writel(0xB, &cpg->flckcr);
 183         clrbits_le32(&cpg->smstpcr0, (1 << 1));
 184
 185         clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
 186         writel(0x0514, &hpb_bscr->smgpiotime);
 187         writel(0x0514, &hpb_bscr->smcmt2time);
 188         writel(0x0514, &hpb_bscr->smcpgtime);
 189         writel(0x0514, &hpb_bscr->smsysctime);
 190
 191         writel(0x00092000, &cpg->dvfscr4);
 192         writel(0x000000DC, &cpg->dvfscr5);
 193         writel(0x0, &cpg->pllecr);
 194         cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
 195
 196         /* FRQCR Init */
 197         writel(0x0012453C, &cpg->frqcra);
 198         writel(0x80331350, &cpg->frqcrb);
 199         cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
 200         writel(0x00000B0B, &cpg->frqcrd);
 201         cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
 202
 203         /* Clock Init */
 204         writel(0x00000003, PCLKCR);
 205         writel(0x0000012F, &cpg->vclkcr1);
 206         writel(0x00000119, &cpg->vclkcr2);
 207         writel(0x00000119, &cpg->vclkcr3);
 208         writel(0x00000002, &cpg->zbckcr);
 209         writel(0x00000005, &cpg->flckcr);
 210         writel(0x00000080, &cpg->sd0ckcr);
 211         writel(0x00000080, &cpg->sd1ckcr);
 212         writel(0x00000080, &cpg->sd2ckcr);
 213         writel(0x0000003F, &cpg->fsiackcr);
 214         writel(0x0000003F, &cpg->fsibckcr);
 215         writel(0x00000080, &cpg->subckcr);
 216         writel(0x0000000B, &cpg->spuackcr);
 217         writel(0x0000000B, &cpg->spuvckcr);
 218         writel(0x0000013F, &cpg->msuckcr);
 219         writel(0x00000080, &cpg->hsickcr);
 220         writel(0x0000003F, &cpg->mfck1cr);
 221         writel(0x0000003F, &cpg->mfck2cr);
 222         writel(0x00000107, &cpg->dsitckcr);
 223         writel(0x00000313, &cpg->dsi0pckcr);
 224         writel(0x0000130D, &cpg->dsi1pckcr);
 225         writel(0x2A800E0E, &cpg->dsi0phycr);
 226         writel(0x1E000000, &cpg->pll0cr);
 227         writel(0x2D000000, &cpg->pll0cr);
 228         writel(0x17100000, &cpg->pll1cr);
 229         writel(0x27000080, &cpg->pll2cr);
 230         writel(0x1D000000, &cpg->pll3cr);
 231         writel(0x00080000, &cpg->pll0stpcr);
 232         writel(0x000120C0, &cpg->pll1stpcr);
 233         writel(0x00012000, &cpg->pll2stpcr);
 234         writel(0x00000030, &cpg->pll3stpcr);
 235
 236         writel(0x0000000B, &cpg->pllecr);
 237         cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
 238
 239         writel(0x000120F0, &cpg->dvfscr3);
 240         writel(0x00000020, &cpg->mpmode);
 241         writel(0x0000028A, &cpg->vrefcr);
 242         writel(0xE4628087, &cpg->rmstpcr0);
 243         writel(0xFFFFFFFF, &cpg->rmstpcr1);
 244         writel(0x53FFFFFF, &cpg->rmstpcr2);
 245         writel(0xFFFFFFFF, &cpg->rmstpcr3);
 246         writel(0x00800D3D, &cpg->rmstpcr4);
 247         writel(0xFFFFF3FF, &cpg->rmstpcr5);
 248         writel(0x00000000, &cpg->smstpcr2);
 249         writel(0x00040000, &cpg_srcr->srcr2);
 250
 251         clrbits_le32(&cpg->pllecr, (1 << 3));
 252         cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
 253
 254         writel(0x00000001, &hpb->hpbctrl6);
 255         cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
 256
 257         writel(0x00001414, &cpg->frqcrd);
 258         cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
 259
 260         writel(0x1d000000, &cpg->pll3cr);
 261         setbits_le32(&cpg->pllecr, (1 << 3));
 262         cmp_loop(&cpg->pllecr, 0x800, 0x800);
 263
 264         /* SBSC1 Init*/
 265         sbsc_init(sbsc1);
 266
 267         /* SBSC2 Init*/
 268         sbsc_init(sbsc2);
 269
 270         writel(0x00000b0b, &cpg->frqcrd);
 271         cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
 272         writel(0xfffffffc, &cpg->cpgxxcs4);
 273 }
 274
 275 int board_early_init_f(void)
 276 {
 277         struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
 278         struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
 279         struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
 280                 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
 281
 282         writel(CS0BCR_D, &bsc->cs0bcr);
 283         writel(CS4BCR_D, &bsc->cs4bcr);
 284         writel(CS0WCR_D, &bsc->cs0wcr);
 285         writel(CS4WCR_D, &bsc->cs4wcr);
 286
 287         clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
 288
 289         clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
 290         clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
 291         clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
 292         clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
 293         writel(VCLKCR1_D, &cpg->vclkcr1);
 294
 295         /* Setup SCIF4 / workaround */
 296         writeb(0x12, PORT32CR);
 297         writeb(0x22, PORT33CR);
 298         writeb(0x12, PORT34CR);
 299         writeb(0x22, PORT35CR);
 300
 301         return 0;
 302 }
 303
 304 int board_init(void)
 305 {
 306         sh73a0_pinmux_init();
 307
 308     /* SCIFA 4 */
 309         gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
 310         gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
 311         gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
 312         gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
 313
 314         /* Ethernet/SMSC */
 315         gpio_request(GPIO_PORT224, NULL);
 316         gpio_direction_input(GPIO_PORT224);
 317
 318         /* SMSC/USB */
 319         gpio_request(GPIO_FN_CS4_, NULL);
 320
 321         /* MMCIF */
 322         gpio_request(GPIO_FN_MMCCLK0, NULL);
 323         gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
 324         gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
 325         gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
 326         gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
 327         gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
 328         gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
 329         gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
 330         gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
 331         gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
 332
 333         /* SDHI */
 334         gpio_request(GPIO_FN_SDHIWP0, NULL);
 335         gpio_request(GPIO_FN_SDHICD0, NULL);
 336         gpio_request(GPIO_FN_SDHICMD0, NULL);
 337         gpio_request(GPIO_FN_SDHICLK0,  NULL);
 338         gpio_request(GPIO_FN_SDHID0_3,  NULL);
 339         gpio_request(GPIO_FN_SDHID0_2,  NULL);
 340         gpio_request(GPIO_FN_SDHID0_1,  NULL);
 341         gpio_request(GPIO_FN_SDHID0_0,  NULL);
 342         gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
 343         gpio_request(GPIO_PORT15, NULL);
 344         gpio_direction_output(GPIO_PORT15, 1);
 345
 346         /* I2C */
 347         gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
 348         gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
 349         gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
 350         gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
 351
 352         gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 353
 354         return 0;
 355 }
 356
 357 const struct rmobile_sysinfo sysinfo = {
 358         CONFIG_RMOBILE_BOARD_STRING
 359 };
 360
 361 int dram_init(void)
 362 {
 363         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 364         return 0;
 365 }
 366
 367 int board_eth_init(bd_t *bis)
 368 {
 369         int ret = 0;
 370 #ifdef CONFIG_SMC911X
 371         ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 372 #endif
 373         return ret;
 374 }
 375
 376 void reset_cpu(ulong addr)
 377 {
 378         /* Soft Power On Reset */
 379         writel((1 << 31), RESCNT2);
 380 }