board/linkstation/ide.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 /* ide.c - ide support functions */
   8
   9
  10 #include <common.h>
  11
  12 #ifdef CONFIG_CMD_IDE
  13 #include <ata.h>
  14 #include <ide.h>
  15 #include <pci.h>
  16
  17 #define IT8212_PCI_CpuCONTROL           0x5e
  18 #define IT8212_PCI_PciModeCONTROL       0x50
  19 #define IT8212_PCI_IdeIoCONFIG          0x40
  20 #define IT8212_PCI_IdeBusSkewCONTROL    0x4c
  21 #define IT8212_PCI_IdeDrivingCURRENT    0x42
  22
  23 extern struct pci_controller hose;
  24
  25 int ide_preinit (void)
  26 {
  27         int status;
  28         pci_dev_t devbusfn;
  29         int l;
  30
  31         status = 1;
  32         for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
  33                 ide_bus_offset[l] = -ATA_STATUS;
  34         }
  35         devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0);
  36         if (devbusfn == -1)
  37                 devbusfn = pci_find_device(PCI_VENDOR_ID_ITE,PCI_DEVICE_ID_ITE_8212,0);
  38         if (devbusfn != -1) {
  39                 u32 ide_bus_offset32;
  40
  41                 status = 0;
  42
  43                 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
  44                                                            &ide_bus_offset32);
  45                 ide_bus_offset[0] = ide_bus_offset32 & 0xfffffffe;
  46                 ide_bus_offset[0] = pci_hose_bus_to_phys(&hose,
  47                                                 ide_bus_offset[0] & 0xfffffffe,
  48                                                 PCI_REGION_IO);
  49                 if (CONFIG_SYS_IDE_MAXBUS > 1) {
  50                         pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2,
  51                                               (u32 *) &ide_bus_offset[1]);
  52                         ide_bus_offset[1] &= 0xfffffffe;
  53                         ide_bus_offset[1] = pci_hose_bus_to_phys(&hose,
  54                                                 ide_bus_offset[1] & 0xfffffffe,
  55                                                 PCI_REGION_IO);
  56                 }
  57         }
  58
  59         if (pci_find_device (PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, 0) != -1) {
  60                 pci_write_config_byte(devbusfn, IT8212_PCI_CpuCONTROL, 0x01);
  61                 pci_write_config_byte(devbusfn, IT8212_PCI_PciModeCONTROL, 0x00);
  62                 pci_write_config_word(devbusfn, PCI_COMMAND, 0x0047);
  63 #ifdef CONFIG_IT8212_SECONDARY_ENABLE
  64                 pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0xA0F3);
  65 #else
  66                 pci_write_config_word(devbusfn, IT8212_PCI_IdeIoCONFIG, 0x8031);
  67 #endif
  68                 pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204);
  69 /* __LS_COMMENT__ BUFFALO changed 2004.11.10  changed for EMI */
  70                 pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */
  71 /*              pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */
  72 /*              pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */
  73 /*              pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */
  74 /*              pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */
  75                 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00);
  76         }
  77
  78         return (status);
  79 }
  80
  81 void ide_set_reset (int flag) {
  82         return;
  83 }
  84
  85 #endif /* CONFIG_CMD_IDE */