board/mimc/mimc200/mimc200.c

   1 /*
   2  * Copyright (C) 2006 Atmel Corporation
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #include <common.h>
  23 #include <netdev.h>
  24
  25 #include <asm/io.h>
  26 #include <asm/sdram.h>
  27 #include <asm/arch/clk.h>
  28 #include <asm/arch/gpio.h>
  29 #include <asm/arch/hmatrix.h>
  30 #include <asm/arch/mmu.h>
  31 #include <asm/arch/portmux.h>
  32 #include <atmel_lcdc.h>
  33 #include <lcd.h>
  34
  35 #include "../../../arch/avr32/cpu/hsmc3.h"
  36
  37 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  38         {
  39                 .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
  40                 .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
  41                 .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
  42                                         | MMU_VMR_CACHE_NONE,
  43         }, {
  44                 .virt_pgno      = EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
  45                 .nr_pages       = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
  46                 .phys           = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
  47                                         | MMU_VMR_CACHE_NONE,
  48         }, {
  49                 .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
  50                 .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
  51                 .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
  52                                         | MMU_VMR_CACHE_WRBACK,
  53         },
  54 };
  55
  56 #if defined(CONFIG_LCD)
  57 /* 480x272x16 @ 72 Hz */
  58 vidinfo_t panel_info = {
  59         .vl_col                 = 480,          /* Number of columns */
  60         .vl_row                 = 272,          /* Number of rows */
  61         .vl_clk                 = 5000000,      /* pixel clock in ps */
  62         .vl_sync                = ATMEL_LCDC_INVCLK_INVERTED |
  63                                   ATMEL_LCDC_INVLINE_INVERTED |
  64                                   ATMEL_LCDC_INVFRAME_INVERTED,
  65         .vl_bpix                = LCD_COLOR16,  /* Bits per pixel, BPP = 2^n */
  66         .vl_tft                 = 1,            /* 0 = passive, 1 = TFT */
  67         .vl_hsync_len           = 42,           /* Length of horizontal sync */
  68         .vl_left_margin         = 1,            /* Time from sync to picture */
  69         .vl_right_margin        = 1,            /* Time from picture to sync */
  70         .vl_vsync_len           = 1,            /* Length of vertical sync */
  71         .vl_upper_margin        = 12,           /* Time from sync to picture */
  72         .vl_lower_margin        = 1,            /* Time from picture to sync */
  73         .mmio                   = LCDC_BASE,    /* Memory mapped registers */
  74 };
  75
  76 void lcd_enable(void)
  77 {
  78 }
  79
  80 void lcd_disable(void)
  81 {
  82 }
  83 #endif
  84
  85 DECLARE_GLOBAL_DATA_PTR;
  86
  87 static const struct sdram_config sdram_config = {
  88         .data_bits      = SDRAM_DATA_16BIT,
  89         .row_bits       = 13,
  90         .col_bits       = 9,
  91         .bank_bits      = 2,
  92         .cas            = 3,
  93         .twr            = 2,
  94         .trc            = 6,
  95         .trp            = 2,
  96         .trcd           = 2,
  97         .tras           = 6,
  98         .txsr           = 6,
  99         /* 15.6 us */
 100         .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
 101 };
 102
 103 int board_early_init_f(void)
 104 {
 105         /* Enable SDRAM in the EBI mux */
 106         hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
 107
 108         /* Enable 26 address bits and NCS2 */
 109         portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
 110         portmux_enable_usart1(PORTMUX_DRIVE_MIN);
 111
 112         /* de-assert "force sys reset" pin */
 113         portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
 114                         PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
 115
 116         /* init custom i/o */
 117         /* cpu type inputs */
 118         portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
 119                         PORTMUX_DIR_INPUT);
 120         /* main board type inputs */
 121         portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
 122                         PORTMUX_DIR_INPUT);
 123         /* DEBUG input (use weak pullup) */
 124         portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
 125                         PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
 126
 127         /* are we suppressing the console ? */
 128         if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
 129                 gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
 130
 131         /* reset phys */
 132         portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
 133         portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
 134                         PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
 135
 136         udelay(5000);
 137
 138         /* release phys reset */
 139         gpio_set_value(GPIO_PIN_PC(18), 0);     /* PHY RESET (Release)  */
 140
 141         /* setup Data Flash chip select (NCS2) */
 142         hsmc3_writel(MODE2, 0x20121003);
 143         hsmc3_writel(CYCLE2, 0x000a0009);
 144         hsmc3_writel(PULSE2, 0x0a060806);
 145         hsmc3_writel(SETUP2, 0x00030102);
 146
 147         /* setup FRAM chip select (NCS3) */
 148         hsmc3_writel(MODE3, 0x10120001);
 149         hsmc3_writel(CYCLE3, 0x001e001d);
 150         hsmc3_writel(PULSE3, 0x08040704);
 151         hsmc3_writel(SETUP3, 0x02050204);
 152
 153 #if defined(CONFIG_MACB)
 154         /* init macb0 pins */
 155         portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
 156         portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
 157 #endif
 158
 159 #if defined(CONFIG_MMC)
 160         portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
 161 #endif
 162
 163 #if defined(CONFIG_LCD)
 164         portmux_enable_lcdc(1);
 165 #endif
 166
 167         return 0;
 168 }
 169
 170 phys_size_t initdram(int board_type)
 171 {
 172         unsigned long expected_size;
 173         unsigned long actual_size;
 174         void *sdram_base;
 175
 176         sdram_base = uncached(EBI_SDRAM_BASE);
 177
 178         expected_size = sdram_init(sdram_base, &sdram_config);
 179         actual_size = get_ram_size(sdram_base, expected_size);
 180
 181         if (expected_size != actual_size)
 182                 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
 183                                 actual_size >> 20, expected_size >> 20);
 184
 185         return actual_size;
 186 }
 187
 188 int board_early_init_r(void)
 189 {
 190         gd->bd->bi_phy_id[0] = 0x01;
 191         gd->bd->bi_phy_id[1] = 0x03;
 192         return 0;
 193 }
 194
 195 int board_postclk_init(void)
 196 {
 197         /* Use GCLK0 as 10MHz output */
 198         gclk_enable_output(0, PORTMUX_DRIVE_LOW);
 199         gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
 200         return 0;
 201 }
 202
 203 /* SPI chip select control */
 204 #ifdef CONFIG_ATMEL_SPI
 205 #include <spi.h>
 206
 207 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 208 {
 209         return (bus == 0) && (cs == 0);
 210 }
 211
 212 void spi_cs_activate(struct spi_slave *slave)
 213 {
 214 }
 215
 216 void spi_cs_deactivate(struct spi_slave *slave)
 217 {
 218 }
 219 #endif /* CONFIG_ATMEL_SPI */
 220
 221 #ifdef CONFIG_CMD_NET
 222 int board_eth_init(bd_t *bi)
 223 {
 224         macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
 225         macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
 226
 227         return 0;
 228 }
 229 #endif