2 * Copyright (C) 2006 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/sdram.h>
27 #include <asm/arch/clk.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/hmatrix.h>
30 #include <asm/arch/portmux.h>
31 #include <atmel_lcdc.h>
34 #include "../../../arch/avr32/cpu/hsmc3.h"
36 #if defined(CONFIG_LCD)
37 /* 480x272x16 @ 72 Hz */
38 vidinfo_t panel_info = {
39 .vl_col = 480, /* Number of columns */
40 .vl_row = 272, /* Number of rows */
41 .vl_clk = 5000000, /* pixel clock in ps */
42 .vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
43 ATMEL_LCDC_INVLINE_INVERTED |
44 ATMEL_LCDC_INVFRAME_INVERTED,
45 .vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */
46 .vl_tft = 1, /* 0 = passive, 1 = TFT */
47 .vl_hsync_len = 42, /* Length of horizontal sync */
48 .vl_left_margin = 1, /* Time from sync to picture */
49 .vl_right_margin = 1, /* Time from picture to sync */
50 .vl_vsync_len = 1, /* Length of vertical sync */
51 .vl_upper_margin = 12, /* Time from sync to picture */
52 .vl_lower_margin = 1, /* Time from picture to sync */
53 .mmio = LCDC_BASE, /* Memory mapped registers */
60 void lcd_disable(void)
65 DECLARE_GLOBAL_DATA_PTR;
67 static const struct sdram_config sdram_config = {
68 .data_bits = SDRAM_DATA_16BIT,
80 .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
83 int board_early_init_f(void)
85 /* Enable SDRAM in the EBI mux */
86 hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
88 /* Enable 26 address bits and NCS2 */
89 portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
90 portmux_enable_usart1(PORTMUX_DRIVE_MIN);
92 /* de-assert "force sys reset" pin */
93 portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
94 PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
98 portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
100 /* main board type inputs */
101 portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
103 /* DEBUG input (use weak pullup) */
104 portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
105 PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
107 /* are we suppressing the console ? */
108 if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
109 gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
112 portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
113 portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
114 PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
118 /* release phys reset */
119 gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
121 /* setup Data Flash chip select (NCS2) */
122 hsmc3_writel(MODE2, 0x20121003);
123 hsmc3_writel(CYCLE2, 0x000a0009);
124 hsmc3_writel(PULSE2, 0x0a060806);
125 hsmc3_writel(SETUP2, 0x00030102);
127 /* setup FRAM chip select (NCS3) */
128 hsmc3_writel(MODE3, 0x10120001);
129 hsmc3_writel(CYCLE3, 0x001e001d);
130 hsmc3_writel(PULSE3, 0x08040704);
131 hsmc3_writel(SETUP3, 0x02050204);
133 #if defined(CONFIG_MACB)
134 /* init macb0 pins */
135 portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
136 portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
139 #if defined(CONFIG_MMC)
140 portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
143 #if defined(CONFIG_LCD)
144 portmux_enable_lcdc(1);
150 phys_size_t initdram(int board_type)
152 unsigned long expected_size;
153 unsigned long actual_size;
156 sdram_base = uncached(EBI_SDRAM_BASE);
158 expected_size = sdram_init(sdram_base, &sdram_config);
159 actual_size = get_ram_size(sdram_base, expected_size);
161 if (expected_size != actual_size)
162 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
163 actual_size >> 20, expected_size >> 20);
168 int board_early_init_r(void)
170 gd->bd->bi_phy_id[0] = 0x01;
171 gd->bd->bi_phy_id[1] = 0x03;
175 int board_postclk_init(void)
177 /* Use GCLK0 as 10MHz output */
178 gclk_enable_output(0, PORTMUX_DRIVE_LOW);
179 gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
183 /* SPI chip select control */
184 #ifdef CONFIG_ATMEL_SPI
187 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
189 return (bus == 0) && (cs == 0);
192 void spi_cs_activate(struct spi_slave *slave)
196 void spi_cs_deactivate(struct spi_slave *slave)
199 #endif /* CONFIG_ATMEL_SPI */
201 #ifdef CONFIG_CMD_NET
202 int board_eth_init(bd_t *bi)
204 macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
205 macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);