board/renesas/koelsch/koelsch.c

   1 /*
   2  * board/renesas/koelsch/koelsch.c
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  *
   6  * SPDX-License-Identifier: GPL-2.0
   7  *
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <asm/processor.h>
  13 #include <asm/mach-types.h>
  14 #include <asm/io.h>
  15 #include <asm/errno.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/rmobile.h>
  19 #include <i2c.h>
  20 #include "qos.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define s_init_wait(cnt) \
  25         ({      \
  26                 u32 i = 0x10000 * cnt;  \
  27                 while (i > 0)   \
  28                         i--;    \
  29         })
  30
  31
  32 #define dbpdrgd_check(bsc) \
  33         ({      \
  34                 while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1)     \
  35                         ;       \
  36         })
  37
  38 #if defined(CONFIG_NORFLASH)
  39 static void bsc_init(void)
  40 {
  41         struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
  42         struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
  43
  44         /* LBSC */
  45         writel(0x00000020, &lbsc->cs0ctrl);
  46         writel(0x00000020, &lbsc->cs1ctrl);
  47         writel(0x00002020, &lbsc->ecs0ctrl);
  48         writel(0x00002020, &lbsc->ecs1ctrl);
  49
  50         writel(0x077F077F, &lbsc->cswcr0);
  51         writel(0x077F077F, &lbsc->cswcr1);
  52         writel(0x077F077F, &lbsc->ecswcr0);
  53         writel(0x077F077F, &lbsc->ecswcr1);
  54
  55         /* DBSC3 */
  56         s_init_wait(10);
  57
  58         writel(0x0000A55A, &dbsc3_0->dbpdlck);
  59         writel(0x00000001, &dbsc3_0->dbpdrga);
  60         writel(0x80000000, &dbsc3_0->dbpdrgd);
  61         writel(0x00000004, &dbsc3_0->dbpdrga);
  62         dbpdrgd_check(dbsc3_0);
  63
  64         writel(0x00000006, &dbsc3_0->dbpdrga);
  65         writel(0x0001C000, &dbsc3_0->dbpdrgd);
  66
  67         writel(0x00000023, &dbsc3_0->dbpdrga);
  68         writel(0x00FD2480, &dbsc3_0->dbpdrgd);
  69
  70         writel(0x00000010, &dbsc3_0->dbpdrga);
  71         writel(0xF004649B, &dbsc3_0->dbpdrgd);
  72
  73         writel(0x0000000F, &dbsc3_0->dbpdrga);
  74         writel(0x00181EE4, &dbsc3_0->dbpdrgd);
  75
  76         writel(0x0000000E, &dbsc3_0->dbpdrga);
  77         writel(0x33C03812, &dbsc3_0->dbpdrgd);
  78
  79         writel(0x00000003, &dbsc3_0->dbpdrga);
  80         writel(0x0300C481, &dbsc3_0->dbpdrgd);
  81
  82         writel(0x00000007, &dbsc3_0->dbkind);
  83         writel(0x10030A02, &dbsc3_0->dbconf0);
  84         writel(0x00000001, &dbsc3_0->dbphytype);
  85         writel(0x00000000, &dbsc3_0->dbbl);
  86         writel(0x0000000B, &dbsc3_0->dbtr0);
  87         writel(0x00000008, &dbsc3_0->dbtr1);
  88         writel(0x00000000, &dbsc3_0->dbtr2);
  89         writel(0x0000000B, &dbsc3_0->dbtr3);
  90         writel(0x000C000B, &dbsc3_0->dbtr4);
  91         writel(0x00000027, &dbsc3_0->dbtr5);
  92         writel(0x0000001C, &dbsc3_0->dbtr6);
  93         writel(0x00000005, &dbsc3_0->dbtr7);
  94         writel(0x00000018, &dbsc3_0->dbtr8);
  95         writel(0x00000008, &dbsc3_0->dbtr9);
  96         writel(0x0000000C, &dbsc3_0->dbtr10);
  97         writel(0x00000009, &dbsc3_0->dbtr11);
  98         writel(0x00000012, &dbsc3_0->dbtr12);
  99         writel(0x000000D0, &dbsc3_0->dbtr13);
 100         writel(0x00140005, &dbsc3_0->dbtr14);
 101         writel(0x00050004, &dbsc3_0->dbtr15);
 102         writel(0x70233005, &dbsc3_0->dbtr16);
 103         writel(0x000C0000, &dbsc3_0->dbtr17);
 104         writel(0x00000300, &dbsc3_0->dbtr18);
 105         writel(0x00000040, &dbsc3_0->dbtr19);
 106         writel(0x00000001, &dbsc3_0->dbrnk0);
 107         writel(0x00020001, &dbsc3_0->dbadj0);
 108         writel(0x20082008, &dbsc3_0->dbadj2);
 109         writel(0x00020002, &dbsc3_0->dbwt0cnf0);
 110         writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
 111
 112         writel(0x00000015, &dbsc3_0->dbpdrga);
 113         writel(0x00000D70, &dbsc3_0->dbpdrgd);
 114
 115         writel(0x00000016, &dbsc3_0->dbpdrga);
 116         writel(0x00000006, &dbsc3_0->dbpdrgd);
 117
 118         writel(0x00000017, &dbsc3_0->dbpdrga);
 119         writel(0x00000018, &dbsc3_0->dbpdrgd);
 120
 121         writel(0x00000012, &dbsc3_0->dbpdrga);
 122         writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
 123
 124         writel(0x00000013, &dbsc3_0->dbpdrga);
 125         writel(0x1A868300, &dbsc3_0->dbpdrgd);
 126
 127         writel(0x00000023, &dbsc3_0->dbpdrga);
 128         writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
 129
 130         writel(0x00000014, &dbsc3_0->dbpdrga);
 131         writel(0x300214D8, &dbsc3_0->dbpdrgd);
 132
 133         writel(0x0000001A, &dbsc3_0->dbpdrga);
 134         writel(0x930035C7, &dbsc3_0->dbpdrgd);
 135
 136         writel(0x00000060, &dbsc3_0->dbpdrga);
 137         writel(0x330657B2, &dbsc3_0->dbpdrgd);
 138
 139         writel(0x00000011, &dbsc3_0->dbpdrga);
 140         writel(0x1000040B, &dbsc3_0->dbpdrgd);
 141
 142         writel(0x0000FA00, &dbsc3_0->dbcmd);
 143         writel(0x00000001, &dbsc3_0->dbpdrga);
 144         writel(0x00000071, &dbsc3_0->dbpdrgd);
 145
 146         writel(0x00000004, &dbsc3_0->dbpdrga);
 147         dbpdrgd_check(dbsc3_0);
 148
 149         writel(0x0000FA00, &dbsc3_0->dbcmd);
 150         writel(0x2100FA00, &dbsc3_0->dbcmd);
 151         writel(0x0000FA00, &dbsc3_0->dbcmd);
 152         writel(0x0000FA00, &dbsc3_0->dbcmd);
 153         writel(0x0000FA00, &dbsc3_0->dbcmd);
 154         writel(0x0000FA00, &dbsc3_0->dbcmd);
 155         writel(0x0000FA00, &dbsc3_0->dbcmd);
 156         writel(0x0000FA00, &dbsc3_0->dbcmd);
 157         writel(0x0000FA00, &dbsc3_0->dbcmd);
 158
 159         writel(0x110000DB, &dbsc3_0->dbcmd);
 160
 161         writel(0x00000001, &dbsc3_0->dbpdrga);
 162         writel(0x00000181, &dbsc3_0->dbpdrgd);
 163
 164         writel(0x00000004, &dbsc3_0->dbpdrga);
 165         dbpdrgd_check(dbsc3_0);
 166
 167         writel(0x00000001, &dbsc3_0->dbpdrga);
 168         writel(0x0000FE01, &dbsc3_0->dbpdrgd);
 169
 170         writel(0x00000004, &dbsc3_0->dbpdrga);
 171         dbpdrgd_check(dbsc3_0);
 172
 173         writel(0x00000000, &dbsc3_0->dbbs0cnt1);
 174         writel(0x01004C20, &dbsc3_0->dbcalcnf);
 175         writel(0x014000AA, &dbsc3_0->dbcaltr);
 176         writel(0x00000140, &dbsc3_0->dbrfcnf0);
 177         writel(0x00081860, &dbsc3_0->dbrfcnf1);
 178         writel(0x00010000, &dbsc3_0->dbrfcnf2);
 179         writel(0x00000001, &dbsc3_0->dbrfen);
 180         writel(0x00000001, &dbsc3_0->dbacen);
 181 }
 182 #else
 183 #define bsc_init() do {} while (0)
 184 #endif /* CONFIG_NORFLASH */
 185
 186 void s_init(void)
 187 {
 188         struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
 189         struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
 190
 191         /* Watchdog init */
 192         writel(0xA5A5A500, &rwdt->rwtcsra);
 193         writel(0xA5A5A500, &swdt->swtcsra);
 194
 195         /* QoS */
 196         qos_init();
 197
 198         /* BSC */
 199         bsc_init();
 200 }
 201
 202 #define MSTPSR1         0xE6150038
 203 #define SMSTPCR1        0xE6150134
 204 #define TMU0_MSTP125    (1 << 25)
 205
 206 #define MSTPSR7         0xE61501C4
 207 #define SMSTPCR7        0xE615014C
 208 #define SCIF0_MSTP721   (1 << 21)
 209
 210 #define PMMR    0xE6060000
 211 #define GPSR4   0xE6060014
 212 #define IPSR14  0xE6060058
 213
 214 #define set_guard_reg(addr, mask, value)        \
 215 { \
 216         u32 val; \
 217         val = (readl(addr) & ~(mask)) | (value); \
 218         writel(~val, PMMR); \
 219         writel(val, addr); \
 220 }
 221
 222 #define mstp_setbits(type, addr, saddr, set) \
 223         out_##type((saddr), in_##type(addr) | (set))
 224 #define mstp_clrbits(type, addr, saddr, clear) \
 225         out_##type((saddr), in_##type(addr) & ~(clear))
 226 #define mstp_setbits_le32(addr, saddr, set) \
 227         mstp_setbits(le32, addr, saddr, set)
 228 #define mstp_clrbits_le32(addr, saddr, clear)   \
 229         mstp_clrbits(le32, addr, saddr, clear)
 230
 231 int board_early_init_f(void)
 232 {
 233         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 234
 235 #if defined(CONFIG_NORFLASH)
 236         /* SCIF0 */
 237         set_guard_reg(GPSR4, 0x34000000, 0x00000000);
 238         set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
 239         set_guard_reg(GPSR4, 0x00000000, 0x34000000);
 240 #endif
 241
 242         mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
 243
 244         return 0;
 245 }
 246
 247 int board_init(void)
 248 {
 249         /* adress of boot parameters */
 250         gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
 251
 252         /* Init PFC controller */
 253         r8a7791_pinmux_init();
 254
 255         return 0;
 256 }
 257
 258 int dram_init(void)
 259 {
 260         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 261         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 262
 263         return 0;
 264 }
 265
 266 const struct rmobile_sysinfo sysinfo = {
 267         CONFIG_RMOBILE_BOARD_STRING
 268 };
 269
 270 void dram_init_banksize(void)
 271 {
 272         gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
 273         gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
 274 }
 275
 276 int board_late_init(void)
 277 {
 278         return 0;
 279 }
 280
 281 void reset_cpu(ulong addr)
 282 {
 283 }