board/ronetix/pm9261/pm9261.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
   6  * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/sizes.h>
  13 #include <asm/io.h>
  14 #include <asm/gpio.h>
  15 #include <asm/arch/at91sam9_smc.h>
  16 #include <asm/arch/at91_common.h>
  17 #include <asm/arch/at91_pmc.h>
  18 #include <asm/arch/at91_rstc.h>
  19 #include <asm/arch/at91_matrix.h>
  20 #include <asm/arch/clk.h>
  21 #include <asm/arch/gpio.h>
  22
  23 #include <lcd.h>
  24 #include <atmel_lcdc.h>
  25 #include <dataflash.h>
  26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  27 #include <net.h>
  28 #endif
  29 #include <netdev.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 /* ------------------------------------------------------------------------- */
  34 /*
  35  * Miscelaneous platform dependent initialisations
  36  */
  37
  38 #ifdef CONFIG_CMD_NAND
  39 static void pm9261_nand_hw_init(void)
  40 {
  41         unsigned long csa;
  42         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  43         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  44         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  45
  46         /* Enable CS3 */
  47         csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
  48         writel(csa, &matrix->csa);
  49
  50         /* Configure SMC CS3 for NAND/SmartMedia */
  51         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  52                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  53                 &smc->cs[3].setup);
  54
  55         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  56                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  57                 &smc->cs[3].pulse);
  58
  59         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  60                 &smc->cs[3].cycle);
  61
  62         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  63                 AT91_SMC_MODE_EXNW_DISABLE |
  64 #ifdef CONFIG_SYS_NAND_DBW_16
  65                 AT91_SMC_MODE_DBW_16 |
  66 #else /* CONFIG_SYS_NAND_DBW_8 */
  67                 AT91_SMC_MODE_DBW_8 |
  68 #endif
  69                 AT91_SMC_MODE_TDF_CYCLE(2),
  70                 &smc->cs[3].mode);
  71
  72         writel(1 << ATMEL_ID_PIOA |
  73                 1 << ATMEL_ID_PIOC,
  74                 &pmc->pcer);
  75
  76         /* Configure RDY/BSY */
  77         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  78
  79         /* Enable NandFlash */
  80         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  81
  82         at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* NANDOE */
  83         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* NANDWE */
  84 }
  85 #endif
  86
  87
  88 #ifdef CONFIG_DRIVER_DM9000
  89 static void pm9261_dm9000_hw_init(void)
  90 {
  91         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  92         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  93
  94         /* Configure SMC CS2 for DM9000 */
  95         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  96                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  97                 &smc->cs[2].setup);
  98
  99         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
 100                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
 101                 &smc->cs[2].pulse);
 102
 103         writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
 104                 &smc->cs[2].cycle);
 105
 106         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 107                 AT91_SMC_MODE_EXNW_DISABLE |
 108                 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 109                 AT91_SMC_MODE_TDF_CYCLE(1),
 110                 &smc->cs[2].mode);
 111
 112         /* Configure Interrupt pin as input, no pull-up */
 113         writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
 114         at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
 115 }
 116 #endif
 117
 118 #ifdef CONFIG_LCD
 119 vidinfo_t panel_info = {
 120         vl_col:         240,
 121         vl_row:         320,
 122         vl_clk:         4965000,
 123         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 124                         ATMEL_LCDC_INVFRAME_INVERTED,
 125         vl_bpix:        3,
 126         vl_tft:         1,
 127         vl_hsync_len:   5,
 128         vl_left_margin: 1,
 129         vl_right_margin:33,
 130         vl_vsync_len:   1,
 131         vl_upper_margin:1,
 132         vl_lower_margin:0,
 133         mmio:           ATMEL_BASE_LCDC,
 134 };
 135
 136 void lcd_enable(void)
 137 {
 138         at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
 139 }
 140
 141 void lcd_disable(void)
 142 {
 143         at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
 144 }
 145
 146 static void pm9261_lcd_hw_init(void)
 147 {
 148         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 149
 150         at91_set_a_periph(AT91_PIO_PORTB, 1, 0);        /* LCDHSYNC */
 151         at91_set_a_periph(AT91_PIO_PORTB, 2, 0);        /* LCDDOTCK */
 152         at91_set_a_periph(AT91_PIO_PORTB, 3, 0);        /* LCDDEN */
 153         at91_set_a_periph(AT91_PIO_PORTB, 4, 0);        /* LCDCC */
 154         at91_set_a_periph(AT91_PIO_PORTB, 7, 0);        /* LCDD2 */
 155         at91_set_a_periph(AT91_PIO_PORTB, 8, 0);        /* LCDD3 */
 156         at91_set_a_periph(AT91_PIO_PORTB, 9, 0);        /* LCDD4 */
 157         at91_set_a_periph(AT91_PIO_PORTB, 10, 0);       /* LCDD5 */
 158         at91_set_a_periph(AT91_PIO_PORTB, 11, 0);       /* LCDD6 */
 159         at91_set_a_periph(AT91_PIO_PORTB, 12, 0);       /* LCDD7 */
 160         at91_set_a_periph(AT91_PIO_PORTB, 15, 0);       /* LCDD10 */
 161         at91_set_a_periph(AT91_PIO_PORTB, 16, 0);       /* LCDD11 */
 162         at91_set_a_periph(AT91_PIO_PORTB, 17, 0);       /* LCDD12 */
 163         at91_set_a_periph(AT91_PIO_PORTB, 18, 0);       /* LCDD13 */
 164         at91_set_a_periph(AT91_PIO_PORTB, 19, 0);       /* LCDD14 */
 165         at91_set_a_periph(AT91_PIO_PORTB, 20, 0);       /* LCDD15 */
 166         at91_set_b_periph(AT91_PIO_PORTB, 23, 0);       /* LCDD18 */
 167         at91_set_b_periph(AT91_PIO_PORTB, 24, 0);       /* LCDD19 */
 168         at91_set_b_periph(AT91_PIO_PORTB, 25, 0);       /* LCDD20 */
 169         at91_set_b_periph(AT91_PIO_PORTB, 26, 0);       /* LCDD21 */
 170         at91_set_b_periph(AT91_PIO_PORTB, 27, 0);       /* LCDD22 */
 171         at91_set_b_periph(AT91_PIO_PORTB, 28, 0);       /* LCDD23 */
 172
 173         writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
 174
 175         gd->fb_base = ATMEL_BASE_SRAM;
 176 }
 177
 178 #ifdef CONFIG_LCD_INFO
 179 #include <nand.h>
 180 #include <version.h>
 181
 182 extern flash_info_t flash_info[];
 183
 184 void lcd_show_board_info(void)
 185 {
 186         ulong dram_size, nand_size, flash_size, dataflash_size;
 187         int i;
 188         char temp[32];
 189
 190         lcd_printf ("%s\n", U_BOOT_VERSION);
 191         lcd_printf ("(C) 2009 Ronetix GmbH\n");
 192         lcd_printf ("support@ronetix.at\n");
 193         lcd_printf ("%s CPU at %s MHz",
 194                 CONFIG_SYS_AT91_CPU_NAME,
 195                 strmhz(temp, get_cpu_clk_rate()));
 196
 197         dram_size = 0;
 198         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 199                 dram_size += gd->bd->bi_dram[i].size;
 200
 201         nand_size = 0;
 202         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 203                 nand_size += nand_info[i].size;
 204
 205         flash_size = 0;
 206         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 207                 flash_size += flash_info[i].size;
 208
 209         dataflash_size = 0;
 210         for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
 211                 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
 212                                 dataflash_info[i].Device.pages_size;
 213
 214         lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
 215                         "%ld MB DataFlash\n",
 216                 dram_size >> 20,
 217                 nand_size >> 20,
 218                 flash_size >> 20,
 219                 dataflash_size >> 20);
 220 }
 221 #endif /* CONFIG_LCD_INFO */
 222
 223 #endif /* CONFIG_LCD */
 224
 225 int board_early_init_f(void)
 226 {
 227         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 228
 229         /* Enable clocks for some PIOs */
 230         writel(1 << ATMEL_ID_PIOA |
 231                 1 << ATMEL_ID_PIOC,
 232                 &pmc->pcer);
 233
 234         at91_seriald_hw_init();
 235
 236         return 0;
 237 }
 238
 239 int board_init(void)
 240 {
 241         /* arch number of PM9261-Board */
 242         gd->bd->bi_arch_number = MACH_TYPE_PM9261;
 243
 244         /* adress of boot parameters */
 245         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 246
 247 #ifdef CONFIG_CMD_NAND
 248         pm9261_nand_hw_init();
 249 #endif
 250 #ifdef CONFIG_HAS_DATAFLASH
 251         at91_spi0_hw_init(1 << 0);
 252 #endif
 253 #ifdef CONFIG_DRIVER_DM9000
 254         pm9261_dm9000_hw_init();
 255 #endif
 256 #ifdef CONFIG_LCD
 257         pm9261_lcd_hw_init();
 258 #endif
 259         return 0;
 260 }
 261
 262 #ifdef CONFIG_DRIVER_DM9000
 263 int board_eth_init(bd_t *bis)
 264 {
 265         return dm9000_initialize(bis);
 266 }
 267 #endif
 268
 269 int dram_init(void)
 270 {
 271         /* dram_init must store complete ramsize in gd->ram_size */
 272         gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
 273                                 PHYS_SDRAM_SIZE);
 274         return 0;
 275 }
 276
 277 void dram_init_banksize(void)
 278 {
 279         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 280         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 281 }
 282
 283 #ifdef CONFIG_RESET_PHY_R
 284 void reset_phy(void)
 285 {
 286 #ifdef CONFIG_DRIVER_DM9000
 287         /*
 288          * Initialize ethernet HW addr prior to starting Linux,
 289          * needed for nfsroot
 290          */
 291         eth_init(gd->bd);
 292 #endif
 293 }
 294 #endif
 295
 296 #ifdef CONFIG_DISPLAY_BOARDINFO
 297 int checkboard (void)
 298 {
 299         char buf[32];
 300
 301         printf ("Board : Ronetix PM9261\n");
 302         printf ("Crystal frequency: %8s MHz\n",
 303                                         strmhz(buf, get_main_clk_rate()));
 304         printf ("CPU clock        : %8s MHz\n",
 305                                         strmhz(buf, get_cpu_clk_rate()));
 306         printf ("Master clock     : %8s MHz\n",
 307                                         strmhz(buf, get_mck_clk_rate()));
 308
 309         return 0;
 310 }
 311 #endif