2 * Copyright (C) 2012 Samsung Electronics
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/dwmmc.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/mmc.h>
35 #include <asm/arch/pinmux.h>
36 #include <asm/arch/power.h>
37 #include <asm/arch/sromc.h>
38 #include <power/pmic.h>
39 #include <power/max77686_pmic.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 #if defined CONFIG_EXYNOS_TMU
46 * Boot Time Thermal Analysis for SoC temperature threshold breach
48 static void boot_temp_check(void)
52 switch (tmu_monitor(&temp)) {
53 /* Status TRIPPED ans WARNING means corresponding threshold breach */
54 case TMU_STATUS_TRIPPED:
55 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n");
59 case TMU_STATUS_WARNING:
60 puts("EXYNOS_TMU: WARNING! Temperature very high\n");
63 * TMU_STATUS_INIT means something is wrong with temperature sensing
64 * and TMU status was changed back from NORMAL to INIT.
68 debug("EXYNOS_TMU: Unknown TMU state\n");
74 struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */
75 int cros_ec_err; /* Error for cros_ec, 0 if ok */
78 static struct local_info local;
80 #ifdef CONFIG_USB_EHCI_EXYNOS
81 int board_usb_vbus_init(void)
83 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
84 samsung_get_base_gpio_part1();
86 /* Enable VBUS power switch */
87 s5p_gpio_direction_output(&gpio1->x2, 6, 1);
89 /* VBUS turn ON time */
96 #ifdef CONFIG_SOUND_MAX98095
97 static void board_enable_audio_codec(void)
99 struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
100 samsung_get_base_gpio_part1();
102 /* Enable MAX98095 Codec */
103 s5p_gpio_direction_output(&gpio1->x1, 7, 1);
104 s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
108 struct cros_ec_dev *board_get_cros_ec_dev(void)
110 return local.cros_ec_dev;
113 static int board_init_cros_ec_devices(const void *blob)
115 local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev);
116 if (local.cros_ec_err)
117 return -1; /* Will report in board_late_init() */
124 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
126 #if defined CONFIG_EXYNOS_TMU
127 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) {
128 debug("%s: Failed to init TMU\n", __func__);
134 #ifdef CONFIG_EXYNOS_SPI
138 if (board_init_cros_ec_devices(gd->fdt_blob))
141 #ifdef CONFIG_USB_EHCI_EXYNOS
142 board_usb_vbus_init();
144 #ifdef CONFIG_SOUND_MAX98095
145 board_enable_audio_codec();
155 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
156 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
157 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
162 #if defined(CONFIG_POWER)
163 static int pmic_reg_update(struct pmic *p, int reg, uint regval)
168 ret = pmic_reg_read(p, reg, &val);
170 debug("%s: PMIC %d register read failed\n", __func__, reg);
174 ret = pmic_reg_write(p, reg, val);
176 debug("%s: PMIC %d register write failed\n", __func__, reg);
182 int power_init_board(void)
188 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
190 if (pmic_init(I2C_PMIC))
193 p = pmic_get("MAX77686_PMIC");
200 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
203 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
204 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
208 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
209 MAX77686_BUCK1OUT_1V)) {
210 debug("%s: PMIC %d register write failed\n", __func__,
211 MAX77686_REG_PMIC_BUCK1OUT);
215 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
216 MAX77686_BUCK1CTRL_EN))
220 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
221 MAX77686_BUCK2DVS1_1_3V)) {
222 debug("%s: PMIC %d register write failed\n", __func__,
223 MAX77686_REG_PMIC_BUCK2DVS1);
227 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
228 MAX77686_BUCK2CTRL_ON))
232 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
233 MAX77686_BUCK3DVS1_1_0125V)) {
234 debug("%s: PMIC %d register write failed\n", __func__,
235 MAX77686_REG_PMIC_BUCK3DVS1);
239 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
240 MAX77686_BUCK3CTRL_ON))
244 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
245 MAX77686_BUCK4DVS1_1_2V)) {
246 debug("%s: PMIC %d register write failed\n", __func__,
247 MAX77686_REG_PMIC_BUCK4DVS1);
251 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
252 MAX77686_BUCK3CTRL_ON))
256 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
257 MAX77686_LD02CTRL1_1_5V | EN_LDO))
261 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
262 MAX77686_LD03CTRL1_1_8V | EN_LDO))
266 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
267 MAX77686_LD05CTRL1_1_8V | EN_LDO))
271 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
272 MAX77686_LD10CTRL1_1_8V | EN_LDO))
279 void dram_init_banksize(void)
284 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
285 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
286 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
288 gd->bd->bi_dram[i].start = addr;
289 gd->bd->bi_dram[i].size = size;
293 static int decode_sromc(const void *blob, struct fdt_sromc *config)
298 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
300 debug("Could not find SROMC node\n");
304 config->bank = fdtdec_get_int(blob, node, "bank", 0);
305 config->width = fdtdec_get_int(blob, node, "width", 2);
307 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
308 FDT_SROM_TIMING_COUNT);
310 debug("Could not decode SROMC configuration Error: %s\n",
312 return -FDT_ERR_NOTFOUND;
317 int board_eth_init(bd_t *bis)
319 #ifdef CONFIG_SMC911X
320 u32 smc_bw_conf, smc_bc_conf;
321 struct fdt_sromc config;
322 fdt_addr_t base_addr;
325 node = decode_sromc(gd->fdt_blob, &config);
327 debug("%s: Could not find sromc configuration\n", __func__);
330 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
332 debug("%s: Could not find lan9215 configuration\n", __func__);
336 /* We now have a node, so any problems from now on are errors */
337 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
338 if (base_addr == FDT_ADDR_T_NONE) {
339 debug("%s: Could not find lan9215 address\n", __func__);
343 /* Ethernet needs data bus width of 16 bits */
344 if (config.width != 2) {
345 debug("%s: Unsupported bus width %d\n", __func__,
349 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
350 | SROMC_BYTE_ENABLE(config.bank);
352 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
353 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
354 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
355 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
356 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
357 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
358 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
360 /* Select and configure the SROMC bank */
361 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
362 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
363 return smc911x_initialize(0, base_addr);
368 #ifdef CONFIG_DISPLAY_BOARDINFO
371 const char *board_name;
373 board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
374 if (board_name == NULL)
375 printf("\nUnknown Board\n");
377 printf("\nBoard: %s\n", board_name);
383 #ifdef CONFIG_GENERIC_MMC
384 int board_mmc_init(bd_t *bis)
387 /* dwmmc initializattion for available channels */
388 ret = exynos_dwmmc_init(gd->fdt_blob);
390 debug("dwmmc init failed\n");
396 static int board_uart_init(void)
398 int err, uart_id, ret = 0;
400 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
401 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
403 debug("UART%d not configured\n",
404 (uart_id - PERIPH_ID_UART0));
411 #ifdef CONFIG_BOARD_EARLY_INIT_F
412 int board_early_init_f(void)
415 err = board_uart_init();
417 debug("UART init failed\n");
420 #ifdef CONFIG_SYS_I2C_INIT_BOARD
421 board_i2c_init(gd->fdt_blob);
428 void exynos_cfg_lcd_gpio(void)
430 struct exynos5_gpio_part1 *gpio1 =
431 (struct exynos5_gpio_part1 *)samsung_get_base_gpio_part1();
434 s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
435 s5p_gpio_set_value(&gpio1->b2, 0, 1);
438 s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
439 s5p_gpio_set_value(&gpio1->x1, 5, 1);
441 /* Set Hotplug detect for DP */
442 s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
445 void exynos_set_dp_phy(unsigned int onoff)
447 set_dp_phy_ctrl(onoff);
451 #ifdef CONFIG_BOARD_LATE_INIT
452 int board_late_init(void)
454 stdio_print_current_devices();
456 if (local.cros_ec_err) {
457 /* Force console on */
458 gd->flags &= ~GD_FLG_SILENT;
460 printf("cros-ec communications failure %d\n",
462 puts("\nPlease reset with Power+Refresh\n\n");
463 panic("Cannot init cros-ec device");