board/samsung/smdk5250/smdk5250.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <fdtdec.h>
  25 #include <asm/io.h>
  26 #include <i2c.h>
  27 #include <lcd.h>
  28 #include <netdev.h>
  29 #include <spi.h>
  30 #include <asm/arch/cpu.h>
  31 #include <asm/arch/gpio.h>
  32 #include <asm/arch/mmc.h>
  33 #include <asm/arch/pinmux.h>
  34 #include <asm/arch/power.h>
  35 #include <asm/arch/sromc.h>
  36 #include <asm/arch/dp_info.h>
  37 #include <power/pmic.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #ifdef CONFIG_USB_EHCI_EXYNOS
  42 int board_usb_vbus_init(void)
  43 {
  44         struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
  45                                                 samsung_get_base_gpio_part1();
  46
  47         /* Enable VBUS power switch */
  48         s5p_gpio_direction_output(&gpio1->x2, 6, 1);
  49
  50         /* VBUS turn ON time */
  51         mdelay(3);
  52
  53         return 0;
  54 }
  55 #endif
  56
  57 int board_init(void)
  58 {
  59         gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
  60 #ifdef CONFIG_EXYNOS_SPI
  61         spi_init();
  62 #endif
  63 #ifdef CONFIG_USB_EHCI_EXYNOS
  64         board_usb_vbus_init();
  65 #endif
  66         return 0;
  67 }
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
  72                         + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
  73                         + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
  74                         + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
  75                         + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
  76                         + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
  77                         + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
  78                         + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
  79         return 0;
  80 }
  81
  82 #if defined(CONFIG_POWER)
  83 int power_init_board(void)
  84 {
  85         if (pmic_init(I2C_PMIC))
  86                 return -1;
  87         else
  88                 return 0;
  89 }
  90 #endif
  91
  92 void dram_init_banksize(void)
  93 {
  94         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  95         gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
  96                                                         PHYS_SDRAM_1_SIZE);
  97         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  98         gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
  99                                                         PHYS_SDRAM_2_SIZE);
 100         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 101         gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
 102                                                         PHYS_SDRAM_3_SIZE);
 103         gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 104         gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 105                                                         PHYS_SDRAM_4_SIZE);
 106         gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
 107         gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
 108                                                         PHYS_SDRAM_5_SIZE);
 109         gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
 110         gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
 111                                                         PHYS_SDRAM_6_SIZE);
 112         gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
 113         gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
 114                                                         PHYS_SDRAM_7_SIZE);
 115         gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
 116         gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
 117                                                         PHYS_SDRAM_8_SIZE);
 118 }
 119
 120 #ifdef CONFIG_OF_CONTROL
 121 static int decode_sromc(const void *blob, struct fdt_sromc *config)
 122 {
 123         int err;
 124         int node;
 125
 126         node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
 127         if (node < 0) {
 128                 debug("Could not find SROMC node\n");
 129                 return node;
 130         }
 131
 132         config->bank = fdtdec_get_int(blob, node, "bank", 0);
 133         config->width = fdtdec_get_int(blob, node, "width", 2);
 134
 135         err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
 136                         FDT_SROM_TIMING_COUNT);
 137         if (err < 0) {
 138                 debug("Could not decode SROMC configuration\n");
 139                 return -FDT_ERR_NOTFOUND;
 140         }
 141
 142         return 0;
 143 }
 144 #endif
 145
 146 int board_eth_init(bd_t *bis)
 147 {
 148 #ifdef CONFIG_SMC911X
 149         u32 smc_bw_conf, smc_bc_conf;
 150         struct fdt_sromc config;
 151         fdt_addr_t base_addr;
 152         int node;
 153
 154 #ifdef CONFIG_OF_CONTROL
 155         node = decode_sromc(gd->fdt_blob, &config);
 156         if (node < 0) {
 157                 debug("%s: Could not find sromc configuration\n", __func__);
 158                 return 0;
 159         }
 160         node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
 161         if (node < 0) {
 162                 debug("%s: Could not find lan9215 configuration\n", __func__);
 163                 return 0;
 164         }
 165
 166         /* We now have a node, so any problems from now on are errors */
 167         base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
 168         if (base_addr == FDT_ADDR_T_NONE) {
 169                 debug("%s: Could not find lan9215 address\n", __func__);
 170                 return -1;
 171         }
 172 #else
 173         /* Non-FDT configuration - bank number and timing parameters*/
 174         config.bank = CONFIG_ENV_SROM_BANK;
 175         config.width = 2;
 176
 177         config.timing[FDT_SROM_TACS] = 0x01;
 178         config.timing[FDT_SROM_TCOS] = 0x01;
 179         config.timing[FDT_SROM_TACC] = 0x06;
 180         config.timing[FDT_SROM_TCOH] = 0x01;
 181         config.timing[FDT_SROM_TAH] = 0x0C;
 182         config.timing[FDT_SROM_TACP] = 0x09;
 183         config.timing[FDT_SROM_PMC] = 0x01;
 184         base_addr = CONFIG_SMC911X_BASE;
 185 #endif
 186
 187         /* Ethernet needs data bus width of 16 bits */
 188         if (config.width != 2) {
 189                 debug("%s: Unsupported bus width %d\n", __func__,
 190                         config.width);
 191                 return -1;
 192         }
 193         smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
 194                         | SROMC_BYTE_ENABLE(config.bank);
 195
 196         smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
 197                         SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
 198                         SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
 199                         SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
 200                         SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
 201                         SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
 202                         SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
 203
 204         /* Select and configure the SROMC bank */
 205         exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
 206         s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
 207         return smc911x_initialize(0, base_addr);
 208 #endif
 209         return 0;
 210 }
 211
 212 #ifdef CONFIG_DISPLAY_BOARDINFO
 213 int checkboard(void)
 214 {
 215         printf("\nBoard: SMDK5250\n");
 216
 217         return 0;
 218 }
 219 #endif
 220
 221 #ifdef CONFIG_GENERIC_MMC
 222 int board_mmc_init(bd_t *bis)
 223 {
 224         int err;
 225
 226         err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
 227         if (err) {
 228                 debug("SDMMC0 not configured\n");
 229                 return err;
 230         }
 231
 232         err = s5p_mmc_init(0, 8);
 233         return err;
 234 }
 235 #endif
 236
 237 static int board_uart_init(void)
 238 {
 239         int err;
 240
 241         err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
 242         if (err) {
 243                 debug("UART0 not configured\n");
 244                 return err;
 245         }
 246
 247         err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
 248         if (err) {
 249                 debug("UART1 not configured\n");
 250                 return err;
 251         }
 252
 253         err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
 254         if (err) {
 255                 debug("UART2 not configured\n");
 256                 return err;
 257         }
 258
 259         err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
 260         if (err) {
 261                 debug("UART3 not configured\n");
 262                 return err;
 263         }
 264
 265         return 0;
 266 }
 267
 268 #ifdef CONFIG_BOARD_EARLY_INIT_F
 269 int board_early_init_f(void)
 270 {
 271         int err;
 272         err = board_uart_init();
 273         if (err) {
 274                 debug("UART init failed\n");
 275                 return err;
 276         }
 277 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 278         board_i2c_init(gd->fdt_blob);
 279 #endif
 280         return err;
 281 }
 282 #endif
 283
 284 #ifdef CONFIG_LCD
 285 void cfg_lcd_gpio(void)
 286 {
 287         struct exynos5_gpio_part1 *gpio1 =
 288                 (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 289
 290         /* For Backlight */
 291         s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
 292         s5p_gpio_set_value(&gpio1->b2, 0, 1);
 293
 294         /* LCD power on */
 295         s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
 296         s5p_gpio_set_value(&gpio1->x1, 5, 1);
 297
 298         /* Set Hotplug detect for DP */
 299         s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
 300 }
 301
 302 vidinfo_t panel_info = {
 303         .vl_freq        = 60,
 304         .vl_col         = 2560,
 305         .vl_row         = 1600,
 306         .vl_width       = 2560,
 307         .vl_height      = 1600,
 308         .vl_clkp        = CONFIG_SYS_LOW,
 309         .vl_hsp         = CONFIG_SYS_LOW,
 310         .vl_vsp         = CONFIG_SYS_LOW,
 311         .vl_dp          = CONFIG_SYS_LOW,
 312         .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
 313
 314         /* wDP panel timing infomation */
 315         .vl_hspw        = 32,
 316         .vl_hbpd        = 80,
 317         .vl_hfpd        = 48,
 318
 319         .vl_vspw        = 6,
 320         .vl_vbpd        = 37,
 321         .vl_vfpd        = 3,
 322         .vl_cmd_allow_len = 0xf,
 323
 324         .win_id         = 3,
 325         .cfg_gpio       = cfg_lcd_gpio,
 326         .backlight_on   = NULL,
 327         .lcd_power_on   = NULL,
 328         .reset_lcd      = NULL,
 329         .dual_lcd_enabled = 0,
 330
 331         .init_delay     = 0,
 332         .power_on_delay = 0,
 333         .reset_delay    = 0,
 334         .interface_mode = FIMD_RGB_INTERFACE,
 335         .dp_enabled     = 1,
 336 };
 337
 338 static struct edp_device_info edp_info = {
 339         .disp_info = {
 340                 .h_res = 2560,
 341                 .h_sync_width = 32,
 342                 .h_back_porch = 80,
 343                 .h_front_porch = 48,
 344                 .v_res = 1600,
 345                 .v_sync_width  = 6,
 346                 .v_back_porch = 37,
 347                 .v_front_porch = 3,
 348                 .v_sync_rate = 60,
 349         },
 350         .lt_info = {
 351                 .lt_status = DP_LT_NONE,
 352         },
 353         .video_info = {
 354                 .master_mode = 0,
 355                 .bist_mode = DP_DISABLE,
 356                 .bist_pattern = NO_PATTERN,
 357                 .h_sync_polarity = 0,
 358                 .v_sync_polarity = 0,
 359                 .interlaced = 0,
 360                 .color_space = COLOR_RGB,
 361                 .dynamic_range = VESA,
 362                 .ycbcr_coeff = COLOR_YCBCR601,
 363                 .color_depth = COLOR_8,
 364         },
 365 };
 366
 367 static struct exynos_dp_platform_data dp_platform_data = {
 368         .phy_enable     = set_dp_phy_ctrl,
 369         .edp_dev_info   = &edp_info,
 370 };
 371
 372 void init_panel_info(vidinfo_t *vid)
 373 {
 374         vid->rgb_mode   = MODE_RGB_P,
 375
 376         exynos_set_dp_platform_data(&dp_platform_data);
 377 }
 378 #endif