2 * Lowlevel setup for SMDKV310 board based on EXYNOS4210
4 * Copyright (C) 2011 Samsung Electronics
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/cpu.h>
33 * r7 has GPIO part1 base 0x11400000
34 * r6 has GPIO part2 base 0x11000000
40 .word CONFIG_SYS_TEXT_BASE
46 /* r5 has always zero */
48 ldr r7, =EXYNOS4_GPIO_PART1_BASE
49 ldr r6, =EXYNOS4_GPIO_PART2_BASE
51 /* check reset status */
52 ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7
55 /* AFTR wakeup reset */
56 ldr r2, =S5P_CHECK_DIDLE
60 /* Sleep wakeup reset */
61 ldr r2, =S5P_CHECK_SLEEP
66 * If U-boot is already running in ram, no need to relocate U-Boot.
67 * Memory controller must be configured before relocating U-Boot
70 ldr r0, =0x00ffffff /* r0 <- Mask Bits*/
71 bic r1, pc, r0 /* pc <- current addr of code */
72 /* r1 <- unmasked bits of pc */
74 ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
75 bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
76 cmp r1, r2 /* compare r1, r2 */
77 beq 1f /* r0 == r1 then skip sdram init */
79 /* init system clock */
82 /* Memory initialize */
99 /* Load return address and jump to kernel */
100 ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0
102 /* r1 = physical address of exynos4210_cpu_resume function */
111 * system_clock_init: Initialize core clock and bus clock.
112 * void system_clock_init(void)
116 ldr r0, =EXYNOS4_CLOCK_BASE
118 /* APLL(1), MPLL(1), CORE(0), HPM(0) */
120 ldr r2, =0x14200 @CLK_SRC_CPU
129 ldr r2, =0x0C210 @CLK_SRC_TOP0
133 ldr r2, =0x0C214 @CLK_SRC_TOP1_OFFSET
138 ldr r2, =0x10200 @CLK_SRC_DMC_OFFSET
143 ldr r2, =0x04200 @CLK_SRC_LEFTBUS_OFFSET
146 /*CLK_SRC_RIGHTBUS */
148 ldr r2, =0x08200 @CLK_SRC_RIGHTBUS_OFFSET
151 /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
153 ldr r2, =0x0C240 @ CLK_SRC_FSYS
156 /* UART[0:4], PWM: SCLKMPLL(6) */
158 ldr r2, =0x0C250 @CLK_SRC_PERIL0_OFFSET
169 * PCLK_DBG_RATIO[20] 0x1
171 * PERIPH_RATIO[12] 0x3
172 * COREM1_RATIO[8] 0x7
173 * COREM0_RATIO[4] 0x3
176 ldr r2, =0x14500 @CLK_DIV_CPU0_OFFSET
179 /* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */
181 ldr r2, =0x14504 @CLK_DIV_CPU1_OFFSET
187 * CORE_TIMERS_RATIO[28] 0x1
188 * COPY2_RATIO[24] 0x3
193 * ACP_PCLK_RATIO[4] 0x1
197 ldr r2, =0x010500 @CLK_DIV_DMC0_OFFSET
204 * DVSEM_RATIO[16] 0x1
208 ldr r2, =0x010504 @CLK_DIV_DMC1_OFFSET
218 ldr r2, =0x04500 @CLK_DIV_LEFTBUS_OFFSET
228 ldr r2, =0x08500 @CLK_DIV_RIGHTBUS_OFFSET
234 * ONENAND_RATIO[16] 0x0
235 * ACLK_133_RATIO[12] 0x5
236 * ACLK_160_RATIO[8] 0x4
237 * ACLK_100_RATIO[4] 0x7
238 * ACLK_200_RATIO[0] 0x3
241 ldr r2, =0x0C510 @CLK_DIV_TOP_OFFSET
245 ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
246 ldr r2, =0x0C544 @ CLK_DIV_FSYS1
250 ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
251 ldr r2, =0x0C548 @ CLK_DIV_FSYS2
255 ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
256 ldr r2, =0x0C54C @ CLK_DIV_FSYS3
275 ldr r2, =0x0C550 @CLK_DIV_PERIL0_OFFSET
278 /* SLIMBUS: ???, PWM */
280 ldr r2, =0x0C55C @ CLK_DIV_PERIL3
283 /* Set PLL locktime */
285 ldr r2, =0x014000 @APLL_LOCK_OFFSET
288 ldr r2, =0x014008 @MPLL_LOCK_OFFSET
291 ldr r2, =0x0C010 @EPLL_LOCK_OFFSET
294 ldr r2, =0x0C020 @VPLL_LOCK_OFFSET
300 * APLL_AFC_ENB[31] 0x1
304 ldr r2, =0x014104 @APLL_CON1_OFFSET
315 ldr r2, =0x014100 @APLL_CON0_OFFSET
321 * MPLL_AFC_ENB[31] 0x1
325 ldr r2, =0x01410C @MPLL_CON1_OFFSET
336 ldr r2, =0x014108 @MPLL_CON0_OFFSET
341 ldr r2, =0x0C114 @EPLL_CON1_OFFSET
352 ldr r2, =0x0C110 @EPLL_CON0_OFFSET
363 ldr r2, =0x0C124 @VPLL_CON1_OFFSET
374 ldr r2, =0x0C120 @VPLL_CON0_OFFSET
384 * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
385 * void uart_asm_init(void)
390 /* setup UART0-UART3 GPIOs (part1) */
393 str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
395 str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
397 ldr r0, =EXYNOS4_UART_BASE
398 add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET