board/samsung/trats/trats.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  * Kyungmin Park <kyungmin.park@samsung.com>
   5  * Donghwa Lee <dh09.lee@samsung.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <lcd.h>
  12 #include <asm/io.h>
  13 #include <asm/gpio.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/pinmux.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/mipi_dsim.h>
  18 #include <asm/arch/watchdog.h>
  19 #include <asm/arch/power.h>
  20 #include <power/pmic.h>
  21 #include <usb/s3c_udc.h>
  22 #include <power/max8997_pmic.h>
  23 #include <power/max8997_muic.h>
  24 #include <power/battery.h>
  25 #include <power/max17042_fg.h>
  26 #include <libtizen.h>
  27 #include <usb.h>
  28 #include <usb_mass_storage.h>
  29
  30 #include "setup.h"
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 unsigned int board_rev;
  35
  36 #ifdef CONFIG_REVISION_TAG
  37 u32 get_board_rev(void)
  38 {
  39         return board_rev;
  40 }
  41 #endif
  42
  43 static void check_hw_revision(void);
  44 struct s3c_plat_otg_data s5pc210_otg_data;
  45
  46 int exynos_init(void)
  47 {
  48         check_hw_revision();
  49         printf("HW Revision:\t0x%x\n", board_rev);
  50
  51         return 0;
  52 }
  53
  54 void i2c_init_board(void)
  55 {
  56         int err;
  57
  58         /* I2C_5 -> PMIC */
  59         err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
  60         if (err) {
  61                 debug("I2C%d not configured\n", (I2C_5));
  62                 return;
  63         }
  64
  65         /* I2C_8 -> FG */
  66         gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk");
  67         gpio_request(EXYNOS4_GPIO_Y41, "i2c_data");
  68         gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
  69         gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
  70 }
  71
  72 static void trats_low_power_mode(void)
  73 {
  74         struct exynos4_clock *clk =
  75             (struct exynos4_clock *)samsung_get_base_clock();
  76         struct exynos4_power *pwr =
  77             (struct exynos4_power *)samsung_get_base_power();
  78
  79         /* Power down CORE1 */
  80         /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
  81         writel(0x0, &pwr->arm_core1_configuration);
  82
  83         /* Change the APLL frequency */
  84         /* ENABLE (1 enable) | LOCKED (1 locked)  */
  85         /* [31]              | [29]               */
  86         /* FSEL      | MDIV          | PDIV            | SDIV */
  87         /* [27]      | [25:16]       | [13:8]          | [2:0]      */
  88         writel(0xa0c80604, &clk->apll_con0);
  89
  90         /* Change CPU0 clock divider */
  91         /* CORE2_RATIO  | APLL_RATIO   | PCLK_DBG_RATIO | ATB_RATIO  */
  92         /* [30:28]      | [26:24]      | [22:20]        | [18:16]    */
  93         /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO   | CORE_RATIO */
  94         /* [14:12]      | [10:8]       | [6:4]          | [2:0]      */
  95         writel(0x00000100, &clk->div_cpu0);
  96
  97         /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
  98         while (readl(&clk->div_stat_cpu0) & 0x1111111)
  99                 continue;
 100
 101         /* Change clock divider ratio for DMC */
 102         /* DMCP_RATIO                  | DMCD_RATIO  */
 103         /* [22:20]                     | [18:16]     */
 104         /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO   | ACP_RATIO */
 105         /* [14:12]   | [10:8]     | [6:4]            | [2:0]     */
 106         writel(0x13113117, &clk->div_dmc0);
 107
 108         /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
 109         while (readl(&clk->div_stat_dmc0) & 0x11111111)
 110                 continue;
 111
 112         /* Turn off unnecessary power domains */
 113         writel(0x0, &pwr->xxti_configuration);  /* XXTI */
 114         writel(0x0, &pwr->cam_configuration);   /* CAM */
 115         writel(0x0, &pwr->tv_configuration);    /* TV */
 116         writel(0x0, &pwr->mfc_configuration);   /* MFC */
 117         writel(0x0, &pwr->g3d_configuration);   /* G3D */
 118         writel(0x0, &pwr->gps_configuration);   /* GPS */
 119         writel(0x0, &pwr->gps_alive_configuration);     /* GPS_ALIVE */
 120
 121         /* Turn off unnecessary clocks */
 122         writel(0x0, &clk->gate_ip_cam); /* CAM */
 123         writel(0x0, &clk->gate_ip_tv);          /* TV */
 124         writel(0x0, &clk->gate_ip_mfc); /* MFC */
 125         writel(0x0, &clk->gate_ip_g3d); /* G3D */
 126         writel(0x0, &clk->gate_ip_image);       /* IMAGE */
 127         writel(0x0, &clk->gate_ip_gps); /* GPS */
 128 }
 129
 130 static int pmic_init_max8997(void)
 131 {
 132         struct pmic *p = pmic_get("MAX8997_PMIC");
 133         int i = 0, ret = 0;
 134         u32 val;
 135
 136         if (pmic_probe(p))
 137                 return -1;
 138
 139         /* BUCK1 VARM: 1.2V */
 140         val = (1200000 - 650000) / 25000;
 141         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val);
 142         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 143         ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val);
 144
 145         /* BUCK2 VINT: 1.1V */
 146         val = (1100000 - 650000) / 25000;
 147         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val);
 148         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 149         ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val);
 150
 151
 152         /* BUCK3 G3D: 1.1V - OFF */
 153         ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val);
 154         val &= ~ENBUCK;
 155         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val);
 156
 157         val = (1100000 - 750000) / 50000;
 158         ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val);
 159
 160         /* BUCK4 CAMISP: 1.2V - OFF */
 161         ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val);
 162         val &= ~ENBUCK;
 163         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val);
 164
 165         val = (1200000 - 650000) / 25000;
 166         ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val);
 167
 168         /* BUCK5 VMEM: 1.2V */
 169         val = (1200000 - 650000) / 25000;
 170         for (i = 0; i < 8; i++)
 171                 ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val);
 172
 173         val = ENBUCK | ACTIVE_DISCHARGE;                /* DVS OFF */
 174         ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val);
 175
 176         /* BUCK6 CAM AF: 2.8V */
 177         /* No Voltage Setting Register */
 178         /* GNSLCT 3.0X */
 179         val = GNSLCT;
 180         ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val);
 181
 182         /* BUCK7 VCC_SUB: 2.0V */
 183         val = (2000000 - 750000) / 50000;
 184         ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val);
 185
 186         /* LDO1 VADC: 3.3V */
 187         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 188         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val);
 189
 190         /* LDO1 Disable active discharging */
 191         ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val);
 192         val &= ~LDO_ADE;
 193         ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val);
 194
 195         /* LDO2 VALIVE: 1.1V */
 196         val = max8997_reg_ldo(1100000) | EN_LDO;
 197         ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val);
 198
 199         /* LDO3 VUSB/MIPI: 1.1V */
 200         val = max8997_reg_ldo(1100000) | DIS_LDO;       /* OFF */
 201         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val);
 202
 203         /* LDO4 VMIPI: 1.8V */
 204         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 205         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val);
 206
 207         /* LDO5 VHSIC: 1.2V */
 208         val = max8997_reg_ldo(1200000) | DIS_LDO;       /* OFF */
 209         ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val);
 210
 211         /* LDO6 VCC_1.8V_PDA: 1.8V */
 212         val = max8997_reg_ldo(1800000) | EN_LDO;
 213         ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val);
 214
 215         /* LDO7 CAM_ISP: 1.8V */
 216         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 217         ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val);
 218
 219         /* LDO8 VDAC/VUSB: 3.3V */
 220         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 221         ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val);
 222
 223         /* LDO9 VCC_2.8V_PDA: 2.8V */
 224         val = max8997_reg_ldo(2800000) | EN_LDO;
 225         ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val);
 226
 227         /* LDO10 VPLL: 1.1V */
 228         val = max8997_reg_ldo(1100000) | EN_LDO;
 229         ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val);
 230
 231         /* LDO11 TOUCH: 2.8V */
 232         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 233         ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val);
 234
 235         /* LDO12 VTCAM: 1.8V */
 236         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 237         ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val);
 238
 239         /* LDO13 VCC_3.0_LCD: 3.0V */
 240         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 241         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val);
 242
 243         /* LDO14 MOTOR: 3.0V */
 244         val = max8997_reg_ldo(3000000) | DIS_LDO;       /* OFF */
 245         ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val);
 246
 247         /* LDO15 LED_A: 2.8V */
 248         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 249         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val);
 250
 251         /* LDO16 CAM_SENSOR: 1.8V */
 252         val = max8997_reg_ldo(1800000) | DIS_LDO;       /* OFF */
 253         ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val);
 254
 255         /* LDO17 VTF: 2.8V */
 256         val = max8997_reg_ldo(2800000) | DIS_LDO;       /* OFF */
 257         ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val);
 258
 259         /* LDO18 TOUCH_LED 3.3V */
 260         val = max8997_reg_ldo(3300000) | DIS_LDO;       /* OFF */
 261         ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val);
 262
 263         /* LDO21 VDDQ: 1.2V */
 264         val = max8997_reg_ldo(1200000) | EN_LDO;
 265         ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val);
 266
 267         /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */
 268         val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) |
 269                 ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2;
 270         ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val);
 271
 272         if (ret) {
 273                 puts("MAX8997 PMIC setting error!\n");
 274                 return -1;
 275         }
 276         return 0;
 277 }
 278
 279 int exynos_power_init(void)
 280 {
 281         int chrg, ret;
 282         struct power_battery *pb;
 283         struct pmic *p_fg, *p_chrg, *p_muic, *p_bat;
 284
 285         /*
 286          * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected
 287          * to logical I2C adapter 0
 288          *
 289          * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected
 290          * to logical I2C adapter 1
 291          */
 292         ret = pmic_init(I2C_5);
 293         ret |= pmic_init_max8997();
 294         ret |= power_fg_init(I2C_9);
 295         ret |= power_muic_init(I2C_5);
 296         ret |= power_bat_init(0);
 297         if (ret)
 298                 return ret;
 299
 300         p_fg = pmic_get("MAX17042_FG");
 301         if (!p_fg) {
 302                 puts("MAX17042_FG: Not found\n");
 303                 return -ENODEV;
 304         }
 305
 306         p_chrg = pmic_get("MAX8997_PMIC");
 307         if (!p_chrg) {
 308                 puts("MAX8997_PMIC: Not found\n");
 309                 return -ENODEV;
 310         }
 311
 312         p_muic = pmic_get("MAX8997_MUIC");
 313         if (!p_muic) {
 314                 puts("MAX8997_MUIC: Not found\n");
 315                 return -ENODEV;
 316         }
 317
 318         p_bat = pmic_get("BAT_TRATS");
 319         if (!p_bat) {
 320                 puts("BAT_TRATS: Not found\n");
 321                 return -ENODEV;
 322         }
 323
 324         p_fg->parent =  p_bat;
 325         p_chrg->parent = p_bat;
 326         p_muic->parent = p_bat;
 327
 328         p_bat->low_power_mode = trats_low_power_mode;
 329         p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic);
 330
 331         pb = p_bat->pbat;
 332         chrg = p_muic->chrg->chrg_type(p_muic);
 333         debug("CHARGER TYPE: %d\n", chrg);
 334
 335         if (!p_chrg->chrg->chrg_bat_present(p_chrg)) {
 336                 puts("No battery detected\n");
 337                 return 0;
 338         }
 339
 340         p_fg->fg->fg_battery_check(p_fg, p_bat);
 341
 342         if (pb->bat->state == CHARGE && chrg == CHARGER_USB)
 343                 puts("CHARGE Battery !\n");
 344
 345         return 0;
 346 }
 347
 348 static unsigned int get_hw_revision(void)
 349 {
 350         int hwrev = 0;
 351         char str[10];
 352         int i;
 353
 354         /* hw_rev[3:0] == GPE1[3:0] */
 355         for (i = 0; i < 4; i++) {
 356                 int pin = i + EXYNOS4_GPIO_E10;
 357
 358                 sprintf(str, "hw_rev%d", i);
 359                 gpio_request(pin, str);
 360                 gpio_cfg_pin(pin, S5P_GPIO_INPUT);
 361                 gpio_set_pull(pin, S5P_GPIO_PULL_NONE);
 362         }
 363
 364         udelay(1);
 365
 366         for (i = 0; i < 4; i++)
 367                 hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i);
 368
 369         debug("hwrev 0x%x\n", hwrev);
 370
 371         return hwrev;
 372 }
 373
 374 static void check_hw_revision(void)
 375 {
 376         int hwrev;
 377
 378         hwrev = get_hw_revision();
 379
 380         board_rev |= hwrev;
 381 }
 382
 383
 384 #ifdef CONFIG_USB_GADGET
 385 static int s5pc210_phy_control(int on)
 386 {
 387         int ret = 0;
 388         u32 val = 0;
 389         struct pmic *p = pmic_get("MAX8997_PMIC");
 390         if (!p)
 391                 return -ENODEV;
 392
 393         if (pmic_probe(p))
 394                 return -1;
 395
 396         if (on) {
 397                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 398                                       ENSAFEOUT1, LDO_ON);
 399                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 400                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val);
 401
 402                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 403                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val);
 404         } else {
 405                 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val);
 406                 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val);
 407
 408                 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val);
 409                 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val);
 410                 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL,
 411                                       ENSAFEOUT1, LDO_OFF);
 412         }
 413
 414         if (ret) {
 415                 puts("MAX8997 LDO setting error!\n");
 416                 return -1;
 417         }
 418
 419         return 0;
 420 }
 421
 422 struct s3c_plat_otg_data s5pc210_otg_data = {
 423         .phy_control    = s5pc210_phy_control,
 424         .regs_phy       = EXYNOS4_USBPHY_BASE,
 425         .regs_otg       = EXYNOS4_USBOTG_BASE,
 426         .usb_phy_ctrl   = EXYNOS4_USBPHY_CONTROL,
 427         .usb_flags      = PHY0_SLEEP,
 428 };
 429
 430 int board_usb_init(int index, enum usb_init_type init)
 431 {
 432         debug("USB_udc_probe\n");
 433         return s3c_udc_probe(&s5pc210_otg_data);
 434 }
 435
 436 int g_dnl_board_usb_cable_connected(void)
 437 {
 438         struct pmic *muic = pmic_get("MAX8997_MUIC");
 439         if (!muic)
 440                 return 0;
 441
 442         return !!muic->chrg->chrg_type(muic);
 443 }
 444 #endif
 445
 446 static void pmic_reset(void)
 447 {
 448         gpio_direction_output(EXYNOS4_GPIO_X07, 1);
 449         gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE);
 450 }
 451
 452 static void board_clock_init(void)
 453 {
 454         struct exynos4_clock *clk =
 455                 (struct exynos4_clock *)samsung_get_base_clock();
 456
 457         writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu);
 458         writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0);
 459         writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys);
 460         writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0);
 461
 462         writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0);
 463         writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1);
 464         writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0);
 465         writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1);
 466         writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus);
 467         writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus);
 468         writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top);
 469         writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1);
 470         writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2);
 471         writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3);
 472         writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0);
 473         writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3);
 474
 475         writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock);
 476         writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock);
 477         writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock);
 478         writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock);
 479         writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1);
 480         writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0);
 481         writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1);
 482         writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0);
 483         writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1);
 484         writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0);
 485         writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1);
 486         writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0);
 487
 488         writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam);
 489         writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv);
 490         writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc);
 491         writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d);
 492         writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image);
 493         writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0);
 494         writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1);
 495         writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys);
 496         writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps);
 497         writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril);
 498         writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir);
 499         writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block);
 500 }
 501
 502 static void board_power_init(void)
 503 {
 504         struct exynos4_power *pwr =
 505                 (struct exynos4_power *)samsung_get_base_power();
 506
 507         /* PS HOLD */
 508         writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
 509
 510         /* Set power down */
 511         writel(0, (unsigned int)&pwr->cam_configuration);
 512         writel(0, (unsigned int)&pwr->tv_configuration);
 513         writel(0, (unsigned int)&pwr->mfc_configuration);
 514         writel(0, (unsigned int)&pwr->g3d_configuration);
 515         writel(0, (unsigned int)&pwr->lcd1_configuration);
 516         writel(0, (unsigned int)&pwr->gps_configuration);
 517         writel(0, (unsigned int)&pwr->gps_alive_configuration);
 518
 519         /* It is necessary to power down core 1 */
 520         /* to successfully boot CPU1 in kernel */
 521         writel(0, (unsigned int)&pwr->arm_core1_configuration);
 522 }
 523
 524 static void exynos_uart_init(void)
 525 {
 526         /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
 527         gpio_request(EXYNOS4_GPIO_Y47, "uart_sel");
 528         gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP);
 529         gpio_direction_output(EXYNOS4_GPIO_Y47, 1);
 530 }
 531
 532 int exynos_early_init_f(void)
 533 {
 534         wdt_stop();
 535         pmic_reset();
 536         board_clock_init();
 537         exynos_uart_init();
 538         board_power_init();
 539
 540         return 0;
 541 }
 542
 543 void exynos_reset_lcd(void)
 544 {
 545         gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
 546         gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
 547         udelay(10000);
 548         gpio_direction_output(EXYNOS4_GPIO_Y45, 0);
 549         udelay(10000);
 550         gpio_direction_output(EXYNOS4_GPIO_Y45, 1);
 551 }
 552
 553 int lcd_power(void)
 554 {
 555         int ret = 0;
 556         struct pmic *p = pmic_get("MAX8997_PMIC");
 557         if (!p)
 558                 return -ENODEV;
 559
 560         if (pmic_probe(p))
 561                 return 0;
 562
 563         /* LDO15 voltage: 2.2v */
 564         ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO);
 565         /* LDO13 voltage: 3.0v */
 566         ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO);
 567
 568         if (ret) {
 569                 puts("MAX8997 LDO setting error!\n");
 570                 return -1;
 571         }
 572
 573         return 0;
 574 }
 575
 576 int mipi_power(void)
 577 {
 578         int ret = 0;
 579         struct pmic *p = pmic_get("MAX8997_PMIC");
 580         if (!p)
 581                 return -ENODEV;
 582
 583         if (pmic_probe(p))
 584                 return 0;
 585
 586         /* LDO3 voltage: 1.1v */
 587         ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO);
 588         /* LDO4 voltage: 1.8v */
 589         ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO);
 590
 591         if (ret) {
 592                 puts("MAX8997 LDO setting error!\n");
 593                 return -1;
 594         }
 595
 596         return 0;
 597 }
 598
 599 void exynos_lcd_misc_init(vidinfo_t *vid)
 600 {
 601 #ifdef CONFIG_TIZEN
 602         get_tizen_logo_info(vid);
 603 #endif
 604 #ifdef CONFIG_S6E8AX0
 605         s6e8ax0_init();
 606         setenv("lcdinfo", "lcd=s6e8ax0");
 607 #endif
 608 }