board/sandburst/metrobox/metrobox.c

   1 /*
   2  *  Copyright (c) 2005
   3  *  Travis B. Sawyer,  Sandburst Corporation, tsawyer@sandburst.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <config.h>
   8 #include <common.h>
   9 #include <command.h>
  10 #include "metrobox.h"
  11 #include "metrobox_version.h"
  12 #include <timestamp.h>
  13 #include <asm/processor.h>
  14 #include <asm/io.h>
  15 #include <spd_sdram.h>
  16 #include <i2c.h>
  17 #include "../common/sb_common.h"
  18 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
  19     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
  20 #include <net.h>
  21 #endif
  22
  23 void fpga_init (void);
  24
  25 METROBOX_BOARD_ID_ST board_id_as[] =
  26 {       {"Undefined"},                      /* Not specified */
  27         {"2x10Gb"},                         /* 2 ports, 10 GbE */
  28         {"20x1Gb"},                         /* 20 ports, 1 GbE */
  29         {"Reserved"},                        /* Reserved for future use */
  30 };
  31
  32 /*************************************************************************
  33  *  board_early_init_f
  34  *
  35  *  Setup chip selects, initialize the Opto-FPGA, initialize
  36  *  interrupt polarity and triggers.
  37  ************************************************************************/
  38 int board_early_init_f (void)
  39 {
  40         ppc440_gpio_regs_t *gpio_regs;
  41
  42         /* Enable GPIO interrupts */
  43         mtsdr(SDR0_PFC0, 0x00103E00);
  44
  45         /* Setup access for LEDs, and system topology info */
  46         gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
  47         gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
  48         gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
  49
  50         /* Turn on all the leds for now */
  51         gpio_regs->out = SBCOMMON_GPIO_LEDS;
  52
  53         /*--------------------------------------------------------------------+
  54           | Initialize EBC CONFIG
  55           +-------------------------------------------------------------------*/
  56         mtebc(EBC0_CFG,
  57               EBC_CFG_LE_UNLOCK    | EBC_CFG_PTD_ENABLE |
  58               EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
  59               EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
  60               EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
  61               EBC_CFG_PR_32);
  62
  63         /*--------------------------------------------------------------------+
  64           | 1/2 MB FLASH. Initialize bank 0 with default values.
  65           +-------------------------------------------------------------------*/
  66         mtebc(PB0AP,
  67               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  68               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  69               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  70               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  71               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  72               EBC_BXAP_PEN_DISABLED);
  73
  74         mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
  75               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  76         /*--------------------------------------------------------------------+
  77           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
  78           +-------------------------------------------------------------------*/
  79         mtebc(PB1AP,
  80               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
  81               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  82               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  83               EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
  84               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  85               EBC_BXAP_PEN_DISABLED);
  86
  87         mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
  88               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
  89
  90         /*--------------------------------------------------------------------+
  91           | Compact Flash, uses 2 Chip Selects (2 & 6)
  92           +-------------------------------------------------------------------*/
  93         mtebc(PB2AP,
  94               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
  95               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
  96               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
  97               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
  98               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
  99               EBC_BXAP_PEN_DISABLED);
 100
 101         mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
 102               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 103
 104         /*--------------------------------------------------------------------+
 105           | OPTO & OFEM FPGA. Initialize bank 3 with default values.
 106           +-------------------------------------------------------------------*/
 107         mtebc(PB3AP,
 108               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 109               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 110               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 111               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 112               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 113
 114         mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
 115               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 116
 117         /*--------------------------------------------------------------------+
 118           | MAC A for metrobox
 119           | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
 120           | Initialize bank 4 with default values.
 121           +-------------------------------------------------------------------*/
 122         mtebc(PB4AP,
 123               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 124               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 125               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 126               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 127               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 128
 129         mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
 130               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 131
 132         /*--------------------------------------------------------------------+
 133           | Metrobox MAC B  Initialize bank 5 with default values.
 134           | KA REF FPGA  Initialize bank 5 with default values.
 135           +-------------------------------------------------------------------*/
 136         mtebc(PB5AP,
 137               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 138               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 139               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 140               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 141               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 142
 143         mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
 144               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 145
 146         /*--------------------------------------------------------------------+
 147           | Compact Flash, uses 2 Chip Selects (2 & 6)
 148           +-------------------------------------------------------------------*/
 149         mtebc(PB6AP,
 150               EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
 151               EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
 152               EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
 153               EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
 154               EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 155               EBC_BXAP_PEN_DISABLED);
 156
 157         mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
 158               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
 159
 160         /*--------------------------------------------------------------------+
 161           | BME-32. Initialize bank 7 with default values.
 162           +-------------------------------------------------------------------*/
 163         mtebc(PB7AP,
 164               EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
 165               EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
 166               EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
 167               EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
 168               EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
 169
 170         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
 171               EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
 172
 173         /*--------------------------------------------------------------------+
 174          * Setup the interrupt controller polarities, triggers, etc.
 175          +-------------------------------------------------------------------*/
 176         /*
 177          * Because of the interrupt handling rework to handle 440GX interrupts
 178          * with the common code, we needed to change names of the UIC registers.
 179          * Here the new relationship:
 180          *
 181          * U-Boot name  440GX name
 182          * -----------------------
 183          * UIC0         UICB0
 184          * UIC1         UIC0
 185          * UIC2         UIC1
 186          * UIC3         UIC2
 187          */
 188         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 189         mtdcr (UIC1ER, 0x00000000);     /* disable all */
 190         mtdcr (UIC1CR, 0x00000000);     /* all non- critical */
 191         mtdcr (UIC1PR, 0xfffffe03);     /* polarity */
 192         mtdcr (UIC1TR, 0x01c00000);     /* trigger edge vs level */
 193         mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
 194         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 195
 196         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 197         mtdcr (UIC2ER, 0x00000000);     /* disable all */
 198         mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
 199         mtdcr (UIC2PR, 0xffffc8ff);     /* polarity */
 200         mtdcr (UIC2TR, 0x00ff0000);     /* trigger edge vs level */
 201         mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
 202         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 203
 204         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 205         mtdcr (UIC3ER, 0x00000000);     /* disable all */
 206         mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
 207         mtdcr (UIC3PR, 0xffff83ff);     /* polarity */
 208         mtdcr (UIC3TR, 0x00ff8c0f);     /* trigger edge vs level */
 209         mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
 210         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 211
 212         mtdcr (UIC0SR, 0xfc000000);     /* clear all */
 213         mtdcr (UIC0ER, 0x00000000);     /* disable all */
 214         mtdcr (UIC0CR, 0x00000000);     /* all non-critical */
 215         mtdcr (UIC0PR, 0xfc000000);
 216         mtdcr (UIC0TR, 0x00000000);
 217         mtdcr (UIC0VR, 0x00000001);
 218
 219         fpga_init();
 220
 221         return 0;
 222 }
 223
 224 /*************************************************************************
 225  *  checkboard
 226  *
 227  *  Dump pertinent info to the console
 228  ************************************************************************/
 229 int checkboard (void)
 230 {
 231         sys_info_t sysinfo;
 232         unsigned char brd_rev, brd_id;
 233         unsigned short sernum;
 234         unsigned char opto_rev, opto_id;
 235         OPTO_FPGA_REGS_ST *opto_ps;
 236
 237         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 238
 239         opto_rev = (unsigned char)((opto_ps->revision_ul &
 240                                     SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 241                                    >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 242
 243         opto_id = (unsigned char)((opto_ps->revision_ul &
 244                                    SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
 245                                   >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
 246
 247         brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
 248                                    SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
 249                                   >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
 250
 251         brd_id = (unsigned char)((opto_ps->boardinfo_ul &
 252                                   SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
 253                                  >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
 254
 255         get_sys_info (&sysinfo);
 256
 257         sernum = sbcommon_get_serial_number();
 258         printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
 259         printf ("%s\n", METROBOX_U_BOOT_REL_STR);
 260
 261         printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 262         if (sbcommon_get_master()) {
 263                 printf("Slot 0 - Master\nSlave board");
 264                 if (sbcommon_secondary_present())
 265                         printf(" present\n");
 266                 else
 267                         printf(" not detected\n");
 268         } else {
 269                 printf("Slot 1 - Slave\n\n");
 270         }
 271
 272         printf ("OptoFPGA ID:\t0x%02X\tRev:  0x%02X\n", opto_id, opto_rev);
 273         printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, board_id_as[brd_id].name);
 274
 275         /* Fix the ack in the bme 32 */
 276         udelay(5000);
 277         out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 278         asm("eieio");
 279
 280
 281         return (0);
 282 }
 283
 284 /*************************************************************************
 285  *  misc_init_f
 286  *
 287  *  Initialize I2C bus one to gain access to the fans
 288  ************************************************************************/
 289 int misc_init_f (void)
 290 {
 291         /* Turn on fans */
 292         sbcommon_fans();
 293
 294         return (0);
 295 }
 296
 297 /*************************************************************************
 298  *  misc_init_r
 299  *
 300  *  Do nothing.
 301  ************************************************************************/
 302 int misc_init_r (void)
 303 {
 304         unsigned short sernum;
 305         char envstr[255];
 306         uchar enetaddr[6];
 307         unsigned char opto_rev;
 308         OPTO_FPGA_REGS_ST *opto_ps;
 309
 310         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 311
 312         if(NULL != getenv("secondserial")) {
 313             puts("secondserial is set, switching to second serial port\n");
 314             setenv("stderr", "serial1");
 315             setenv("stdout", "serial1");
 316             setenv("stdin", "serial1");
 317         }
 318
 319         setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
 320
 321         memset(envstr, 0, 255);
 322         sprintf (envstr, "Built %s %s by %s",
 323                  U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
 324         setenv("bldstr", envstr);
 325         saveenv();
 326
 327         if( getenv("autorecover")) {
 328                 setenv("autorecover", NULL);
 329                 saveenv();
 330                 sernum = sbcommon_get_serial_number();
 331
 332                 printf("\nSetting up environment for automatic filesystem recovery\n");
 333                 /*
 334                  * Setup default bootargs
 335                  */
 336                 memset(envstr, 0, 255);
 337                 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 338                         "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
 339                         sernum, sernum);
 340                 setenv("bootargs", envstr);
 341
 342                 /*
 343                  * Setup Default boot command
 344                  */
 345                 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
 346                        "fatload ide 0 8100000 pramdisk;"
 347                        "bootm 8000000 8100000");
 348
 349                 printf("Done.  Please type allow the system to continue to boot\n");
 350         }
 351
 352         if( getenv("fakeled")) {
 353                 setenv("bootdelay", "-1");
 354                 saveenv();
 355                 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
 356                 opto_rev = (unsigned char)((opto_ps->revision_ul &
 357                                             SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 358                                            >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 359
 360                 if(0x12 <= opto_rev) {
 361                         opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
 362                 }
 363         }
 364
 365 #ifdef CONFIG_HAS_ETH0
 366         if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
 367                 board_get_enetaddr(0, enetaddr);
 368                 eth_setenv_enetaddr("ethaddr", enetaddr);
 369         }
 370 #endif
 371
 372 #ifdef CONFIG_HAS_ETH1
 373         if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
 374                 board_get_enetaddr(1, enetaddr);
 375                 eth_setenv_enetaddr("eth1addr", enetaddr);
 376         }
 377 #endif
 378
 379 #ifdef CONFIG_HAS_ETH2
 380         if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
 381                 board_get_enetaddr(2, enetaddr);
 382                 eth_setenv_enetaddr("eth2addr", enetaddr);
 383         }
 384 #endif
 385
 386 #ifdef CONFIG_HAS_ETH3
 387         if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
 388                 board_get_enetaddr(3, enetaddr);
 389                 eth_setenv_enetaddr("eth3addr", enetaddr);
 390         }
 391 #endif
 392
 393         return (0);
 394 }
 395
 396 /*************************************************************************
 397  *  ide_set_reset
 398  ************************************************************************/
 399 #ifdef CONFIG_IDE_RESET
 400 void ide_set_reset(int on)
 401 {
 402         OPTO_FPGA_REGS_ST *opto_ps;
 403         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 404
 405         if (on) {               /* assert RESET */
 406             opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
 407         } else {                /* release RESET */
 408             opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
 409         }
 410 }
 411 #endif /* CONFIG_IDE_RESET */
 412
 413 /*************************************************************************
 414  *  fpga_init
 415  ************************************************************************/
 416 void fpga_init(void)
 417 {
 418         OPTO_FPGA_REGS_ST *opto_ps;
 419         unsigned char opto_rev;
 420         unsigned long tmp;
 421
 422         /* Ensure we have power all around */
 423         udelay(500);
 424
 425         /*
 426          * Take appropriate hw bits out of reset
 427          */
 428         opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 429
 430         tmp =
 431             SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
 432             SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
 433             SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
 434             SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
 435             SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
 436             SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
 437             SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
 438             SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
 439             SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
 440             SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
 441             SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
 442             SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
 443             SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
 444             SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
 445             SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
 446             SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
 447             SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
 448             SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
 449         opto_ps->reset_ul = tmp;
 450         /*
 451          * Turn on the 'Slow Blink' for the System Error Led.
 452          * Ensure FPGA rev is up to at least rev 0x12
 453          */
 454         opto_rev = (unsigned char)((opto_ps->revision_ul &
 455                                     SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
 456                                    >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
 457         if(0x12 <= opto_rev) {
 458             opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
 459         }
 460
 461         asm("eieio");
 462
 463         return;
 464 }
 465
 466 int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 467 {
 468         unsigned short sernum;
 469         char envstr[255];
 470
 471         sernum = sbcommon_get_serial_number();
 472
 473         memset(envstr, 0, 255);
 474         /*
 475          * Setup our ip address
 476          */
 477         sprintf(envstr, "10.100.60.%d", sernum);
 478
 479         setenv("ipaddr", envstr);
 480         /*
 481          * Setup the host ip address
 482          */
 483         setenv("serverip", "10.100.17.10");
 484
 485         /*
 486          * Setup default bootargs
 487          */
 488         memset(envstr, 0, 255);
 489
 490         sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
 491                 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
 492                 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
 493                 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
 494                 sernum, sernum, sernum);
 495
 496         setenv("bootargs_nfs", envstr);
 497         setenv("bootargs", envstr);
 498
 499         /*
 500          * Setup CF bootargs
 501          */
 502         memset(envstr, 0, 255);
 503         sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
 504                 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
 505                 sernum, sernum);
 506
 507         setenv("bootargs_cf", envstr);
 508
 509         /*
 510          * Setup Default boot command
 511          */
 512         setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
 513         setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
 514
 515         /*
 516          * Setup compact flash boot command
 517          */
 518         setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
 519
 520         saveenv();
 521
 522
 523         return(1);
 524 }
 525
 526 int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 527 {
 528         unsigned short sernum;
 529         char envstr[255];
 530
 531         sernum = sbcommon_get_serial_number();
 532
 533         printf("\nSetting up environment for filesystem recovery\n");
 534         /*
 535          * Setup default bootargs
 536          */
 537         memset(envstr, 0, 255);
 538         sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
 539                 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
 540                 sernum, sernum);
 541
 542         setenv("bootargs", envstr);
 543
 544         /*
 545          * Setup Default boot command
 546          */
 547         setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
 548                "fatload ide 0 8100000 pramdisk;"
 549                "bootm 8000000 8100000");
 550
 551         printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
 552                " please type fsrecover.sh<cr>\n");
 553
 554         return(1);
 555 }
 556
 557 U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
 558            "Set environment to factory defaults", "");
 559
 560 U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
 561            "Set environment to allow for fs recovery", "");