board/siemens/dxr2/board.c

   1 /*
   2  * Board functions for TI AM335X based dxr2 board
   3  * (C) Copyright 2013 Siemens Schweiz AG
   4  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  *
   8  * Board functions for TI AM335X based boards
   9  * u-boot:/board/ti/am335x/board.c
  10  *
  11  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <errno.h>
  18 #include <spl.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/io.h>
  28 #include <asm/emif.h>
  29 #include <asm/gpio.h>
  30 #include <i2c.h>
  31 #include <miiphy.h>
  32 #include <cpsw.h>
  33 #include <watchdog.h>
  34 #include "board.h"
  35 #include "../common/factoryset.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifdef CONFIG_SPL_BUILD
  40 static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
  41
  42 const struct ddr3_data ddr3_default = {
  43         0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
  44         0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
  45         0x00000618,
  46 };
  47
  48 static void set_default_ddr3_timings(void)
  49 {
  50         printf("Set default DDR3 settings\n");
  51         settings.ddr3 = ddr3_default;
  52 }
  53
  54 static void print_ddr3_timings(void)
  55 {
  56         printf("\n\nDDR3 Timing parameters:\n");
  57         printf("Diff     Eeprom  Default\n");
  58         PRINTARGS(magic);
  59         PRINTARGS(version);
  60         PRINTARGS(ddr3_sratio);
  61         PRINTARGS(iclkout);
  62
  63         PRINTARGS(dt0rdsratio0);
  64         PRINTARGS(dt0wdsratio0);
  65         PRINTARGS(dt0fwsratio0);
  66         PRINTARGS(dt0wrsratio0);
  67
  68         PRINTARGS(sdram_tim1);
  69         PRINTARGS(sdram_tim2);
  70         PRINTARGS(sdram_tim3);
  71
  72         PRINTARGS(emif_ddr_phy_ctlr_1);
  73
  74         PRINTARGS(sdram_config);
  75         PRINTARGS(ref_ctrl);
  76 }
  77
  78 static void print_chip_data(void)
  79 {
  80         printf("\n");
  81         printf("Device: '%s'\n", settings.chip.sdevname);
  82         printf("HW version: '%s'\n", settings.chip.shwver);
  83 }
  84 #endif /* CONFIG_SPL_BUILD */
  85
  86 /*
  87  * Read header information from EEPROM into global structure.
  88  */
  89 static int read_eeprom(void)
  90 {
  91         /* Check if baseboard eeprom is available */
  92         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  93                 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  94                 return 1;
  95         }
  96
  97 #ifdef CONFIG_SPL_BUILD
  98         /* Read Siemens eeprom data (DDR3) */
  99         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
 100                      (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
 101                 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
 102                 set_default_ddr3_timings();
 103         }
 104         /* Read Siemens eeprom data (CHIP) */
 105         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
 106                      (uchar *)&settings.chip, sizeof(settings.chip)))
 107                 printf("Could not read chip settings\n");
 108
 109         if (ddr3_default.magic == settings.ddr3.magic &&
 110             ddr3_default.version == settings.ddr3.version) {
 111                 printf("Using DDR3 settings from EEPROM\n");
 112         } else {
 113                 if (ddr3_default.magic != settings.ddr3.magic)
 114                         printf("Error: No valid DDR3 data in eeprom.\n");
 115                 if (ddr3_default.version != settings.ddr3.version)
 116                         printf("Error: DDR3 data version does not match.\n");
 117
 118                 printf("Using default settings\n");
 119                 set_default_ddr3_timings();
 120         }
 121
 122         if (MAGIC_CHIP == settings.chip.magic) {
 123                 printf("Valid chip data in eeprom\n");
 124                 print_chip_data();
 125         } else {
 126                 printf("Error: No chip data in eeprom\n");
 127         }
 128
 129         print_ddr3_timings();
 130 #endif
 131         return 0;
 132 }
 133
 134 #ifdef CONFIG_SPL_BUILD
 135 static void board_init_ddr(void)
 136 {
 137 struct emif_regs dxr2_ddr3_emif_reg_data = {
 138         .zq_config = 0x50074BE4,
 139 };
 140
 141 struct ddr_data dxr2_ddr3_data = {
 142         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 143 };
 144
 145 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 146         .cmd0dldiff = 0,
 147         .cmd1dldiff = 0,
 148         .cmd2dldiff = 0,
 149 };
 150         /* pass values from eeprom */
 151         dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 152         dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
 153         dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
 154         dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 155                 settings.ddr3.emif_ddr_phy_ctlr_1;
 156         dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
 157         dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 158
 159         dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
 160         dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
 161         dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
 162         dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
 163
 164         dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
 165         dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
 166         dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
 167         dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
 168         dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 169         dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 170
 171         config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
 172                    &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 173 }
 174
 175 static void spl_siemens_board_init(void)
 176 {
 177         return;
 178 }
 179 #endif /* if def CONFIG_SPL_BUILD */
 180
 181 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 182         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 183 static void cpsw_control(int enabled)
 184 {
 185         /* VTP can be added here */
 186
 187         return;
 188 }
 189
 190 static struct cpsw_slave_data cpsw_slaves[] = {
 191         {
 192                 .slave_reg_ofs  = 0x208,
 193                 .sliver_reg_ofs = 0xd80,
 194                 .phy_id         = 0,
 195                 .phy_if         = PHY_INTERFACE_MODE_MII,
 196         },
 197 };
 198
 199 static struct cpsw_platform_data cpsw_data = {
 200         .mdio_base              = CPSW_MDIO_BASE,
 201         .cpsw_base              = CPSW_BASE,
 202         .mdio_div               = 0xff,
 203         .channels               = 4,
 204         .cpdma_reg_ofs          = 0x800,
 205         .slaves                 = 1,
 206         .slave_data             = cpsw_slaves,
 207         .ale_reg_ofs            = 0xd00,
 208         .ale_entries            = 1024,
 209         .host_port_reg_ofs      = 0x108,
 210         .hw_stats_reg_ofs       = 0x900,
 211         .bd_ram_ofs             = 0x2000,
 212         .mac_control            = (1 << 5),
 213         .control                = cpsw_control,
 214         .host_port_num          = 0,
 215         .version                = CPSW_CTRL_VERSION_2,
 216 };
 217
 218 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 219         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
 220 int board_eth_init(bd_t *bis)
 221 {
 222         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 223         int n = 0;
 224         int rv;
 225
 226         factoryset_setenv();
 227
 228         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 229         writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 230
 231         rv = cpsw_register(&cpsw_data);
 232         if (rv < 0)
 233                 printf("Error %d registering CPSW switch\n", rv);
 234         else
 235                 n += rv;
 236         return n;
 237 }
 238 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 239 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 240
 241 #include "../common/board.c"