board/siemens/pxm2/board.c

   1 /*
   2  * Board functions for TI AM335X based pxm2 board
   3  * (C) Copyright 2013 Siemens Schweiz AG
   4  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * u-boot:/board/ti/am335x/board.c
   8  *
   9  * Board functions for TI AM335X based boards
  10  *
  11  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <errno.h>
  18 #include <spl.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include "../../../drivers/video/da8xx-fb.h"
  28 #include <asm/io.h>
  29 #include <asm/emif.h>
  30 #include <asm/gpio.h>
  31 #include <i2c.h>
  32 #include <miiphy.h>
  33 #include <cpsw.h>
  34 #include <watchdog.h>
  35 #include "board.h"
  36 #include "../common/factoryset.h"
  37 #include "pmic.h"
  38 #include <nand.h>
  39 #include <bmp_layout.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #ifdef CONFIG_SPL_BUILD
  44 static void board_init_ddr(void)
  45 {
  46 struct emif_regs pxm2_ddr3_emif_reg_data = {
  47         .sdram_config = 0x41805332,
  48         .sdram_tim1 = 0x666b3c9,
  49         .sdram_tim2 = 0x243631ca,
  50         .sdram_tim3 = 0x33f,
  51         .emif_ddr_phy_ctlr_1 = 0x100005,
  52         .zq_config = 0,
  53         .ref_ctrl = 0x81a,
  54 };
  55
  56 struct ddr_data pxm2_ddr3_data = {
  57         .datardsratio0 = 0x81204812,
  58         .datawdsratio0 = 0,
  59         .datafwsratio0 = 0x8020080,
  60         .datawrsratio0 = 0x4010040,
  61         .datauserank0delay = 1,
  62         .datadldiff0 = PHY_DLL_LOCK_DIFF,
  63 };
  64
  65 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
  66         .cmd0csratio = 0x80,
  67         .cmd0dldiff = 0,
  68         .cmd0iclkout = 0,
  69         .cmd1csratio = 0x80,
  70         .cmd1dldiff = 0,
  71         .cmd1iclkout = 0,
  72         .cmd2csratio = 0x80,
  73         .cmd2dldiff = 0,
  74         .cmd2iclkout = 0,
  75 };
  76
  77         config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
  78                    &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
  79 }
  80
  81 /*
  82  * voltage switching for MPU frequency switching.
  83  * @module = mpu - 0, core - 1
  84  * @vddx_op_vol_sel = vdd voltage to set
  85  */
  86
  87 #define MPU     0
  88 #define CORE    1
  89
  90 int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
  91 {
  92         uchar buf[4];
  93         unsigned int reg_offset;
  94
  95         if (module == MPU)
  96                 reg_offset = PMIC_VDD1_OP_REG;
  97         else
  98                 reg_offset = PMIC_VDD2_OP_REG;
  99
 100         /* Select VDDx OP   */
 101         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 102                 return 1;
 103
 104         buf[0] &= ~PMIC_OP_REG_CMD_MASK;
 105
 106         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 107                 return 1;
 108
 109         /* Configure VDDx OP  Voltage */
 110         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 111                 return 1;
 112
 113         buf[0] &= ~PMIC_OP_REG_SEL_MASK;
 114         buf[0] |= vddx_op_vol_sel;
 115
 116         if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 117                 return 1;
 118
 119         if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
 120                 return 1;
 121
 122         if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
 123                 return 1;
 124
 125         return 0;
 126 }
 127
 128 #define OSC     (V_OSCK/1000000)
 129
 130 const struct dpll_params dpll_mpu_pxm2 = {
 131                 720, OSC-1, 1, -1, -1, -1, -1};
 132
 133 void spl_siemens_board_init(void)
 134 {
 135         uchar buf[4];
 136         /*
 137          * pxm2 PMIC code.  All boards currently want an MPU voltage
 138          * of 1.2625V and CORE voltage of 1.1375V to operate at
 139          * 720MHz.
 140          */
 141         if (i2c_probe(PMIC_CTRL_I2C_ADDR))
 142                 return;
 143
 144         /* VDD1/2 voltage selection register access by control i/f */
 145         if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 146                 return;
 147
 148         buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
 149
 150         if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
 151                 return;
 152
 153         /* Frequency switching for OPP 120 */
 154         if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
 155             voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
 156                 printf("voltage update failed\n");
 157         }
 158 }
 159 #endif /* if def CONFIG_SPL_BUILD */
 160
 161 int read_eeprom(void)
 162 {
 163         /* nothing ToDo here for this board */
 164
 165         return 0;
 166 }
 167
 168 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 169         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 170 static void cpsw_control(int enabled)
 171 {
 172         /* VTP can be added here */
 173
 174         return;
 175 }
 176
 177 static struct cpsw_slave_data cpsw_slaves[] = {
 178         {
 179                 .slave_reg_ofs  = 0x208,
 180                 .sliver_reg_ofs = 0xd80,
 181                 .phy_id         = 0,
 182                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 183         },
 184         {
 185                 .slave_reg_ofs  = 0x308,
 186                 .sliver_reg_ofs = 0xdc0,
 187                 .phy_id         = 1,
 188                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 189         },
 190 };
 191
 192 static struct cpsw_platform_data cpsw_data = {
 193         .mdio_base              = CPSW_MDIO_BASE,
 194         .cpsw_base              = CPSW_BASE,
 195         .mdio_div               = 0xff,
 196         .channels               = 4,
 197         .cpdma_reg_ofs          = 0x800,
 198         .slaves                 = 1,
 199         .slave_data             = cpsw_slaves,
 200         .ale_reg_ofs            = 0xd00,
 201         .ale_entries            = 1024,
 202         .host_port_reg_ofs      = 0x108,
 203         .hw_stats_reg_ofs       = 0x900,
 204         .bd_ram_ofs             = 0x2000,
 205         .mac_control            = (1 << 5),
 206         .control                = cpsw_control,
 207         .host_port_num          = 0,
 208         .version                = CPSW_CTRL_VERSION_2,
 209 };
 210 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 211
 212 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 213         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
 214 int board_eth_init(bd_t *bis)
 215 {
 216         int n = 0;
 217 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 218         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 219         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 220 #ifdef CONFIG_FACTORYSET
 221         int rv;
 222         if (!is_valid_ether_addr(factory_dat.mac))
 223                 printf("Error: no valid mac address\n");
 224         else
 225                 eth_setenv_enetaddr("ethaddr", factory_dat.mac);
 226 #endif /* #ifdef CONFIG_FACTORYSET */
 227
 228         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 229         writel(RGMII_MODE_ENABLE , &cdev->miisel);
 230
 231         rv = cpsw_register(&cpsw_data);
 232         if (rv < 0)
 233                 printf("Error %d registering CPSW switch\n", rv);
 234         else
 235                 n += rv;
 236 #endif
 237         return n;
 238 }
 239 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 240
 241 #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
 242 static struct da8xx_panel lcd_panels[] = {
 243         /* AUO G156XW01 V1 */
 244         [0] = {
 245                 .name = "AUO_G156XW01_V1",
 246                 .width = 1376,
 247                 .height = 768,
 248                 .hfp = 14,
 249                 .hbp = 64,
 250                 .hsw = 56,
 251                 .vfp = 1,
 252                 .vbp = 28,
 253                 .vsw = 3,
 254                 .pxl_clk = 60000000,
 255                 .invert_pxl_clk = 0,
 256         },
 257         /* AUO B101EVN06 V0 */
 258         [1] = {
 259                 .name = "AUO_B101EVN06_V0",
 260                 .width = 1280,
 261                 .height = 800,
 262                 .hfp = 52,
 263                 .hbp = 84,
 264                 .hsw = 36,
 265                 .vfp = 3,
 266                 .vbp = 14,
 267                 .vsw = 6,
 268                 .pxl_clk = 60000000,
 269                 .invert_pxl_clk = 0,
 270         },
 271         /*
 272          * Settings from factoryset
 273          * stored in EEPROM
 274          */
 275         [2] = {
 276                 .name = "factoryset",
 277                 .width = 0,
 278                 .height = 0,
 279                 .hfp = 0,
 280                 .hbp = 0,
 281                 .hsw = 0,
 282                 .vfp = 0,
 283                 .vbp = 0,
 284                 .vsw = 0,
 285                 .pxl_clk = 60000000,
 286                 .invert_pxl_clk = 0,
 287         },
 288 };
 289
 290 static const struct display_panel disp_panel = {
 291         WVGA,
 292         32,
 293         16,
 294         COLOR_ACTIVE,
 295 };
 296
 297 static const struct lcd_ctrl_config lcd_cfg = {
 298         &disp_panel,
 299         .ac_bias                = 255,
 300         .ac_bias_intrpt         = 0,
 301         .dma_burst_sz           = 16,
 302         .bpp                    = 32,
 303         .fdd                    = 0x80,
 304         .tft_alt_mode           = 0,
 305         .stn_565_mode           = 0,
 306         .mono_8bit_mode         = 0,
 307         .invert_line_clock      = 1,
 308         .invert_frm_clock       = 1,
 309         .sync_edge              = 0,
 310         .sync_ctrl              = 1,
 311         .raster_order           = 0,
 312 };
 313
 314 static int set_gpio(int gpio, int state)
 315 {
 316         gpio_request(gpio, "temp");
 317         gpio_direction_output(gpio, state);
 318         gpio_set_value(gpio, state);
 319         gpio_free(gpio);
 320         return 0;
 321 }
 322
 323 static int enable_backlight(void)
 324 {
 325         set_gpio(BOARD_LCD_POWER, 1);
 326         set_gpio(BOARD_BACK_LIGHT, 1);
 327         set_gpio(BOARD_TOUCH_POWER, 1);
 328         return 0;
 329 }
 330
 331 static int enable_pwm(void)
 332 {
 333         struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
 334         struct pwmss_ecap_regs *ecap;
 335         int ticks = PWM_TICKS;
 336         int duty = PWM_DUTY;
 337
 338         ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
 339         /* enable clock */
 340         setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
 341         /* TimeStam Counter register */
 342         writel(0xdb9, &ecap->tsctr);
 343         /* config period */
 344         writel(ticks - 1, &ecap->cap3);
 345         writel(ticks - 1, &ecap->cap1);
 346         setbits_le16(&ecap->ecctl2,
 347                      (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
 348         /* config duty */
 349         writel(duty, &ecap->cap2);
 350         writel(duty, &ecap->cap4);
 351         /* start */
 352         setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
 353         return 0;
 354 }
 355
 356 static struct dpll_regs dpll_lcd_regs = {
 357         .cm_clkmode_dpll = CM_WKUP + 0x98,
 358         .cm_idlest_dpll = CM_WKUP + 0x48,
 359         .cm_clksel_dpll = CM_WKUP + 0x54,
 360 };
 361
 362 /* no console on this board */
 363 int board_cfb_skip(void)
 364 {
 365         return 1;
 366 }
 367
 368 #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
 369 #define PLL_GET_N(v) (v & 0x7f)
 370
 371 static int get_clk(struct dpll_regs *dpll_regs)
 372 {
 373         unsigned int val;
 374         unsigned int m, n;
 375         int f = 0;
 376
 377         val = readl(dpll_regs->cm_clksel_dpll);
 378         m = PLL_GET_M(val);
 379         n = PLL_GET_N(val);
 380         f = (m * V_OSCK) / n;
 381
 382         return f;
 383 };
 384
 385 int clk_get(int clk)
 386 {
 387         return get_clk(&dpll_lcd_regs);
 388 };
 389
 390 static int conf_disp_pll(int m, int n)
 391 {
 392         struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 393         struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
 394         struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
 395
 396         u32 *const clk_domains[] = {
 397                 &cmper->lcdclkctrl,
 398                 0
 399         };
 400         u32 *const clk_modules_explicit_en[] = {
 401                 &cmper->lcdclkctrl,
 402                 &cmper->lcdcclkstctrl,
 403                 &cmper->epwmss0clkctrl,
 404                 0
 405         };
 406         do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
 407         writel(0x0, &cmdpll->clklcdcpixelclk);
 408
 409         do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
 410
 411         return 0;
 412 }
 413
 414 static int board_video_init(void)
 415 {
 416         /* set 300 MHz */
 417         conf_disp_pll(25, 2);
 418         if (factory_dat.pxm50)
 419                 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
 420         else
 421                 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
 422
 423         enable_pwm();
 424         enable_backlight();
 425
 426         return 0;
 427 }
 428 #endif
 429 #include "../common/board.c"