board/taskit/stamp9g20/stamp9g20.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * Achim Ehrlich <aehrlich@taskit.de>
   7  * taskit GmbH <www.taskit.de>
   8  *
   9  * (C) Copyright 2012-
  10  * Markus Hubig <mhubig@imko.de>
  11  * IMKO GmbH <www.imko.de>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/at91sam9260_matrix.h>
  19 #include <asm/arch/at91sam9_smc.h>
  20 #include <asm/arch/at91_common.h>
  21 #include <asm/arch/at91_pmc.h>
  22 #include <asm/arch/gpio.h>
  23 #include <watchdog.h>
  24
  25 #ifdef CONFIG_MACB
  26 # include <net.h>
  27 # include <netdev.h>
  28 #endif
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 static void stamp9G20_nand_hw_init(void)
  33 {
  34         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  35         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  36         unsigned long csa;
  37
  38         /* Assign CS3 to NAND/SmartMedia Interface */
  39         csa = readl(&matrix->ebicsa);
  40         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  41         writel(csa, &matrix->ebicsa);
  42
  43         /* Configure SMC CS3 for NAND/SmartMedia */
  44         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  45                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  46                 &smc->cs[3].setup);
  47         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  48                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  49                 &smc->cs[3].pulse);
  50         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  51                 &smc->cs[3].cycle);
  52         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  53                 AT91_SMC_MODE_EXNW_DISABLE |
  54                 AT91_SMC_MODE_DBW_8 |
  55                 AT91_SMC_MODE_TDF_CYCLE(2),
  56                 &smc->cs[3].mode);
  57
  58         /* Configure RDY/BSY */
  59         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  60
  61         /* Enable NandFlash */
  62         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  63 }
  64
  65 #ifdef CONFIG_MACB
  66 static void stamp9G20_macb_hw_init(void)
  67 {
  68         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  69
  70         /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
  71         at91_set_gpio_output(AT91_PIN_PA26, 0);
  72
  73         /*
  74          * Disable pull-up on:
  75          *      RXDV (PA17) => PHY normal mode (not Test mode)
  76          *      ERX0 (PA14) => PHY ADDR0
  77          *      ERX1 (PA15) => PHY ADDR1
  78          *      ERX2 (PA25) => PHY ADDR2
  79          *      ERX3 (PA26) => PHY ADDR3
  80          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
  81          *
  82          * PHY has internal pull-down
  83          */
  84         writel(pin_to_mask(AT91_PIN_PA14) |
  85                 pin_to_mask(AT91_PIN_PA15) |
  86                 pin_to_mask(AT91_PIN_PA17) |
  87                 pin_to_mask(AT91_PIN_PA18) |
  88                 pin_to_mask(AT91_PIN_PA28),
  89                 &pioa->pudr);
  90
  91         at91_phy_reset();
  92
  93         /* Re-enable pull-up */
  94         writel(pin_to_mask(AT91_PIN_PA14) |
  95                 pin_to_mask(AT91_PIN_PA15) |
  96                 pin_to_mask(AT91_PIN_PA17) |
  97                 pin_to_mask(AT91_PIN_PA18) |
  98                 pin_to_mask(AT91_PIN_PA28),
  99                 &pioa->puer);
 100
 101         /* Initialize EMAC=MACB hardware */
 102         at91_macb_hw_init();
 103 }
 104 #endif /* CONFIG_MACB */
 105
 106 int board_early_init_f(void)
 107 {
 108         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 109
 110         /* Enable clocks for all PIOs */
 111         writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
 112                 (1 << ATMEL_ID_PIOC), &pmc->pcer);
 113
 114         return 0;
 115 }
 116
 117 int board_postclk_init(void)
 118 {
 119         /*
 120          * Initialize the serial interface here, because be need a running
 121          * timer to set PC9 to high and wait for some time to enable the
 122          * level converter of the RS232 interface on the PortuxG20 board.
 123          */
 124
 125 #ifdef CONFIG_PORTUXG20
 126         at91_set_gpio_output(AT91_PIN_PC9, 1);
 127         mdelay(1);
 128 #endif
 129         at91_seriald_hw_init();
 130
 131         return 0;
 132 }
 133
 134 int board_init(void)
 135 {
 136         /* Adress of boot parameters */
 137         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 138
 139         stamp9G20_nand_hw_init();
 140 #ifdef CONFIG_MACB
 141         stamp9G20_macb_hw_init();
 142 #endif
 143         return 0;
 144 }
 145
 146 int dram_init(void)
 147 {
 148         gd->ram_size = get_ram_size(
 149                 (void *)CONFIG_SYS_SDRAM_BASE,
 150                 CONFIG_SYS_SDRAM_SIZE);
 151         return 0;
 152 }
 153
 154 #ifdef CONFIG_MACB
 155 int board_eth_init(bd_t *bis)
 156 {
 157         return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 158 }
 159 #endif /* CONFIG_MACB */