board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mem.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <i2c.h>
  27 #include <miiphy.h>
  28 #include <cpsw.h>
  29 #include "board.h"
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 /* MII mode defines */
  34 #define MII_MODE_ENABLE         0x0
  35 #define RGMII_MODE_ENABLE       0x3A
  36
  37 /* GPIO that controls power to DDR on EVM-SK */
  38 #define GPIO_DDR_VTT_EN         7
  39
  40 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  41
  42 /*
  43  * Read header information from EEPROM into global structure.
  44  */
  45 static int read_eeprom(struct am335x_baseboard_id *header)
  46 {
  47         /* Check if baseboard eeprom is available */
  48         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  49                 puts("Could not probe the EEPROM; something fundamentally "
  50                         "wrong on the I2C bus.\n");
  51                 return -ENODEV;
  52         }
  53
  54         /* read the eeprom using i2c */
  55         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  56                      sizeof(struct am335x_baseboard_id))) {
  57                 puts("Could not read the EEPROM; something fundamentally"
  58                         " wrong on the I2C bus.\n");
  59                 return -EIO;
  60         }
  61
  62         if (header->magic != 0xEE3355AA) {
  63                 /*
  64                  * read the eeprom using i2c again,
  65                  * but use only a 1 byte address
  66                  */
  67                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  68                              sizeof(struct am335x_baseboard_id))) {
  69                         puts("Could not read the EEPROM; something "
  70                                 "fundamentally wrong on the I2C bus.\n");
  71                         return -EIO;
  72                 }
  73
  74                 if (header->magic != 0xEE3355AA) {
  75                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  76                                         header->magic);
  77                         return -EINVAL;
  78                 }
  79         }
  80
  81         return 0;
  82 }
  83
  84 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
  85 static const struct ddr_data ddr2_data = {
  86         .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
  87                           (MT47H128M16RT25E_RD_DQS<<20) |
  88                           (MT47H128M16RT25E_RD_DQS<<10) |
  89                           (MT47H128M16RT25E_RD_DQS<<0)),
  90         .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
  91                           (MT47H128M16RT25E_WR_DQS<<20) |
  92                           (MT47H128M16RT25E_WR_DQS<<10) |
  93                           (MT47H128M16RT25E_WR_DQS<<0)),
  94         .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
  95                          (MT47H128M16RT25E_PHY_WRLVL<<20) |
  96                          (MT47H128M16RT25E_PHY_WRLVL<<10) |
  97                          (MT47H128M16RT25E_PHY_WRLVL<<0)),
  98         .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
  99                          (MT47H128M16RT25E_PHY_GATELVL<<20) |
 100                          (MT47H128M16RT25E_PHY_GATELVL<<10) |
 101                          (MT47H128M16RT25E_PHY_GATELVL<<0)),
 102         .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
 103                           (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
 104                           (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
 105                           (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
 106         .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
 107                           (MT47H128M16RT25E_PHY_WR_DATA<<20) |
 108                           (MT47H128M16RT25E_PHY_WR_DATA<<10) |
 109                           (MT47H128M16RT25E_PHY_WR_DATA<<0)),
 110         .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
 111         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 112 };
 113
 114 static const struct cmd_control ddr2_cmd_ctrl_data = {
 115         .cmd0csratio = MT47H128M16RT25E_RATIO,
 116         .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 117         .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 118
 119         .cmd1csratio = MT47H128M16RT25E_RATIO,
 120         .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 121         .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 122
 123         .cmd2csratio = MT47H128M16RT25E_RATIO,
 124         .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 125         .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 126 };
 127
 128 static const struct emif_regs ddr2_emif_reg_data = {
 129         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 130         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 131         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 132         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 133         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 134         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 135 };
 136
 137 static const struct ddr_data ddr3_data = {
 138         .datardsratio0 = MT41J128MJT125_RD_DQS,
 139         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 140         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 141         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 142         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 143 };
 144
 145 static const struct ddr_data ddr3_beagleblack_data = {
 146         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 147         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 148         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 149         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 150         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 151 };
 152
 153 static const struct ddr_data ddr3_evm_data = {
 154         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 155         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 156         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 157         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 158         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 159 };
 160
 161 static const struct cmd_control ddr3_cmd_ctrl_data = {
 162         .cmd0csratio = MT41J128MJT125_RATIO,
 163         .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 164         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 165
 166         .cmd1csratio = MT41J128MJT125_RATIO,
 167         .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 168         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 169
 170         .cmd2csratio = MT41J128MJT125_RATIO,
 171         .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 172         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 173 };
 174
 175 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 176         .cmd0csratio = MT41K256M16HA125E_RATIO,
 177         .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 178         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 179
 180         .cmd1csratio = MT41K256M16HA125E_RATIO,
 181         .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 182         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 183
 184         .cmd2csratio = MT41K256M16HA125E_RATIO,
 185         .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 186         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 187 };
 188
 189 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 190         .cmd0csratio = MT41J512M8RH125_RATIO,
 191         .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 192         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 193
 194         .cmd1csratio = MT41J512M8RH125_RATIO,
 195         .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 196         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 197
 198         .cmd2csratio = MT41J512M8RH125_RATIO,
 199         .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 200         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 201 };
 202
 203 static struct emif_regs ddr3_emif_reg_data = {
 204         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 205         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 206         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 207         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 208         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 209         .zq_config = MT41J128MJT125_ZQ_CFG,
 210         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 211                                 PHY_EN_DYN_PWRDN,
 212 };
 213
 214 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 215         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 216         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 217         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 218         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 219         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 220         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 221         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 222 };
 223
 224 static struct emif_regs ddr3_evm_emif_reg_data = {
 225         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 226         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 227         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 228         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 229         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 230         .zq_config = MT41J512M8RH125_ZQ_CFG,
 231         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 232                                 PHY_EN_DYN_PWRDN,
 233 };
 234
 235 #ifdef CONFIG_SPL_OS_BOOT
 236 int spl_start_uboot(void)
 237 {
 238         /* break into full u-boot on 'c' */
 239         return (serial_tstc() && serial_getc() == 'c');
 240 }
 241 #endif
 242
 243 #define OSC     (V_OSCK/1000000)
 244 const struct dpll_params dpll_ddr = {
 245                 266, OSC-1, 1, -1, -1, -1, -1};
 246 const struct dpll_params dpll_ddr_evm_sk = {
 247                 303, OSC-1, 1, -1, -1, -1, -1};
 248 const struct dpll_params dpll_ddr_bone_black = {
 249                 400, OSC-1, 1, -1, -1, -1, -1};
 250
 251 const struct dpll_params *get_dpll_ddr_params(void)
 252 {
 253         struct am335x_baseboard_id header;
 254
 255         enable_i2c0_pin_mux();
 256         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 257         if (read_eeprom(&header) < 0)
 258                 puts("Could not get board ID.\n");
 259
 260         if (board_is_evm_sk(&header))
 261                 return &dpll_ddr_evm_sk;
 262         else if (board_is_bone_lt(&header))
 263                 return &dpll_ddr_bone_black;
 264         else if (board_is_evm_15_or_later(&header))
 265                 return &dpll_ddr_evm_sk;
 266         else
 267                 return &dpll_ddr;
 268 }
 269
 270 void set_uart_mux_conf(void)
 271 {
 272 #ifdef CONFIG_SERIAL1
 273         enable_uart0_pin_mux();
 274 #endif /* CONFIG_SERIAL1 */
 275 #ifdef CONFIG_SERIAL2
 276         enable_uart1_pin_mux();
 277 #endif /* CONFIG_SERIAL2 */
 278 #ifdef CONFIG_SERIAL3
 279         enable_uart2_pin_mux();
 280 #endif /* CONFIG_SERIAL3 */
 281 #ifdef CONFIG_SERIAL4
 282         enable_uart3_pin_mux();
 283 #endif /* CONFIG_SERIAL4 */
 284 #ifdef CONFIG_SERIAL5
 285         enable_uart4_pin_mux();
 286 #endif /* CONFIG_SERIAL5 */
 287 #ifdef CONFIG_SERIAL6
 288         enable_uart5_pin_mux();
 289 #endif /* CONFIG_SERIAL6 */
 290 }
 291
 292 void set_mux_conf_regs(void)
 293 {
 294         __maybe_unused struct am335x_baseboard_id header;
 295
 296         if (read_eeprom(&header) < 0)
 297                 puts("Could not get board ID.\n");
 298
 299         enable_board_pin_mux(&header);
 300 }
 301
 302 void sdram_init(void)
 303 {
 304         __maybe_unused struct am335x_baseboard_id header;
 305
 306         if (read_eeprom(&header) < 0)
 307                 puts("Could not get board ID.\n");
 308
 309         if (board_is_evm_sk(&header)) {
 310                 /*
 311                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 312                  * This is safe enough to do on older revs.
 313                  */
 314                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 315                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 316         }
 317
 318         if (board_is_evm_sk(&header))
 319                 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
 320                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 321         else if (board_is_bone_lt(&header))
 322                 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
 323                            &ddr3_beagleblack_data,
 324                            &ddr3_beagleblack_cmd_ctrl_data,
 325                            &ddr3_beagleblack_emif_reg_data, 0);
 326         else if (board_is_evm_15_or_later(&header))
 327                 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
 328                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 329         else
 330                 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
 331                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 332 }
 333 #endif
 334
 335 /*
 336  * Basic board specific setup.  Pinmux has been handled already.
 337  */
 338 int board_init(void)
 339 {
 340 #ifdef CONFIG_NOR
 341         const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
 342                 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
 343                 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
 344 #endif
 345
 346         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 347
 348         gpmc_init();
 349
 350 #ifdef CONFIG_NOR
 351         /* Reconfigure CS0 for NOR instead of NAND. */
 352         enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
 353                               CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
 354 #endif
 355
 356         return 0;
 357 }
 358
 359 #ifdef CONFIG_BOARD_LATE_INIT
 360 int board_late_init(void)
 361 {
 362 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 363         char safe_string[HDR_NAME_LEN + 1];
 364         struct am335x_baseboard_id header;
 365
 366         if (read_eeprom(&header) < 0)
 367                 puts("Could not get board ID.\n");
 368
 369         /* Now set variables based on the header. */
 370         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 371         safe_string[sizeof(header.name)] = 0;
 372         setenv("board_name", safe_string);
 373
 374         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 375         safe_string[sizeof(header.version)] = 0;
 376         setenv("board_rev", safe_string);
 377 #endif
 378
 379         return 0;
 380 }
 381 #endif
 382
 383 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 384         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 385 static void cpsw_control(int enabled)
 386 {
 387         /* VTP can be added here */
 388
 389         return;
 390 }
 391
 392 static struct cpsw_slave_data cpsw_slaves[] = {
 393         {
 394                 .slave_reg_ofs  = 0x208,
 395                 .sliver_reg_ofs = 0xd80,
 396                 .phy_id         = 0,
 397         },
 398         {
 399                 .slave_reg_ofs  = 0x308,
 400                 .sliver_reg_ofs = 0xdc0,
 401                 .phy_id         = 1,
 402         },
 403 };
 404
 405 static struct cpsw_platform_data cpsw_data = {
 406         .mdio_base              = CPSW_MDIO_BASE,
 407         .cpsw_base              = CPSW_BASE,
 408         .mdio_div               = 0xff,
 409         .channels               = 8,
 410         .cpdma_reg_ofs          = 0x800,
 411         .slaves                 = 1,
 412         .slave_data             = cpsw_slaves,
 413         .ale_reg_ofs            = 0xd00,
 414         .ale_entries            = 1024,
 415         .host_port_reg_ofs      = 0x108,
 416         .hw_stats_reg_ofs       = 0x900,
 417         .bd_ram_ofs             = 0x2000,
 418         .mac_control            = (1 << 5),
 419         .control                = cpsw_control,
 420         .host_port_num          = 0,
 421         .version                = CPSW_CTRL_VERSION_2,
 422 };
 423 #endif
 424
 425 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 426         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
 427 int board_eth_init(bd_t *bis)
 428 {
 429         int rv, n = 0;
 430         uint8_t mac_addr[6];
 431         uint32_t mac_hi, mac_lo;
 432         __maybe_unused struct am335x_baseboard_id header;
 433
 434         /* try reading mac address from efuse */
 435         mac_lo = readl(&cdev->macid0l);
 436         mac_hi = readl(&cdev->macid0h);
 437         mac_addr[0] = mac_hi & 0xFF;
 438         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 439         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 440         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 441         mac_addr[4] = mac_lo & 0xFF;
 442         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 443
 444 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 445         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 446         if (!getenv("ethaddr")) {
 447                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 448
 449                 if (is_valid_ether_addr(mac_addr))
 450                         eth_setenv_enetaddr("ethaddr", mac_addr);
 451         }
 452
 453 #ifdef CONFIG_DRIVER_TI_CPSW
 454         if (read_eeprom(&header) < 0)
 455                 puts("Could not get board ID.\n");
 456
 457         if (board_is_bone(&header) || board_is_bone_lt(&header) ||
 458             board_is_idk(&header)) {
 459                 writel(MII_MODE_ENABLE, &cdev->miisel);
 460                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 461                                 PHY_INTERFACE_MODE_MII;
 462         } else {
 463                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 464                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 465                                 PHY_INTERFACE_MODE_RGMII;
 466         }
 467
 468         rv = cpsw_register(&cpsw_data);
 469         if (rv < 0)
 470                 printf("Error %d registering CPSW switch\n", rv);
 471         else
 472                 n += rv;
 473 #endif
 474
 475         /*
 476          *
 477          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 478          * operating points.  So we must set the TX clock delay feature
 479          * in the AR8051 PHY.  Since we only support a single ethernet
 480          * device in U-Boot, we only do this for the first instance.
 481          */
 482 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 483 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 484 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 485 #define AR8051_RGMII_TX_CLK_DLY         0x100
 486
 487         if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
 488                 const char *devname;
 489                 devname = miiphy_get_current_dev();
 490
 491                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 492                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 493                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 494                                 AR8051_RGMII_TX_CLK_DLY);
 495         }
 496 #endif
 497 #if defined(CONFIG_USB_ETHER) && \
 498         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 499         if (is_valid_ether_addr(mac_addr))
 500                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 501
 502         rv = usb_eth_initialize(bis);
 503         if (rv < 0)
 504                 printf("Error %d registering USB_ETHER\n", rv);
 505         else
 506                 n += rv;
 507 #endif
 508         return n;
 509 }
 510 #endif