board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <spl.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/omap.h>
  17 #include <asm/arch/ddr_defs.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/mmc_host_def.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mem.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <i2c.h>
  27 #include <miiphy.h>
  28 #include <cpsw.h>
  29 #include <power/tps65217.h>
  30 #include <power/tps65910.h>
  31 #include <environment.h>
  32 #include <watchdog.h>
  33 #include <environment.h>
  34 #include "board.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 /* GPIO that controls power to DDR on EVM-SK */
  39 #define GPIO_DDR_VTT_EN         7
  40
  41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  42
  43 /*
  44  * Read header information from EEPROM into global structure.
  45  */
  46 static int read_eeprom(struct am335x_baseboard_id *header)
  47 {
  48         /* Check if baseboard eeprom is available */
  49         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  50                 puts("Could not probe the EEPROM; something fundamentally "
  51                         "wrong on the I2C bus.\n");
  52                 return -ENODEV;
  53         }
  54
  55         /* read the eeprom using i2c */
  56         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  57                      sizeof(struct am335x_baseboard_id))) {
  58                 puts("Could not read the EEPROM; something fundamentally"
  59                         " wrong on the I2C bus.\n");
  60                 return -EIO;
  61         }
  62
  63         if (header->magic != 0xEE3355AA) {
  64                 /*
  65                  * read the eeprom using i2c again,
  66                  * but use only a 1 byte address
  67                  */
  68                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  69                              sizeof(struct am335x_baseboard_id))) {
  70                         puts("Could not read the EEPROM; something "
  71                                 "fundamentally wrong on the I2C bus.\n");
  72                         return -EIO;
  73                 }
  74
  75                 if (header->magic != 0xEE3355AA) {
  76                         printf("Incorrect magic number (0x%x) in EEPROM\n",
  77                                         header->magic);
  78                         return -EINVAL;
  79                 }
  80         }
  81
  82         return 0;
  83 }
  84
  85 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  86 static const struct ddr_data ddr2_data = {
  87         .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
  88                           (MT47H128M16RT25E_RD_DQS<<20) |
  89                           (MT47H128M16RT25E_RD_DQS<<10) |
  90                           (MT47H128M16RT25E_RD_DQS<<0)),
  91         .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
  92                           (MT47H128M16RT25E_WR_DQS<<20) |
  93                           (MT47H128M16RT25E_WR_DQS<<10) |
  94                           (MT47H128M16RT25E_WR_DQS<<0)),
  95         .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
  96                          (MT47H128M16RT25E_PHY_WRLVL<<20) |
  97                          (MT47H128M16RT25E_PHY_WRLVL<<10) |
  98                          (MT47H128M16RT25E_PHY_WRLVL<<0)),
  99         .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
 100                          (MT47H128M16RT25E_PHY_GATELVL<<20) |
 101                          (MT47H128M16RT25E_PHY_GATELVL<<10) |
 102                          (MT47H128M16RT25E_PHY_GATELVL<<0)),
 103         .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
 104                           (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
 105                           (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
 106                           (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
 107         .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
 108                           (MT47H128M16RT25E_PHY_WR_DATA<<20) |
 109                           (MT47H128M16RT25E_PHY_WR_DATA<<10) |
 110                           (MT47H128M16RT25E_PHY_WR_DATA<<0)),
 111 };
 112
 113 static const struct cmd_control ddr2_cmd_ctrl_data = {
 114         .cmd0csratio = MT47H128M16RT25E_RATIO,
 115         .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 116
 117         .cmd1csratio = MT47H128M16RT25E_RATIO,
 118         .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 119
 120         .cmd2csratio = MT47H128M16RT25E_RATIO,
 121         .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 122 };
 123
 124 static const struct emif_regs ddr2_emif_reg_data = {
 125         .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 126         .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 127         .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 128         .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 129         .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 130         .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 131 };
 132
 133 static const struct ddr_data ddr3_data = {
 134         .datardsratio0 = MT41J128MJT125_RD_DQS,
 135         .datawdsratio0 = MT41J128MJT125_WR_DQS,
 136         .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 137         .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 138 };
 139
 140 static const struct ddr_data ddr3_beagleblack_data = {
 141         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
 142         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 143         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 144         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 145 };
 146
 147 static const struct ddr_data ddr3_evm_data = {
 148         .datardsratio0 = MT41J512M8RH125_RD_DQS,
 149         .datawdsratio0 = MT41J512M8RH125_WR_DQS,
 150         .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 151         .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 152 };
 153
 154 static const struct cmd_control ddr3_cmd_ctrl_data = {
 155         .cmd0csratio = MT41J128MJT125_RATIO,
 156         .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 157
 158         .cmd1csratio = MT41J128MJT125_RATIO,
 159         .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 160
 161         .cmd2csratio = MT41J128MJT125_RATIO,
 162         .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 163 };
 164
 165 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 166         .cmd0csratio = MT41K256M16HA125E_RATIO,
 167         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 168
 169         .cmd1csratio = MT41K256M16HA125E_RATIO,
 170         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 171
 172         .cmd2csratio = MT41K256M16HA125E_RATIO,
 173         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 174 };
 175
 176 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 177         .cmd0csratio = MT41J512M8RH125_RATIO,
 178         .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 179
 180         .cmd1csratio = MT41J512M8RH125_RATIO,
 181         .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 182
 183         .cmd2csratio = MT41J512M8RH125_RATIO,
 184         .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 185 };
 186
 187 static struct emif_regs ddr3_emif_reg_data = {
 188         .sdram_config = MT41J128MJT125_EMIF_SDCFG,
 189         .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 190         .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 191         .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 192         .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 193         .zq_config = MT41J128MJT125_ZQ_CFG,
 194         .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 195                                 PHY_EN_DYN_PWRDN,
 196 };
 197
 198 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 199         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 200         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 201         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 202         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 203         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 204         .zq_config = MT41K256M16HA125E_ZQ_CFG,
 205         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 206 };
 207
 208 static struct emif_regs ddr3_evm_emif_reg_data = {
 209         .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 210         .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 211         .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 212         .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 213         .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 214         .zq_config = MT41J512M8RH125_ZQ_CFG,
 215         .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 216                                 PHY_EN_DYN_PWRDN,
 217 };
 218
 219 #ifdef CONFIG_SPL_OS_BOOT
 220 int spl_start_uboot(void)
 221 {
 222         /* break into full u-boot on 'c' */
 223         if (serial_tstc() && serial_getc() == 'c')
 224                 return 1;
 225
 226 #ifdef CONFIG_SPL_ENV_SUPPORT
 227         env_init();
 228         env_relocate_spec();
 229         if (getenv_yesno("boot_os") != 1)
 230                 return 1;
 231 #endif
 232
 233         return 0;
 234 }
 235 #endif
 236
 237 #define OSC     (V_OSCK/1000000)
 238 const struct dpll_params dpll_ddr = {
 239                 266, OSC-1, 1, -1, -1, -1, -1};
 240 const struct dpll_params dpll_ddr_evm_sk = {
 241                 303, OSC-1, 1, -1, -1, -1, -1};
 242 const struct dpll_params dpll_ddr_bone_black = {
 243                 400, OSC-1, 1, -1, -1, -1, -1};
 244
 245 void am33xx_spl_board_init(void)
 246 {
 247         struct am335x_baseboard_id header;
 248         int mpu_vdd;
 249
 250         if (read_eeprom(&header) < 0)
 251                 puts("Could not get board ID.\n");
 252
 253         /* Get the frequency */
 254         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 255
 256         if (board_is_bone(&header) || board_is_bone_lt(&header)) {
 257                 /* BeagleBone PMIC Code */
 258                 int usb_cur_lim;
 259
 260                 /*
 261                  * Only perform PMIC configurations if board rev > A1
 262                  * on Beaglebone White
 263                  */
 264                 if (board_is_bone(&header) && !strncmp(header.version,
 265                                                        "00A1", 4))
 266                         return;
 267
 268                 if (i2c_probe(TPS65217_CHIP_PM))
 269                         return;
 270
 271                 /*
 272                  * On Beaglebone White we need to ensure we have AC power
 273                  * before increasing the frequency.
 274                  */
 275                 if (board_is_bone(&header)) {
 276                         uchar pmic_status_reg;
 277                         if (tps65217_reg_read(TPS65217_STATUS,
 278                                               &pmic_status_reg))
 279                                 return;
 280                         if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 281                                 puts("No AC power, disabling frequency switch\n");
 282                                 return;
 283                         }
 284                 }
 285
 286                 /*
 287                  * Override what we have detected since we know if we have
 288                  * a Beaglebone Black it supports 1GHz.
 289                  */
 290                 if (board_is_bone_lt(&header))
 291                         dpll_mpu_opp100.m = MPUPLL_M_1000;
 292
 293                 /*
 294                  * Increase USB current limit to 1300mA or 1800mA and set
 295                  * the MPU voltage controller as needed.
 296                  */
 297                 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 298                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 299                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 300                 } else {
 301                         usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 302                         mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 303                 }
 304
 305                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 306                                        TPS65217_POWER_PATH,
 307                                        usb_cur_lim,
 308                                        TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 309                         puts("tps65217_reg_write failure\n");
 310
 311                 /* Set DCDC3 (CORE) voltage to 1.125V */
 312                 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 313                                             TPS65217_DCDC_VOLT_SEL_1125MV)) {
 314                         puts("tps65217_voltage_update failure\n");
 315                         return;
 316                 }
 317
 318                 /* Set CORE Frequencies to OPP100 */
 319                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 320
 321                 /* Set DCDC2 (MPU) voltage */
 322                 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 323                         puts("tps65217_voltage_update failure\n");
 324                         return;
 325                 }
 326
 327                 /*
 328                  * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 329                  * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 330                  */
 331                 if (board_is_bone(&header)) {
 332                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 333                                                TPS65217_DEFLS1,
 334                                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 335                                                TPS65217_LDO_MASK))
 336                                 puts("tps65217_reg_write failure\n");
 337                 } else {
 338                         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 339                                                TPS65217_DEFLS1,
 340                                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 341                                                TPS65217_LDO_MASK))
 342                                 puts("tps65217_reg_write failure\n");
 343                 }
 344
 345                 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 346                                        TPS65217_DEFLS2,
 347                                        TPS65217_LDO_VOLTAGE_OUT_3_3,
 348                                        TPS65217_LDO_MASK))
 349                         puts("tps65217_reg_write failure\n");
 350         } else {
 351                 int sil_rev;
 352
 353                 /*
 354                  * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 355                  * MPU frequencies we support we use a CORE voltage of
 356                  * 1.1375V.  For MPU voltage we need to switch based on
 357                  * the frequency we are running at.
 358                  */
 359                 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 360                         return;
 361
 362                 /*
 363                  * Depending on MPU clock and PG we will need a different
 364                  * VDD to drive at that speed.
 365                  */
 366                 sil_rev = readl(&cdev->deviceid) >> 28;
 367                 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 368                                                       dpll_mpu_opp100.m);
 369
 370                 /* Tell the TPS65910 to use i2c */
 371                 tps65910_set_i2c_control();
 372
 373                 /* First update MPU voltage. */
 374                 if (tps65910_voltage_update(MPU, mpu_vdd))
 375                         return;
 376
 377                 /* Second, update the CORE voltage. */
 378                 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 379                         return;
 380
 381                 /* Set CORE Frequencies to OPP100 */
 382                 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 383         }
 384
 385         /* Set MPU Frequency to what we detected now that voltages are set */
 386         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 387 }
 388
 389 const struct dpll_params *get_dpll_ddr_params(void)
 390 {
 391         struct am335x_baseboard_id header;
 392
 393         enable_i2c0_pin_mux();
 394         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 395         if (read_eeprom(&header) < 0)
 396                 puts("Could not get board ID.\n");
 397
 398         if (board_is_evm_sk(&header))
 399                 return &dpll_ddr_evm_sk;
 400         else if (board_is_bone_lt(&header))
 401                 return &dpll_ddr_bone_black;
 402         else if (board_is_evm_15_or_later(&header))
 403                 return &dpll_ddr_evm_sk;
 404         else
 405                 return &dpll_ddr;
 406 }
 407
 408 void set_uart_mux_conf(void)
 409 {
 410 #ifdef CONFIG_SERIAL1
 411         enable_uart0_pin_mux();
 412 #endif /* CONFIG_SERIAL1 */
 413 #ifdef CONFIG_SERIAL2
 414         enable_uart1_pin_mux();
 415 #endif /* CONFIG_SERIAL2 */
 416 #ifdef CONFIG_SERIAL3
 417         enable_uart2_pin_mux();
 418 #endif /* CONFIG_SERIAL3 */
 419 #ifdef CONFIG_SERIAL4
 420         enable_uart3_pin_mux();
 421 #endif /* CONFIG_SERIAL4 */
 422 #ifdef CONFIG_SERIAL5
 423         enable_uart4_pin_mux();
 424 #endif /* CONFIG_SERIAL5 */
 425 #ifdef CONFIG_SERIAL6
 426         enable_uart5_pin_mux();
 427 #endif /* CONFIG_SERIAL6 */
 428 }
 429
 430 void set_mux_conf_regs(void)
 431 {
 432         __maybe_unused struct am335x_baseboard_id header;
 433
 434         if (read_eeprom(&header) < 0)
 435                 puts("Could not get board ID.\n");
 436
 437         enable_board_pin_mux(&header);
 438 }
 439
 440 const struct ctrl_ioregs ioregs_evmsk = {
 441         .cm0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 442         .cm1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 443         .cm2ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 444         .dt0ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 445         .dt1ioctl               = MT41J128MJT125_IOCTRL_VALUE,
 446 };
 447
 448 const struct ctrl_ioregs ioregs_bonelt = {
 449         .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 450         .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 451         .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 452         .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 453         .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
 454 };
 455
 456 const struct ctrl_ioregs ioregs_evm15 = {
 457         .cm0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 458         .cm1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 459         .cm2ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 460         .dt0ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 461         .dt1ioctl               = MT41J512M8RH125_IOCTRL_VALUE,
 462 };
 463
 464 const struct ctrl_ioregs ioregs = {
 465         .cm0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 466         .cm1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 467         .cm2ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 468         .dt0ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 469         .dt1ioctl               = MT47H128M16RT25E_IOCTRL_VALUE,
 470 };
 471
 472 void sdram_init(void)
 473 {
 474         __maybe_unused struct am335x_baseboard_id header;
 475
 476         if (read_eeprom(&header) < 0)
 477                 puts("Could not get board ID.\n");
 478
 479         if (board_is_evm_sk(&header)) {
 480                 /*
 481                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 482                  * This is safe enough to do on older revs.
 483                  */
 484                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 485                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 486         }
 487
 488         if (board_is_evm_sk(&header))
 489                 config_ddr(303, &ioregs_evmsk, &ddr3_data,
 490                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 491         else if (board_is_bone_lt(&header))
 492                 config_ddr(400, &ioregs_bonelt,
 493                            &ddr3_beagleblack_data,
 494                            &ddr3_beagleblack_cmd_ctrl_data,
 495                            &ddr3_beagleblack_emif_reg_data, 0);
 496         else if (board_is_evm_15_or_later(&header))
 497                 config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 498                            &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 499         else
 500                 config_ddr(266, &ioregs, &ddr2_data,
 501                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 502 }
 503 #endif
 504
 505 /*
 506  * Basic board specific setup.  Pinmux has been handled already.
 507  */
 508 int board_init(void)
 509 {
 510 #if defined(CONFIG_HW_WATCHDOG)
 511         hw_watchdog_init();
 512 #endif
 513
 514         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 515 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 516         gpmc_init();
 517 #endif
 518         return 0;
 519 }
 520
 521 #ifdef CONFIG_BOARD_LATE_INIT
 522 int board_late_init(void)
 523 {
 524 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 525         char safe_string[HDR_NAME_LEN + 1];
 526         struct am335x_baseboard_id header;
 527
 528         if (read_eeprom(&header) < 0)
 529                 puts("Could not get board ID.\n");
 530
 531         /* Now set variables based on the header. */
 532         strncpy(safe_string, (char *)header.name, sizeof(header.name));
 533         safe_string[sizeof(header.name)] = 0;
 534         setenv("board_name", safe_string);
 535
 536         strncpy(safe_string, (char *)header.version, sizeof(header.version));
 537         safe_string[sizeof(header.version)] = 0;
 538         setenv("board_rev", safe_string);
 539 #endif
 540
 541         return 0;
 542 }
 543 #endif
 544
 545 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 546         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 547 static void cpsw_control(int enabled)
 548 {
 549         /* VTP can be added here */
 550
 551         return;
 552 }
 553
 554 static struct cpsw_slave_data cpsw_slaves[] = {
 555         {
 556                 .slave_reg_ofs  = 0x208,
 557                 .sliver_reg_ofs = 0xd80,
 558                 .phy_addr       = 0,
 559         },
 560         {
 561                 .slave_reg_ofs  = 0x308,
 562                 .sliver_reg_ofs = 0xdc0,
 563                 .phy_addr       = 1,
 564         },
 565 };
 566
 567 static struct cpsw_platform_data cpsw_data = {
 568         .mdio_base              = CPSW_MDIO_BASE,
 569         .cpsw_base              = CPSW_BASE,
 570         .mdio_div               = 0xff,
 571         .channels               = 8,
 572         .cpdma_reg_ofs          = 0x800,
 573         .slaves                 = 1,
 574         .slave_data             = cpsw_slaves,
 575         .ale_reg_ofs            = 0xd00,
 576         .ale_entries            = 1024,
 577         .host_port_reg_ofs      = 0x108,
 578         .hw_stats_reg_ofs       = 0x900,
 579         .bd_ram_ofs             = 0x2000,
 580         .mac_control            = (1 << 5),
 581         .control                = cpsw_control,
 582         .host_port_num          = 0,
 583         .version                = CPSW_CTRL_VERSION_2,
 584 };
 585 #endif
 586
 587 /*
 588  * This function will:
 589  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
 590  * in the environment
 591  * Perform fixups to the PHY present on certain boards.  We only need this
 592  * function in:
 593  * - SPL with either CPSW or USB ethernet support
 594  * - Full U-Boot, with either CPSW or USB ethernet
 595  * Build in only these cases to avoid warnings about unused variables
 596  * when we build an SPL that has neither option but full U-Boot will.
 597  */
 598 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
 599                 && defined(CONFIG_SPL_BUILD)) || \
 600         ((defined(CONFIG_DRIVER_TI_CPSW) || \
 601           defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 602          !defined(CONFIG_SPL_BUILD))
 603 int board_eth_init(bd_t *bis)
 604 {
 605         int rv, n = 0;
 606         uint8_t mac_addr[6];
 607         uint32_t mac_hi, mac_lo;
 608         __maybe_unused struct am335x_baseboard_id header;
 609
 610         /* try reading mac address from efuse */
 611         mac_lo = readl(&cdev->macid0l);
 612         mac_hi = readl(&cdev->macid0h);
 613         mac_addr[0] = mac_hi & 0xFF;
 614         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 615         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 616         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 617         mac_addr[4] = mac_lo & 0xFF;
 618         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 619
 620 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 621         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 622         if (!getenv("ethaddr")) {
 623                 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 624
 625                 if (is_valid_ether_addr(mac_addr))
 626                         eth_setenv_enetaddr("ethaddr", mac_addr);
 627         }
 628
 629 #ifdef CONFIG_DRIVER_TI_CPSW
 630
 631         mac_lo = readl(&cdev->macid1l);
 632         mac_hi = readl(&cdev->macid1h);
 633         mac_addr[0] = mac_hi & 0xFF;
 634         mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 635         mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 636         mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 637         mac_addr[4] = mac_lo & 0xFF;
 638         mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 639
 640         if (!getenv("eth1addr")) {
 641                 if (is_valid_ether_addr(mac_addr))
 642                         eth_setenv_enetaddr("eth1addr", mac_addr);
 643         }
 644
 645         if (read_eeprom(&header) < 0)
 646                 puts("Could not get board ID.\n");
 647
 648         if (board_is_bone(&header) || board_is_bone_lt(&header) ||
 649             board_is_idk(&header)) {
 650                 writel(MII_MODE_ENABLE, &cdev->miisel);
 651                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 652                                 PHY_INTERFACE_MODE_MII;
 653         } else {
 654                 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 655                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 656                                 PHY_INTERFACE_MODE_RGMII;
 657         }
 658
 659         rv = cpsw_register(&cpsw_data);
 660         if (rv < 0)
 661                 printf("Error %d registering CPSW switch\n", rv);
 662         else
 663                 n += rv;
 664 #endif
 665
 666         /*
 667          *
 668          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 669          * operating points.  So we must set the TX clock delay feature
 670          * in the AR8051 PHY.  Since we only support a single ethernet
 671          * device in U-Boot, we only do this for the first instance.
 672          */
 673 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 674 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 675 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 676 #define AR8051_RGMII_TX_CLK_DLY         0x100
 677
 678         if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
 679                 const char *devname;
 680                 devname = miiphy_get_current_dev();
 681
 682                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 683                                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
 684                 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 685                                 AR8051_RGMII_TX_CLK_DLY);
 686         }
 687 #endif
 688 #if defined(CONFIG_USB_ETHER) && \
 689         (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 690         if (is_valid_ether_addr(mac_addr))
 691                 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 692
 693         rv = usb_eth_initialize(bis);
 694         if (rv < 0)
 695                 printf("Error %d registering USB_ETHER\n", rv);
 696         else
 697                 n += rv;
 698 #endif
 699         return n;
 700 }
 701 #endif