board/ti/am335x/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for TI AM335X based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <errno.h>
  21 #include <spl.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/arch/hardware.h>
  24 #include <asm/arch/omap.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/mmc_host_def.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/io.h>
  31 #include <asm/emif.h>
  32 #include <asm/gpio.h>
  33 #include <i2c.h>
  34 #include <miiphy.h>
  35 #include <cpsw.h>
  36 #include "board.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  41 #ifdef CONFIG_SPL_BUILD
  42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  43 #endif
  44
  45 /* MII mode defines */
  46 #define MII_MODE_ENABLE         0x0
  47 #define RGMII_MODE_ENABLE       0xA
  48
  49 /* GPIO that controls power to DDR on EVM-SK */
  50 #define GPIO_DDR_VTT_EN         7
  51
  52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  53
  54 static struct am335x_baseboard_id __attribute__((section (".data"))) header;
  55
  56 static inline int board_is_bone(void)
  57 {
  58         return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
  59 }
  60
  61 static inline int board_is_bone_lt(void)
  62 {
  63         return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
  64 }
  65
  66 static inline int board_is_evm_sk(void)
  67 {
  68         return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
  69 }
  70
  71 /*
  72  * Read header information from EEPROM into global structure.
  73  */
  74 static int read_eeprom(void)
  75 {
  76         /* Check if baseboard eeprom is available */
  77         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  78                 puts("Could not probe the EEPROM; something fundamentally "
  79                         "wrong on the I2C bus.\n");
  80                 return -ENODEV;
  81         }
  82
  83         /* read the eeprom using i2c */
  84         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  85                                                         sizeof(header))) {
  86                 puts("Could not read the EEPROM; something fundamentally"
  87                         " wrong on the I2C bus.\n");
  88                 return -EIO;
  89         }
  90
  91         if (header.magic != 0xEE3355AA) {
  92                 /*
  93                  * read the eeprom using i2c again,
  94                  * but use only a 1 byte address
  95                  */
  96                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
  97                                         (uchar *)&header, sizeof(header))) {
  98                         puts("Could not read the EEPROM; something "
  99                                 "fundamentally wrong on the I2C bus.\n");
 100                         return -EIO;
 101                 }
 102
 103                 if (header.magic != 0xEE3355AA) {
 104                         printf("Incorrect magic number (0x%x) in EEPROM\n",
 105                                         header.magic);
 106                         return -EINVAL;
 107                 }
 108         }
 109
 110         return 0;
 111 }
 112
 113 /* UART Defines */
 114 #ifdef CONFIG_SPL_BUILD
 115 #define UART_RESET              (0x1 << 1)
 116 #define UART_CLK_RUNNING_MASK   0x1
 117 #define UART_SMART_IDLE_EN      (0x1 << 0x3)
 118
 119 static void rtc32k_enable(void)
 120 {
 121         struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
 122
 123         /*
 124          * Unlock the RTC's registers.  For more details please see the
 125          * RTC_SS section of the TRM.  In order to unlock we need to
 126          * write these specific values (keys) in this order.
 127          */
 128         writel(0x83e70b13, &rtc->kick0r);
 129         writel(0x95a4f1e0, &rtc->kick1r);
 130
 131         /* Enable the RTC 32K OSC by setting bits 3 and 6. */
 132         writel((1 << 3) | (1 << 6), &rtc->osc);
 133 }
 134
 135 static const struct ddr_data ddr2_data = {
 136         .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
 137                                 |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
 138         .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
 139                                 |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
 140         .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
 141                                 |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
 142         .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
 143                                 |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
 144         .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
 145                                 |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
 146         .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
 147                                 |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
 148         .datauserank0delay = DDR2_PHY_RANK0_DELAY,
 149         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 150 };
 151
 152 static const struct cmd_control ddr2_cmd_ctrl_data = {
 153         .cmd0csratio = DDR2_RATIO,
 154         .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
 155         .cmd0iclkout = DDR2_INVERT_CLKOUT,
 156
 157         .cmd1csratio = DDR2_RATIO,
 158         .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
 159         .cmd1iclkout = DDR2_INVERT_CLKOUT,
 160
 161         .cmd2csratio = DDR2_RATIO,
 162         .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
 163         .cmd2iclkout = DDR2_INVERT_CLKOUT,
 164 };
 165
 166 static const struct emif_regs ddr2_emif_reg_data = {
 167         .sdram_config = DDR2_EMIF_SDCFG,
 168         .ref_ctrl = DDR2_EMIF_SDREF,
 169         .sdram_tim1 = DDR2_EMIF_TIM1,
 170         .sdram_tim2 = DDR2_EMIF_TIM2,
 171         .sdram_tim3 = DDR2_EMIF_TIM3,
 172         .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
 173 };
 174
 175 static const struct ddr_data ddr3_data = {
 176         .datardsratio0 = DDR3_RD_DQS,
 177         .datawdsratio0 = DDR3_WR_DQS,
 178         .datafwsratio0 = DDR3_PHY_FIFO_WE,
 179         .datawrsratio0 = DDR3_PHY_WR_DATA,
 180         .datadldiff0 = PHY_DLL_LOCK_DIFF,
 181 };
 182
 183 static const struct cmd_control ddr3_cmd_ctrl_data = {
 184         .cmd0csratio = DDR3_RATIO,
 185         .cmd0dldiff = DDR3_DLL_LOCK_DIFF,
 186         .cmd0iclkout = DDR3_INVERT_CLKOUT,
 187
 188         .cmd1csratio = DDR3_RATIO,
 189         .cmd1dldiff = DDR3_DLL_LOCK_DIFF,
 190         .cmd1iclkout = DDR3_INVERT_CLKOUT,
 191
 192         .cmd2csratio = DDR3_RATIO,
 193         .cmd2dldiff = DDR3_DLL_LOCK_DIFF,
 194         .cmd2iclkout = DDR3_INVERT_CLKOUT,
 195 };
 196
 197 static struct emif_regs ddr3_emif_reg_data = {
 198         .sdram_config = DDR3_EMIF_SDCFG,
 199         .ref_ctrl = DDR3_EMIF_SDREF,
 200         .sdram_tim1 = DDR3_EMIF_TIM1,
 201         .sdram_tim2 = DDR3_EMIF_TIM2,
 202         .sdram_tim3 = DDR3_EMIF_TIM3,
 203         .zq_config = DDR3_ZQ_CFG,
 204         .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
 205 };
 206 #endif
 207
 208 /*
 209  * early system init of muxing and clocks.
 210  */
 211 void s_init(void)
 212 {
 213         /* WDT1 is already running when the bootloader gets control
 214          * Disable it to avoid "random" resets
 215          */
 216         writel(0xAAAA, &wdtimer->wdtwspr);
 217         while (readl(&wdtimer->wdtwwps) != 0x0)
 218                 ;
 219         writel(0x5555, &wdtimer->wdtwspr);
 220         while (readl(&wdtimer->wdtwwps) != 0x0)
 221                 ;
 222
 223 #ifdef CONFIG_SPL_BUILD
 224         /* Setup the PLLs and the clocks for the peripherals */
 225         pll_init();
 226
 227         /* Enable RTC32K clock */
 228         rtc32k_enable();
 229
 230         /* UART softreset */
 231         u32 regVal;
 232
 233         enable_uart0_pin_mux();
 234
 235         regVal = readl(&uart_base->uartsyscfg);
 236         regVal |= UART_RESET;
 237         writel(regVal, &uart_base->uartsyscfg);
 238         while ((readl(&uart_base->uartsyssts) &
 239                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 240                 ;
 241
 242         /* Disable smart idle */
 243         regVal = readl(&uart_base->uartsyscfg);
 244         regVal |= UART_SMART_IDLE_EN;
 245         writel(regVal, &uart_base->uartsyscfg);
 246
 247         gd = &gdata;
 248
 249         preloader_console_init();
 250
 251         /* Initalize the board header */
 252         enable_i2c0_pin_mux();
 253         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 254         if (read_eeprom() < 0)
 255                 puts("Could not get board ID.\n");
 256
 257         enable_board_pin_mux(&header);
 258         if (board_is_evm_sk()) {
 259                 /*
 260                  * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 261                  * This is safe enough to do on older revs.
 262                  */
 263                 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 264                 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 265         }
 266
 267         if (board_is_evm_sk() || board_is_bone_lt())
 268                 config_ddr(303, DDR3_IOCTRL_VALUE, &ddr3_data,
 269                            &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
 270         else
 271                 config_ddr(266, DDR2_IOCTRL_VALUE, &ddr2_data,
 272                            &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
 273 #endif
 274 }
 275
 276 /*
 277  * Basic board specific setup.  Pinmux has been handled already.
 278  */
 279 int board_init(void)
 280 {
 281         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 282         if (read_eeprom() < 0)
 283                 puts("Could not get board ID.\n");
 284
 285         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 286
 287         return 0;
 288 }
 289
 290 #ifdef CONFIG_DRIVER_TI_CPSW
 291 static void cpsw_control(int enabled)
 292 {
 293         /* VTP can be added here */
 294
 295         return;
 296 }
 297
 298 static struct cpsw_slave_data cpsw_slaves[] = {
 299         {
 300                 .slave_reg_ofs  = 0x208,
 301                 .sliver_reg_ofs = 0xd80,
 302                 .phy_id         = 0,
 303         },
 304         {
 305                 .slave_reg_ofs  = 0x308,
 306                 .sliver_reg_ofs = 0xdc0,
 307                 .phy_id         = 1,
 308         },
 309 };
 310
 311 static struct cpsw_platform_data cpsw_data = {
 312         .mdio_base              = AM335X_CPSW_MDIO_BASE,
 313         .cpsw_base              = AM335X_CPSW_BASE,
 314         .mdio_div               = 0xff,
 315         .channels               = 8,
 316         .cpdma_reg_ofs          = 0x800,
 317         .slaves                 = 1,
 318         .slave_data             = cpsw_slaves,
 319         .ale_reg_ofs            = 0xd00,
 320         .ale_entries            = 1024,
 321         .host_port_reg_ofs      = 0x108,
 322         .hw_stats_reg_ofs       = 0x900,
 323         .mac_control            = (1 << 5),
 324         .control                = cpsw_control,
 325         .host_port_num          = 0,
 326         .version                = CPSW_CTRL_VERSION_2,
 327 };
 328
 329 int board_eth_init(bd_t *bis)
 330 {
 331         uint8_t mac_addr[6];
 332         uint32_t mac_hi, mac_lo;
 333
 334         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 335                 debug("<ethaddr> not set. Reading from E-fuse\n");
 336                 /* try reading mac address from efuse */
 337                 mac_lo = readl(&cdev->macid0l);
 338                 mac_hi = readl(&cdev->macid0h);
 339                 mac_addr[0] = mac_hi & 0xFF;
 340                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 341                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 342                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 343                 mac_addr[4] = mac_lo & 0xFF;
 344                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 345
 346                 if (is_valid_ether_addr(mac_addr))
 347                         eth_setenv_enetaddr("ethaddr", mac_addr);
 348                 else
 349                         return -1;
 350         }
 351
 352         if (board_is_bone() || board_is_bone_lt()) {
 353                 writel(MII_MODE_ENABLE, &cdev->miisel);
 354                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 355                                 PHY_INTERFACE_MODE_MII;
 356         } else {
 357                 writel(RGMII_MODE_ENABLE, &cdev->miisel);
 358                 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 359                                 PHY_INTERFACE_MODE_RGMII;
 360         }
 361
 362         return cpsw_register(&cpsw_data);
 363 }
 364 #endif