board/ti/ks2_evm/ddr3_cfg.c

   1 /*
   2  * Keystone2: DDR3 configuration
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <i2c.h>
  13 #include <asm/arch/ddr3.h>
  14 #include <asm/arch/hardware.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 /* DDR3 PHY configuration data with 1600M rate, 8GB size */
  19 struct ddr3_phy_config ddr3phy_1600_8g = {
  20         .pllcr          = 0x0001C000ul,
  21         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
  22         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
  23         .ptr0           = 0x42C21590ul,
  24         .ptr1           = 0xD05612C0ul,
  25         .ptr2           = 0, /* not set in gel */
  26         .ptr3           = 0x0D861A80ul,
  27         .ptr4           = 0x0C827100ul,
  28         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
  29         .dcr_val        = ((1 << 10)),
  30         .dtpr0          = 0xA19DBB66ul,
  31         .dtpr1          = 0x32868300ul,
  32         .dtpr2          = 0x50035200ul,
  33         .mr0            = 0x00001C70ul,
  34         .mr1            = 0x00000006ul,
  35         .mr2            = 0x00000018ul,
  36         .dtcr           = 0x730035C7ul,
  37         .pgcr2          = 0x00F07A12ul,
  38         .zq0cr1         = 0x0000005Dul,
  39         .zq1cr1         = 0x0000005Bul,
  40         .zq2cr1         = 0x0000005Bul,
  41         .pir_v1         = 0x00000033ul,
  42         .pir_v2         = 0x0000FF81ul,
  43 };
  44
  45 /* DDR3 EMIF configuration data with 1600M rate, 8GB size */
  46 struct ddr3_emif_config ddr3_1600_8g = {
  47         .sdcfg          = 0x6200CE6Aul,
  48         .sdtim1         = 0x16709C55ul,
  49         .sdtim2         = 0x00001D4Aul,
  50         .sdtim3         = 0x435DFF54ul,
  51         .sdtim4         = 0x553F0CFFul,
  52         .zqcfg          = 0xF0073200ul,
  53         .sdrfc          = 0x00001869ul,
  54 };
  55
  56 #ifdef CONFIG_K2HK_EVM
  57 /* DDR3 PHY configuration data with 1333M rate, and 2GB size */
  58 struct ddr3_phy_config ddr3phy_1333_2g = {
  59         .pllcr          = 0x0005C000ul,
  60         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
  61         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
  62         .ptr0           = 0x42C21590ul,
  63         .ptr1           = 0xD05612C0ul,
  64         .ptr2           = 0, /* not set in gel */
  65         .ptr3           = 0x0B4515C2ul,
  66         .ptr4           = 0x0A6E08B4ul,
  67         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
  68         .dcr_val        = ((1 << 10)),
  69         .dtpr0          = 0x8558AA55ul,
  70         .dtpr1          = 0x32857280ul,
  71         .dtpr2          = 0x5002C200ul,
  72         .mr0            = 0x00001A60ul,
  73         .mr1            = 0x00000006ul,
  74         .mr2            = 0x00000010ul,
  75         .dtcr           = 0x710035C7ul,
  76         .pgcr2          = 0x00F065B8ul,
  77         .zq0cr1         = 0x0000005Dul,
  78         .zq1cr1         = 0x0000005Bul,
  79         .zq2cr1         = 0x0000005Bul,
  80         .pir_v1         = 0x00000033ul,
  81         .pir_v2         = 0x0000FF81ul,
  82 };
  83
  84 /* DDR3 EMIF configuration data with 1333M rate, and 2GB size */
  85 struct ddr3_emif_config ddr3_1333_2g = {
  86         .sdcfg          = 0x62008C62ul,
  87         .sdtim1         = 0x125C8044ul,
  88         .sdtim2         = 0x00001D29ul,
  89         .sdtim3         = 0x32CDFF43ul,
  90         .sdtim4         = 0x543F0ADFul,
  91         .zqcfg          = 0x70073200ul,
  92         .sdrfc          = 0x00001457ul,
  93 };
  94 #endif
  95
  96 #ifdef CONFIG_K2E_EVM
  97 /* DDR3 PHY configuration data with 1600M rate, and 4GB size  */
  98 struct ddr3_phy_config ddr3phy_1600_4g = {
  99         .pllcr          = 0x0001C000ul,
 100         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
 101         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
 102         .ptr0           = 0x42C21590ul,
 103         .ptr1           = 0xD05612C0ul,
 104         .ptr2           = 0, /* not set in gel */
 105         .ptr3           = 0x08861A80ul,
 106         .ptr4           = 0x0C827100ul,
 107         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
 108         .dcr_val        = ((1 << 10)),
 109         .dtpr0          = 0x9D9CBB66ul,
 110         .dtpr1          = 0x12840300ul,
 111         .dtpr2          = 0x5002D200ul,
 112         .mr0            = 0x00001C70ul,
 113         .mr1            = 0x00000006ul,
 114         .mr2            = 0x00000018ul,
 115         .dtcr           = 0x710035C7ul,
 116         .pgcr2          = 0x00F07A12ul,
 117         .zq0cr1         = 0x0001005Dul,
 118         .zq1cr1         = 0x0001005Bul,
 119         .zq2cr1         = 0x0001005Bul,
 120         .pir_v1         = 0x00000033ul,
 121         .pir_v2         = 0x0000FF81ul,
 122 };
 123
 124 /* DDR3 EMIF configuration data with 1600M rate, and 4GB size  */
 125 struct ddr3_emif_config ddr3_1600_4g = {
 126         .sdcfg          = 0x6200CE62ul,
 127         .sdtim1         = 0x166C9855ul,
 128         .sdtim2         = 0x00001D4Aul,
 129         .sdtim3         = 0x421DFF53ul,
 130         .sdtim4         = 0x543F07FFul,
 131         .zqcfg          = 0x70073200ul,
 132         .sdrfc          = 0x00001869ul,
 133 };
 134 #endif
 135
 136 struct ddr3_phy_config ddr3phy_1600_2g = {
 137         .pllcr          = 0x0001C000ul,
 138         .pgcr1_mask     = (IODDRM_MASK | ZCKSEL_MASK),
 139         .pgcr1_val      = ((1 << 2) | (1 << 7) | (1 << 23)),
 140         .ptr0           = 0x42C21590ul,
 141         .ptr1           = 0xD05612C0ul,
 142         .ptr2           = 0, /* not set in gel */
 143         .ptr3           = 0x0D861A80ul,
 144         .ptr4           = 0x0C827100ul,
 145         .dcr_mask       = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
 146         .dcr_val        = ((1 << 10)),
 147         .dtpr0          = 0x9D5CBB66ul,
 148         .dtpr1          = 0x12868300ul,
 149         .dtpr2          = 0x5002D200ul,
 150         .mr0            = 0x00001C70ul,
 151         .mr1            = 0x00000006ul,
 152         .mr2            = 0x00000018ul,
 153         .dtcr           = 0x710035C7ul,
 154         .pgcr2          = 0x00F07A12ul,
 155         .zq0cr1         = 0x0001005Dul,
 156         .zq1cr1         = 0x0001005Bul,
 157         .zq2cr1         = 0x0001005Bul,
 158         .pir_v1         = 0x00000033ul,
 159         .pir_v2         = 0x0000FF81ul,
 160 };
 161
 162 struct ddr3_emif_config ddr3_1600_2g = {
 163         .sdcfg          = 0x6200CE62ul,
 164         .sdtim1         = 0x166C9855ul,
 165         .sdtim2         = 0x00001D4Aul,
 166         .sdtim3         = 0x435DFF53ul,
 167         .sdtim4         = 0x543F0CFFul,
 168         .zqcfg          = 0x70073200ul,
 169         .sdrfc          = 0x00001869ul,
 170 };
 171
 172 int ddr3_get_dimm_params(char *dimm_name)
 173 {
 174         int ret;
 175         int old_bus;
 176         u8 spd_params[256];
 177
 178         i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
 179
 180         old_bus = i2c_get_bus_num();
 181         i2c_set_bus_num(1);
 182
 183         ret = i2c_read(0x53, 0, 1, spd_params, 256);
 184
 185         i2c_set_bus_num(old_bus);
 186
 187         dimm_name[0] = '\0';
 188
 189         if (ret) {
 190                 puts("Cannot read DIMM params\n");
 191                 return 1;
 192         }
 193
 194         /*
 195          * We need to convert spd data to dimm parameters
 196          * and to DDR3 EMIF and PHY regirsters values.
 197          * For now we just return DIMM type string value.
 198          * Caller may use this value to choose appropriate
 199          * a pre-set DDR3 configuration
 200          */
 201
 202         strncpy(dimm_name, (char *)&spd_params[0x80], 18);
 203         dimm_name[18] = '\0';
 204
 205         return 0;
 206 }