board/ti/ks2_evm/ddr3_k2hk.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include "ddr3_cfg.h"
  12 #include <asm/arch/ddr3.h>
  13 #include <asm/arch/hardware.h>
  14
  15 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
  16 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
  17
  18 void ddr3_init(void)
  19 {
  20         char dimm_name[32];
  21
  22         ddr3_get_dimm_params(dimm_name);
  23
  24         printf("Detected SO-DIMM [%s]\n", dimm_name);
  25
  26         if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
  27                 init_pll(&ddr3a_400);
  28                 if (cpu_revision() > 0) {
  29                         if (cpu_revision() > 1) {
  30                                 /* PG 2.0 */
  31                                 /* Reset DDR3A PHY after PLL enabled */
  32                                 ddr3_reset_ddrphy();
  33                                 ddr3phy_1600_8g.zq0cr1 |= 0x10000;
  34                                 ddr3phy_1600_8g.zq1cr1 |= 0x10000;
  35                                 ddr3phy_1600_8g.zq2cr1 |= 0x10000;
  36                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  37                                                  &ddr3phy_1600_8g);
  38                         } else {
  39                                 /* PG 1.1 */
  40                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  41                                                  &ddr3phy_1600_8g);
  42                         }
  43
  44                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  45                                           &ddr3_1600_8g);
  46                         printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
  47                 } else {
  48                         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
  49                         ddr3_1600_8g.sdcfg |= 0x1000;
  50                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  51                                           &ddr3_1600_8g);
  52                         printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
  53                 }
  54         } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
  55                 init_pll(&ddr3a_333);
  56                 if (cpu_revision() > 0) {
  57                         if (cpu_revision() > 1) {
  58                                 /* PG 2.0 */
  59                                 /* Reset DDR3A PHY after PLL enabled */
  60                                 ddr3_reset_ddrphy();
  61                                 ddr3phy_1333_2g.zq0cr1 |= 0x10000;
  62                                 ddr3phy_1333_2g.zq1cr1 |= 0x10000;
  63                                 ddr3phy_1333_2g.zq2cr1 |= 0x10000;
  64                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  65                                                  &ddr3phy_1333_2g);
  66                         } else {
  67                                 /* PG 1.1 */
  68                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  69                                                  &ddr3phy_1333_2g);
  70                         }
  71                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  72                                           &ddr3_1333_2g);
  73                 } else {
  74                         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
  75                         ddr3_1333_2g.sdcfg |= 0x1000;
  76                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  77                                           &ddr3_1333_2g);
  78                 }
  79         } else {
  80                 printf("Unknown SO-DIMM. Cannot configure DDR3\n");
  81                 while (1)
  82                         ;
  83         }
  84
  85         /* Apply the workaround for PG 1.0 and 1.1 Silicons */
  86         if (cpu_revision() <= 1)
  87                 ddr3_err_reset_workaround();
  88 }