board/ti/ks2_evm/ddr3_k2hk.c

   1 /*
   2  * Keystone2: DDR3 initialization
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include "ddr3_cfg.h"
  12 #include <asm/arch/ddr3.h>
  13 #include <asm/arch/hardware.h>
  14
  15 static int ddr3_size;
  16
  17 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
  18 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
  19
  20 void ddr3_init(void)
  21 {
  22         char dimm_name[32];
  23
  24         ddr3_get_dimm_params(dimm_name);
  25
  26         printf("Detected SO-DIMM [%s]\n", dimm_name);
  27
  28         if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
  29                 init_pll(&ddr3a_400);
  30                 if (cpu_revision() > 0) {
  31                         if (cpu_revision() > 1) {
  32                                 /* PG 2.0 */
  33                                 /* Reset DDR3A PHY after PLL enabled */
  34                                 ddr3_reset_ddrphy();
  35                                 ddr3phy_1600_8g.zq0cr1 |= 0x10000;
  36                                 ddr3phy_1600_8g.zq1cr1 |= 0x10000;
  37                                 ddr3phy_1600_8g.zq2cr1 |= 0x10000;
  38                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  39                                                  &ddr3phy_1600_8g);
  40                         } else {
  41                                 /* PG 1.1 */
  42                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  43                                                  &ddr3phy_1600_8g);
  44                         }
  45
  46                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  47                                           &ddr3_1600_8g);
  48                         printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
  49                         ddr3_size = 8;
  50                 } else {
  51                         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
  52                         ddr3_1600_8g.sdcfg |= 0x1000;
  53                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  54                                           &ddr3_1600_8g);
  55                         printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
  56                         ddr3_size = 4;
  57                 }
  58         } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
  59                 init_pll(&ddr3a_333);
  60                 if (cpu_revision() > 0) {
  61                         if (cpu_revision() > 1) {
  62                                 /* PG 2.0 */
  63                                 /* Reset DDR3A PHY after PLL enabled */
  64                                 ddr3_reset_ddrphy();
  65                                 ddr3phy_1333_2g.zq0cr1 |= 0x10000;
  66                                 ddr3phy_1333_2g.zq1cr1 |= 0x10000;
  67                                 ddr3phy_1333_2g.zq2cr1 |= 0x10000;
  68                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  69                                                  &ddr3phy_1333_2g);
  70                         } else {
  71                                 /* PG 1.1 */
  72                                 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
  73                                                  &ddr3phy_1333_2g);
  74                         }
  75                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  76                                           &ddr3_1333_2g);
  77                         ddr3_size = 2;
  78                         printf("DRAM:  2 GiB");
  79                 } else {
  80                         ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
  81                         ddr3_1333_2g.sdcfg |= 0x1000;
  82                         ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
  83                                           &ddr3_1333_2g);
  84                         ddr3_size = 1;
  85                         printf("DRAM:  1 GiB");
  86                 }
  87         } else {
  88                 printf("Unknown SO-DIMM. Cannot configure DDR3\n");
  89                 while (1)
  90                         ;
  91         }
  92
  93         /* Apply the workaround for PG 1.0 and 1.1 Silicons */
  94         if (cpu_revision() <= 1)
  95                 ddr3_err_reset_workaround();
  96 }
  97
  98 /**
  99  * ddr3_get_size - return ddr3 size in GiB
 100  */
 101 int ddr3_get_size(void)
 102 {
 103         return ddr3_size;
 104 }