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[karo-tx-uboot.git] / board / ti / omap5_uevm / evm.c
1 /*
2  * (C) Copyright 2010
3  * Texas Instruments Incorporated, <www.ti.com>
4  * Aneesh V       <aneesh@ti.com>
5  * Steve Sakoman  <steve@sakoman.com>
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9 #include <common.h>
10 #include <palmas.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch/mmc_host_def.h>
13 #include <tca642x.h>
14
15 #include "mux_data.h"
16
17 #ifdef CONFIG_USB_EHCI
18 #include <usb.h>
19 #include <asm/gpio.h>
20 #include <asm/arch/clock.h>
21 #include <asm/arch/ehci.h>
22 #include <asm/ehci-omap.h>
23
24 #define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
25 #define DIE_ID_REG_OFFSET       0x200
26
27 #endif
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 const struct omap_sysinfo sysinfo = {
32         "Board: OMAP5432 uEVM\n"
33 };
34
35 /**
36  * @brief tca642x_init - uEVM default values for the GPIO expander
37  * input reg, output reg, polarity reg, configuration reg
38  */
39 struct tca642x_bank_info tca642x_init[] = {
40         { .input_reg = 0x00,
41           .output_reg = 0x04,
42           .polarity_reg = 0x00,
43           .configuration_reg = 0x80 },
44         { .input_reg = 0x00,
45           .output_reg = 0x00,
46           .polarity_reg = 0x00,
47           .configuration_reg = 0xff },
48         { .input_reg = 0x00,
49           .output_reg = 0x00,
50           .polarity_reg = 0x00,
51           .configuration_reg = 0x40 },
52 };
53
54 /**
55  * @brief board_init
56  *
57  * @return 0
58  */
59 int board_init(void)
60 {
61         gpmc_init();
62         gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
63         gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
64
65         tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
66
67         return 0;
68 }
69
70 int board_eth_init(bd_t *bis)
71 {
72         return 0;
73 }
74
75 /**
76  * @brief misc_init_r - Configure EVM board specific configurations
77  * such as power configurations, ethernet initialization as phase2 of
78  * boot sequence
79  *
80  * @return 0
81  */
82 int misc_init_r(void)
83 {
84 #ifdef CONFIG_PALMAS_POWER
85         palmas_init_settings();
86 #endif
87         return 0;
88 }
89
90 void set_muxconf_regs_essential(void)
91 {
92         do_set_mux((*ctrl)->control_padconf_core_base,
93                    core_padconf_array_essential,
94                    sizeof(core_padconf_array_essential) /
95                    sizeof(struct pad_conf_entry));
96
97         do_set_mux((*ctrl)->control_padconf_wkup_base,
98                    wkup_padconf_array_essential,
99                    sizeof(wkup_padconf_array_essential) /
100                    sizeof(struct pad_conf_entry));
101 }
102
103 void set_muxconf_regs_non_essential(void)
104 {
105         do_set_mux((*ctrl)->control_padconf_core_base,
106                    core_padconf_array_non_essential,
107                    sizeof(core_padconf_array_non_essential) /
108                    sizeof(struct pad_conf_entry));
109
110         do_set_mux((*ctrl)->control_padconf_wkup_base,
111                    wkup_padconf_array_non_essential,
112                    sizeof(wkup_padconf_array_non_essential) /
113                    sizeof(struct pad_conf_entry));
114 }
115
116 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
117 int board_mmc_init(bd_t *bis)
118 {
119         omap_mmc_init(0, 0, 0, -1, -1);
120         omap_mmc_init(1, 0, 0, -1, -1);
121         return 0;
122 }
123 #endif
124
125 #ifdef CONFIG_USB_EHCI
126 static struct omap_usbhs_board_data usbhs_bdata = {
127         .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
128         .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
129         .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
130 };
131
132 static void enable_host_clocks(void)
133 {
134         int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK |
135                                 OPTFCLKEN_HSIC480M_P3_CLK |
136                                 OPTFCLKEN_HSIC60M_P2_CLK |
137                                 OPTFCLKEN_HSIC480M_P2_CLK |
138                                 OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK);
139
140         /* Enable port 2 and 3 clocks*/
141         setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val);
142
143         /* Enable port 2 and 3 usb host ports tll clocks*/
144         setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl,
145                         (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE));
146 }
147
148 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
149 {
150         int ret;
151         int auxclk;
152         int reg;
153         uint8_t device_mac[6];
154
155         enable_host_clocks();
156
157         if (!getenv("usbethaddr")) {
158                 reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
159
160                 /*
161                  * create a fake MAC address from the processor ID code.
162                  * first byte is 0x02 to signify locally administered.
163                  */
164                 device_mac[0] = 0x02;
165                 device_mac[1] = readl(reg + 0x10) & 0xff;
166                 device_mac[2] = readl(reg + 0xC) & 0xff;
167                 device_mac[3] = readl(reg + 0x8) & 0xff;
168                 device_mac[4] = readl(reg) & 0xff;
169                 device_mac[5] = (readl(reg) >> 8) & 0xff;
170
171                 eth_setenv_enetaddr("usbethaddr", device_mac);
172         }
173
174         auxclk = readl((*prcm)->scrm_auxclk1);
175         /* Request auxilary clock */
176         auxclk |= AUXCLK_ENABLE_MASK;
177         writel(auxclk, (*prcm)->scrm_auxclk1);
178
179         ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
180         if (ret < 0) {
181                 puts("Failed to initialize ehci\n");
182                 return ret;
183         }
184
185         return 0;
186 }
187
188 int ehci_hcd_stop(void)
189 {
190         int ret;
191
192         ret = omap_ehci_hcd_stop();
193         return ret;
194 }
195
196 void usb_hub_reset_devices(int port)
197 {
198         /* The LAN9730 needs to be reset after the port power has been set. */
199         if (port == 3) {
200                 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
201                 udelay(10);
202                 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
203         }
204 }
205 #endif