4 * Board functions for TI814x EVM
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/omap.h>
26 #include <asm/arch/ddr_defs.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc_host_def.h>
30 #include <asm/arch/sys_proto.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #ifdef CONFIG_SPL_BUILD
39 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
40 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
46 #ifdef CONFIG_SPL_BUILD
47 #define UART_RESET (0x1 << 1)
48 #define UART_CLK_RUNNING_MASK 0x1
49 #define UART_SMART_IDLE_EN (0x1 << 0x3)
51 static void rtc32k_enable(void)
53 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
56 * Unlock the RTC's registers. For more details please see the
57 * RTC_SS section of the TRM. In order to unlock we need to
58 * write these specific values (keys) in this order.
60 writel(0x83e70b13, &rtc->kick0r);
61 writel(0x95a4f1e0, &rtc->kick1r);
63 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
64 writel((1 << 3) | (1 << 6), &rtc->osc);
67 static void uart_enable(void)
72 regVal = readl(&uart_base->uartsyscfg);
74 writel(regVal, &uart_base->uartsyscfg);
75 while ((readl(&uart_base->uartsyssts) &
76 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
79 /* Disable smart idle */
80 regVal = readl(&uart_base->uartsyscfg);
81 regVal |= UART_SMART_IDLE_EN;
82 writel(regVal, &uart_base->uartsyscfg);
85 static void wdt_disable(void)
87 writel(0xAAAA, &wdtimer->wdtwspr);
88 while (readl(&wdtimer->wdtwwps) != 0x0)
90 writel(0x5555, &wdtimer->wdtwspr);
91 while (readl(&wdtimer->wdtwwps) != 0x0)
95 static const struct cmd_control evm_ddr2_cctrl_data = {
109 static const struct emif_regs evm_ddr2_emif0_regs = {
110 .sdram_config = 0x40801ab2,
111 .ref_ctrl = 0x10000c30,
112 .sdram_tim1 = 0x0aaaf552,
113 .sdram_tim2 = 0x043631d2,
114 .sdram_tim3 = 0x00000327,
115 .emif_ddr_phy_ctlr_1 = 0x00000007
118 static const struct emif_regs evm_ddr2_emif1_regs = {
119 .sdram_config = 0x40801ab2,
120 .ref_ctrl = 0x10000c30,
121 .sdram_tim1 = 0x0aaaf552,
122 .sdram_tim2 = 0x043631d2,
123 .sdram_tim3 = 0x00000327,
124 .emif_ddr_phy_ctlr_1 = 0x00000007
127 const struct dmm_lisa_map_regs evm_lisa_map_regs = {
128 .dmm_lisa_map_0 = 0x00000000,
129 .dmm_lisa_map_1 = 0x00000000,
130 .dmm_lisa_map_2 = 0x806c0300,
131 .dmm_lisa_map_3 = 0x806c0300,
134 static const struct ddr_data evm_ddr2_data = {
135 .datardsratio0 = ((0x35<<10) | (0x35<<0)),
136 .datawdsratio0 = ((0x20<<10) | (0x20<<0)),
137 .datawiratio0 = ((0<<10) | (0<<0)),
138 .datagiratio0 = ((0<<10) | (0<<0)),
139 .datafwsratio0 = ((0x90<<10) | (0x90<<0)),
140 .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
141 .datauserank0delay = 1,
147 * early system init of muxing and clocks.
151 #ifdef CONFIG_SPL_BUILD
152 /* WDT1 is already running when the bootloader gets control
153 * Disable it to avoid "random" resets
160 /* Setup the PLLs and the clocks for the peripherals */
163 /* Enable RTC32K clock */
167 enable_uart0_pin_mux();
170 enable_mmc1_pin_mux();
172 /* Set Ethernet pins */
173 enable_enet_pin_mux();
180 preloader_console_init();
182 config_dmm(&evm_lisa_map_regs);
184 config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
185 &evm_ddr2_emif0_regs, 0);
186 config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
187 &evm_ddr2_emif1_regs, 1);
192 * Basic board specific setup. Pinmux has been handled already.
196 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
200 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
201 int board_mmc_init(bd_t *bis)
203 omap_mmc_init(1, 0, 0, -1, -1);
209 #ifdef CONFIG_DRIVER_TI_CPSW
210 static void cpsw_control(int enabled)
212 /* VTP can be added here */
217 static struct cpsw_slave_data cpsw_slaves[] = {
219 .slave_reg_ofs = 0x50,
220 .sliver_reg_ofs = 0x700,
224 .slave_reg_ofs = 0x90,
225 .sliver_reg_ofs = 0x740,
230 static struct cpsw_platform_data cpsw_data = {
231 .mdio_base = CPSW_MDIO_BASE,
232 .cpsw_base = CPSW_BASE,
235 .cpdma_reg_ofs = 0x100,
237 .slave_data = cpsw_slaves,
238 .ale_reg_ofs = 0x600,
240 .host_port_reg_ofs = 0x28,
241 .hw_stats_reg_ofs = 0x400,
242 .mac_control = (1 << 5),
243 .control = cpsw_control,
245 .version = CPSW_CTRL_VERSION_1,
249 int board_eth_init(bd_t *bis)
252 uint32_t mac_hi, mac_lo;
254 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
255 printf("<ethaddr> not set. Reading from E-fuse\n");
256 /* try reading mac address from efuse */
257 mac_lo = readl(&cdev->macid0l);
258 mac_hi = readl(&cdev->macid0h);
259 mac_addr[0] = mac_hi & 0xFF;
260 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
261 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
262 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
263 mac_addr[4] = mac_lo & 0xFF;
264 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
266 if (is_valid_ether_addr(mac_addr))
267 eth_setenv_enetaddr("ethaddr", mac_addr);
269 printf("Unable to read MAC address. Set <ethaddr>\n");
272 return cpsw_register(&cpsw_data);