drivers/ddr/fsl/lc_common_dimm_params.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <fsl_ddr_sdram.h>
  11
  12 #include <fsl_ddr.h>
  13
  14 #if defined(CONFIG_SYS_FSL_DDR3)
  15 static unsigned int
  16 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
  17                          common_timing_params_t *outpdimm,
  18                          unsigned int number_of_dimms)
  19 {
  20         unsigned int i;
  21         unsigned int taamin_ps = 0;
  22         unsigned int tckmin_x_ps = 0;
  23         unsigned int common_caslat;
  24         unsigned int caslat_actual;
  25         unsigned int retry = 16;
  26         unsigned int tmp;
  27         const unsigned int mclk_ps = get_memory_clk_period_ps();
  28
  29         /* compute the common CAS latency supported between slots */
  30         tmp = dimm_params[0].caslat_x;
  31         for (i = 1; i < number_of_dimms; i++) {
  32                 if (dimm_params[i].n_ranks)
  33                         tmp &= dimm_params[i].caslat_x;
  34         }
  35         common_caslat = tmp;
  36
  37         /* compute the max tAAmin tCKmin between slots */
  38         for (i = 0; i < number_of_dimms; i++) {
  39                 taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
  40                 tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
  41         }
  42         /* validate if the memory clk is in the range of dimms */
  43         if (mclk_ps < tckmin_x_ps) {
  44                 printf("DDR clock (MCLK cycle %u ps) is faster than "
  45                         "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
  46                         mclk_ps, tckmin_x_ps);
  47         }
  48         /* determine the acutal cas latency */
  49         caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
  50         /* check if the dimms support the CAS latency */
  51         while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
  52                 caslat_actual++;
  53                 retry--;
  54         }
  55         /* once the caculation of caslat_actual is completed
  56          * we must verify that this CAS latency value does not
  57          * exceed tAAmax, which is 20 ns for all DDR3 speed grades
  58          */
  59         if (caslat_actual * mclk_ps > 20000) {
  60                 printf("The choosen cas latency %d is too large\n",
  61                         caslat_actual);
  62         }
  63         outpdimm->lowest_common_SPD_caslat = caslat_actual;
  64
  65         return 0;
  66 }
  67 #endif
  68
  69 /*
  70  * compute_lowest_common_dimm_parameters()
  71  *
  72  * Determine the worst-case DIMM timing parameters from the set of DIMMs
  73  * whose parameters have been computed into the array pointed to
  74  * by dimm_params.
  75  */
  76 unsigned int
  77 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
  78                                       common_timing_params_t *outpdimm,
  79                                       const unsigned int number_of_dimms)
  80 {
  81         unsigned int i, j;
  82
  83         unsigned int tckmin_x_ps = 0;
  84         unsigned int tckmax_ps = 0xFFFFFFFF;
  85         unsigned int tckmax_max_ps = 0;
  86         unsigned int trcd_ps = 0;
  87         unsigned int trp_ps = 0;
  88         unsigned int tras_ps = 0;
  89         unsigned int twr_ps = 0;
  90         unsigned int twtr_ps = 0;
  91         unsigned int trfc_ps = 0;
  92         unsigned int trrd_ps = 0;
  93         unsigned int trc_ps = 0;
  94         unsigned int refresh_rate_ps = 0;
  95         unsigned int extended_op_srt = 1;
  96         unsigned int tis_ps = 0;
  97         unsigned int tih_ps = 0;
  98         unsigned int tds_ps = 0;
  99         unsigned int tdh_ps = 0;
 100         unsigned int trtp_ps = 0;
 101         unsigned int tdqsq_max_ps = 0;
 102         unsigned int tqhs_ps = 0;
 103
 104         unsigned int temp1, temp2;
 105         unsigned int additive_latency = 0;
 106 #if !defined(CONFIG_SYS_FSL_DDR3)
 107         const unsigned int mclk_ps = get_memory_clk_period_ps();
 108         unsigned int lowest_good_caslat;
 109         unsigned int not_ok;
 110
 111         debug("using mclk_ps = %u\n", mclk_ps);
 112 #endif
 113
 114         temp1 = 0;
 115         for (i = 0; i < number_of_dimms; i++) {
 116                 /*
 117                  * If there are no ranks on this DIMM,
 118                  * it probably doesn't exist, so skip it.
 119                  */
 120                 if (dimm_params[i].n_ranks == 0) {
 121                         temp1++;
 122                         continue;
 123                 }
 124                 if (dimm_params[i].n_ranks == 4 && i != 0) {
 125                         printf("Found Quad-rank DIMM in wrong bank, ignored."
 126                                 " Software may not run as expected.\n");
 127                         temp1++;
 128                         continue;
 129                 }
 130
 131                 /*
 132                  * check if quad-rank DIMM is plugged if
 133                  * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
 134                  * Only the board with proper design is capable
 135                  */
 136 #ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 137                 if (dimm_params[i].n_ranks == 4 && \
 138                   CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
 139                         printf("Found Quad-rank DIMM, not able to support.");
 140                         temp1++;
 141                         continue;
 142                 }
 143 #endif
 144                 /*
 145                  * Find minimum tckmax_ps to find fastest slow speed,
 146                  * i.e., this is the slowest the whole system can go.
 147                  */
 148                 tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
 149
 150                 /* Either find maximum value to determine slowest
 151                  * speed, delay, time, period, etc */
 152                 tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
 153                 tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps);
 154                 trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
 155                 trp_ps = max(trp_ps, dimm_params[i].trp_ps);
 156                 tras_ps = max(tras_ps, dimm_params[i].tras_ps);
 157                 twr_ps = max(twr_ps, dimm_params[i].twr_ps);
 158                 twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
 159                 trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
 160                 trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
 161                 trc_ps = max(trc_ps, dimm_params[i].trc_ps);
 162                 tis_ps = max(tis_ps, dimm_params[i].tis_ps);
 163                 tih_ps = max(tih_ps, dimm_params[i].tih_ps);
 164                 tds_ps = max(tds_ps, dimm_params[i].tds_ps);
 165                 tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
 166                 trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
 167                 tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
 168                 refresh_rate_ps = max(refresh_rate_ps,
 169                                       dimm_params[i].refresh_rate_ps);
 170                 /* extended_op_srt is either 0 or 1, 0 having priority */
 171                 extended_op_srt = min(extended_op_srt,
 172                                       dimm_params[i].extended_op_srt);
 173
 174                 /*
 175                  * Find maximum tdqsq_max_ps to find slowest.
 176                  *
 177                  * FIXME: is finding the slowest value the correct
 178                  * strategy for this parameter?
 179                  */
 180                 tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
 181         }
 182
 183         outpdimm->ndimms_present = number_of_dimms - temp1;
 184
 185         if (temp1 == number_of_dimms) {
 186                 debug("no dimms this memory controller\n");
 187                 return 0;
 188         }
 189
 190         outpdimm->tckmin_x_ps = tckmin_x_ps;
 191         outpdimm->tckmax_ps = tckmax_ps;
 192         outpdimm->tckmax_max_ps = tckmax_max_ps;
 193         outpdimm->trcd_ps = trcd_ps;
 194         outpdimm->trp_ps = trp_ps;
 195         outpdimm->tras_ps = tras_ps;
 196         outpdimm->twr_ps = twr_ps;
 197         outpdimm->twtr_ps = twtr_ps;
 198         outpdimm->trfc_ps = trfc_ps;
 199         outpdimm->trrd_ps = trrd_ps;
 200         outpdimm->trc_ps = trc_ps;
 201         outpdimm->refresh_rate_ps = refresh_rate_ps;
 202         outpdimm->extended_op_srt = extended_op_srt;
 203         outpdimm->tis_ps = tis_ps;
 204         outpdimm->tih_ps = tih_ps;
 205         outpdimm->tds_ps = tds_ps;
 206         outpdimm->tdh_ps = tdh_ps;
 207         outpdimm->trtp_ps = trtp_ps;
 208         outpdimm->tdqsq_max_ps = tdqsq_max_ps;
 209         outpdimm->tqhs_ps = tqhs_ps;
 210
 211         /* Determine common burst length for all DIMMs. */
 212         temp1 = 0xff;
 213         for (i = 0; i < number_of_dimms; i++) {
 214                 if (dimm_params[i].n_ranks) {
 215                         temp1 &= dimm_params[i].burst_lengths_bitmask;
 216                 }
 217         }
 218         outpdimm->all_dimms_burst_lengths_bitmask = temp1;
 219
 220         /* Determine if all DIMMs registered buffered. */
 221         temp1 = temp2 = 0;
 222         for (i = 0; i < number_of_dimms; i++) {
 223                 if (dimm_params[i].n_ranks) {
 224                         if (dimm_params[i].registered_dimm) {
 225                                 temp1 = 1;
 226 #ifndef CONFIG_SPL_BUILD
 227                                 printf("Detected RDIMM %s\n",
 228                                         dimm_params[i].mpart);
 229 #endif
 230                         } else {
 231                                 temp2 = 1;
 232 #ifndef CONFIG_SPL_BUILD
 233                                 printf("Detected UDIMM %s\n",
 234                                         dimm_params[i].mpart);
 235 #endif
 236                         }
 237                 }
 238         }
 239
 240         outpdimm->all_dimms_registered = 0;
 241         outpdimm->all_dimms_unbuffered = 0;
 242         if (temp1 && !temp2) {
 243                 outpdimm->all_dimms_registered = 1;
 244         } else if (!temp1 && temp2) {
 245                 outpdimm->all_dimms_unbuffered = 1;
 246         } else {
 247                 printf("ERROR:  Mix of registered buffered and unbuffered "
 248                                 "DIMMs detected!\n");
 249         }
 250
 251         temp1 = 0;
 252         if (outpdimm->all_dimms_registered)
 253                 for (j = 0; j < 16; j++) {
 254                         outpdimm->rcw[j] = dimm_params[0].rcw[j];
 255                         for (i = 1; i < number_of_dimms; i++) {
 256                                 if (!dimm_params[i].n_ranks)
 257                                         continue;
 258                                 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
 259                                         temp1 = 1;
 260                                         break;
 261                                 }
 262                         }
 263                 }
 264
 265         if (temp1 != 0)
 266                 printf("ERROR: Mix different RDIMM detected!\n");
 267
 268 #if defined(CONFIG_SYS_FSL_DDR3)
 269         if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
 270                 return 1;
 271 #else
 272         /*
 273          * Compute a CAS latency suitable for all DIMMs
 274          *
 275          * Strategy for SPD-defined latencies: compute only
 276          * CAS latency defined by all DIMMs.
 277          */
 278
 279         /*
 280          * Step 1: find CAS latency common to all DIMMs using bitwise
 281          * operation.
 282          */
 283         temp1 = 0xFF;
 284         for (i = 0; i < number_of_dimms; i++) {
 285                 if (dimm_params[i].n_ranks) {
 286                         temp2 = 0;
 287                         temp2 |= 1 << dimm_params[i].caslat_x;
 288                         temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
 289                         temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
 290                         /*
 291                          * FIXME: If there was no entry for X-2 (X-1) in
 292                          * the SPD, then caslat_x_minus_2
 293                          * (caslat_x_minus_1) contains either 255 or
 294                          * 0xFFFFFFFF because that's what the glorious
 295                          * __ilog2 function returns for an input of 0.
 296                          * On 32-bit PowerPC, left shift counts with bit
 297                          * 26 set (that the value of 255 or 0xFFFFFFFF
 298                          * will have), cause the destination register to
 299                          * be 0.  That is why this works.
 300                          */
 301                         temp1 &= temp2;
 302                 }
 303         }
 304
 305         /*
 306          * Step 2: check each common CAS latency against tCK of each
 307          * DIMM's SPD.
 308          */
 309         lowest_good_caslat = 0;
 310         temp2 = 0;
 311         while (temp1) {
 312                 not_ok = 0;
 313                 temp2 =  __ilog2(temp1);
 314                 debug("checking common caslat = %u\n", temp2);
 315
 316                 /* Check if this CAS latency will work on all DIMMs at tCK. */
 317                 for (i = 0; i < number_of_dimms; i++) {
 318                         if (!dimm_params[i].n_ranks) {
 319                                 continue;
 320                         }
 321                         if (dimm_params[i].caslat_x == temp2) {
 322                                 if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
 323                                         debug("CL = %u ok on DIMM %u at tCK=%u"
 324                                             " ps with its tCKmin_X_ps of %u\n",
 325                                                temp2, i, mclk_ps,
 326                                                dimm_params[i].tckmin_x_ps);
 327                                         continue;
 328                                 } else {
 329                                         not_ok++;
 330                                 }
 331                         }
 332
 333                         if (dimm_params[i].caslat_x_minus_1 == temp2) {
 334                                 unsigned int tckmin_x_minus_1_ps
 335                                         = dimm_params[i].tckmin_x_minus_1_ps;
 336                                 if (mclk_ps >= tckmin_x_minus_1_ps) {
 337                                         debug("CL = %u ok on DIMM %u at "
 338                                                 "tCK=%u ps with its "
 339                                                 "tckmin_x_minus_1_ps of %u\n",
 340                                                temp2, i, mclk_ps,
 341                                                tckmin_x_minus_1_ps);
 342                                         continue;
 343                                 } else {
 344                                         not_ok++;
 345                                 }
 346                         }
 347
 348                         if (dimm_params[i].caslat_x_minus_2 == temp2) {
 349                                 unsigned int tckmin_x_minus_2_ps
 350                                         = dimm_params[i].tckmin_x_minus_2_ps;
 351                                 if (mclk_ps >= tckmin_x_minus_2_ps) {
 352                                         debug("CL = %u ok on DIMM %u at "
 353                                                 "tCK=%u ps with its "
 354                                                 "tckmin_x_minus_2_ps of %u\n",
 355                                                temp2, i, mclk_ps,
 356                                                tckmin_x_minus_2_ps);
 357                                         continue;
 358                                 } else {
 359                                         not_ok++;
 360                                 }
 361                         }
 362                 }
 363
 364                 if (!not_ok) {
 365                         lowest_good_caslat = temp2;
 366                 }
 367
 368                 temp1 &= ~(1 << temp2);
 369         }
 370
 371         debug("lowest common SPD-defined CAS latency = %u\n",
 372                lowest_good_caslat);
 373         outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
 374
 375
 376         /*
 377          * Compute a common 'de-rated' CAS latency.
 378          *
 379          * The strategy here is to find the *highest* dereated cas latency
 380          * with the assumption that all of the DIMMs will support a dereated
 381          * CAS latency higher than or equal to their lowest dereated value.
 382          */
 383         temp1 = 0;
 384         for (i = 0; i < number_of_dimms; i++) {
 385                 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
 386         }
 387         outpdimm->highest_common_derated_caslat = temp1;
 388         debug("highest common dereated CAS latency = %u\n", temp1);
 389 #endif /* #if defined(CONFIG_SYS_FSL_DDR3) */
 390
 391         /* Determine if all DIMMs ECC capable. */
 392         temp1 = 1;
 393         for (i = 0; i < number_of_dimms; i++) {
 394                 if (dimm_params[i].n_ranks &&
 395                         !(dimm_params[i].edc_config & EDC_ECC)) {
 396                         temp1 = 0;
 397                         break;
 398                 }
 399         }
 400         if (temp1) {
 401                 debug("all DIMMs ECC capable\n");
 402         } else {
 403                 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
 404         }
 405         outpdimm->all_dimms_ecc_capable = temp1;
 406
 407 #ifndef CONFIG_SYS_FSL_DDR3
 408         /* FIXME: move to somewhere else to validate. */
 409         if (mclk_ps > tckmax_max_ps) {
 410                 printf("Warning: some of the installed DIMMs "
 411                                 "can not operate this slowly.\n");
 412                 return 1;
 413         }
 414 #endif
 415         /*
 416          * Compute additive latency.
 417          *
 418          * For DDR1, additive latency should be 0.
 419          *
 420          * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
 421          *      which comes from Trcd, and also note that:
 422          *          add_lat + caslat must be >= 4
 423          *
 424          * For DDR3, we use the AL=0
 425          *
 426          * When to use additive latency for DDR2:
 427          *
 428          * I. Because you are using CL=3 and need to do ODT on writes and
 429          *    want functionality.
 430          *    1. Are you going to use ODT? (Does your board not have
 431          *      additional termination circuitry for DQ, DQS, DQS_,
 432          *      DM, RDQS, RDQS_ for x4/x8 configs?)
 433          *    2. If so, is your lowest supported CL going to be 3?
 434          *    3. If so, then you must set AL=1 because
 435          *
 436          *       WL >= 3 for ODT on writes
 437          *       RL = AL + CL
 438          *       WL = RL - 1
 439          *       ->
 440          *       WL = AL + CL - 1
 441          *       AL + CL - 1 >= 3
 442          *       AL + CL >= 4
 443          *  QED
 444          *
 445          *  RL >= 3 for ODT on reads
 446          *  RL = AL + CL
 447          *
 448          *  Since CL aren't usually less than 2, AL=0 is a minimum,
 449          *  so the WL-derived AL should be the  -- FIXME?
 450          *
 451          * II. Because you are using auto-precharge globally and want to
 452          *     use additive latency (posted CAS) to get more bandwidth.
 453          *     1. Are you going to use auto-precharge mode globally?
 454          *
 455          *        Use addtivie latency and compute AL to be 1 cycle less than
 456          *        tRCD, i.e. the READ or WRITE command is in the cycle
 457          *        immediately following the ACTIVATE command..
 458          *
 459          * III. Because you feel like it or want to do some sort of
 460          *      degraded-performance experiment.
 461          *     1.  Do you just want to use additive latency because you feel
 462          *         like it?
 463          *
 464          * Validation:  AL is less than tRCD, and within the other
 465          * read-to-precharge constraints.
 466          */
 467
 468         additive_latency = 0;
 469
 470 #if defined(CONFIG_SYS_FSL_DDR2)
 471         if (lowest_good_caslat < 4) {
 472                 additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
 473                         ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
 474                 if (mclk_to_picos(additive_latency) > trcd_ps) {
 475                         additive_latency = picos_to_mclk(trcd_ps);
 476                         debug("setting additive_latency to %u because it was "
 477                                 " greater than tRCD_ps\n", additive_latency);
 478                 }
 479         }
 480
 481 #elif defined(CONFIG_SYS_FSL_DDR3)
 482         /*
 483          * The system will not use the global auto-precharge mode.
 484          * However, it uses the page mode, so we set AL=0
 485          */
 486         additive_latency = 0;
 487 #endif
 488
 489         /*
 490          * Validate additive latency
 491          * FIXME: move to somewhere else to validate
 492          *
 493          * AL <= tRCD(min)
 494          */
 495         if (mclk_to_picos(additive_latency) > trcd_ps) {
 496                 printf("Error: invalid additive latency exceeds tRCD(min).\n");
 497                 return 1;
 498         }
 499
 500         /*
 501          * RL = CL + AL;  RL >= 3 for ODT_RD_CFG to be enabled
 502          * WL = RL - 1;  WL >= 3 for ODT_WL_CFG to be enabled
 503          * ADD_LAT (the register) must be set to a value less
 504          * than ACTTORW if WL = 1, then AL must be set to 1
 505          * RD_TO_PRE (the register) must be set to a minimum
 506          * tRTP + AL if AL is nonzero
 507          */
 508
 509         /*
 510          * Additive latency will be applied only if the memctl option to
 511          * use it.
 512          */
 513         outpdimm->additive_latency = additive_latency;
 514
 515         debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
 516         debug("trcd_ps   = %u\n", outpdimm->trcd_ps);
 517         debug("trp_ps    = %u\n", outpdimm->trp_ps);
 518         debug("tras_ps   = %u\n", outpdimm->tras_ps);
 519         debug("twr_ps    = %u\n", outpdimm->twr_ps);
 520         debug("twtr_ps   = %u\n", outpdimm->twtr_ps);
 521         debug("trfc_ps   = %u\n", outpdimm->trfc_ps);
 522         debug("trrd_ps   = %u\n", outpdimm->trrd_ps);
 523         debug("trc_ps    = %u\n", outpdimm->trc_ps);
 524
 525         return 0;
 526 }