drivers/ddr/fsl/util.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #ifdef CONFIG_PPC
  11 #include <asm/fsl_law.h>
  12 #endif
  13 #include <div64.h>
  14
  15 #include <fsl_ddr.h>
  16 #include <fsl_immap.h>
  17 #include <asm/io.h>
  18
  19 /* To avoid 64-bit full-divides, we factor this here */
  20 #define ULL_2E12 2000000000000ULL
  21 #define UL_5POW12 244140625UL
  22 #define UL_2POW13 (1UL << 13)
  23
  24 #define ULL_8FS 0xFFFFFFFFULL
  25
  26 u32 fsl_ddr_get_version(void)
  27 {
  28         struct ccsr_ddr __iomem *ddr;
  29         u32 ver_major_minor_errata;
  30
  31         ddr = (void *)_DDR_ADDR;
  32         ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8;
  33         ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8;
  34
  35         return ver_major_minor_errata;
  36 }
  37
  38 /*
  39  * Round up mclk_ps to nearest 1 ps in memory controller code
  40  * if the error is 0.5ps or more.
  41  *
  42  * If an imprecise data rate is too high due to rounding error
  43  * propagation, compute a suitably rounded mclk_ps to compute
  44  * a working memory controller configuration.
  45  */
  46 unsigned int get_memory_clk_period_ps(void)
  47 {
  48         unsigned int data_rate = get_ddr_freq(0);
  49         unsigned int result;
  50
  51         /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
  52         unsigned long long rem, mclk_ps = ULL_2E12;
  53
  54         /* Now perform the big divide, the result fits in 32-bits */
  55         rem = do_div(mclk_ps, data_rate);
  56         result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
  57
  58         return result;
  59 }
  60
  61 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  62 unsigned int picos_to_mclk(unsigned int picos)
  63 {
  64         unsigned long long clks, clks_rem;
  65         unsigned long data_rate = get_ddr_freq(0);
  66
  67         /* Short circuit for zero picos */
  68         if (!picos)
  69                 return 0;
  70
  71         /* First multiply the time by the data rate (32x32 => 64) */
  72         clks = picos * (unsigned long long)data_rate;
  73         /*
  74          * Now divide by 5^12 and track the 32-bit remainder, then divide
  75          * by 2*(2^12) using shifts (and updating the remainder).
  76          */
  77         clks_rem = do_div(clks, UL_5POW12);
  78         clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
  79         clks >>= 13;
  80
  81         /* If we had a remainder greater than the 1ps error, then round up */
  82         if (clks_rem > data_rate)
  83                 clks++;
  84
  85         /* Clamp to the maximum representable value */
  86         if (clks > ULL_8FS)
  87                 clks = ULL_8FS;
  88         return (unsigned int) clks;
  89 }
  90
  91 unsigned int mclk_to_picos(unsigned int mclk)
  92 {
  93         return get_memory_clk_period_ps() * mclk;
  94 }
  95
  96 #ifdef CONFIG_PPC
  97 void
  98 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
  99                            unsigned int law_memctl,
 100                            unsigned int ctrl_num)
 101 {
 102         unsigned long long base = memctl_common_params->base_address;
 103         unsigned long long size = memctl_common_params->total_mem;
 104
 105         /*
 106          * If no DIMMs on this controller, do not proceed any further.
 107          */
 108         if (!memctl_common_params->ndimms_present) {
 109                 return;
 110         }
 111
 112 #if !defined(CONFIG_PHYS_64BIT)
 113         if (base >= CONFIG_MAX_MEM_MAPPED)
 114                 return;
 115         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
 116                 size = CONFIG_MAX_MEM_MAPPED - base;
 117 #endif
 118         if (set_ddr_laws(base, size, law_memctl) < 0) {
 119                 printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,
 120                         law_memctl);
 121                 return ;
 122         }
 123         debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n",
 124                 base, size, law_memctl);
 125 }
 126
 127 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 128 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 129                          unsigned int memctl_interleaved,
 130                          unsigned int ctrl_num);
 131 #endif
 132
 133 void fsl_ddr_set_intl3r(const unsigned int granule_size)
 134 {
 135 #ifdef CONFIG_E6500
 136         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 137         *mcintl3r = 0x80000000 | (granule_size & 0x1f);
 138         debug("Enable MCINTL3R with granule size 0x%x\n", granule_size);
 139 #endif
 140 }
 141
 142 u32 fsl_ddr_get_intl3r(void)
 143 {
 144         u32 val = 0;
 145 #ifdef CONFIG_E6500
 146         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 147         val = *mcintl3r;
 148 #endif
 149         return val;
 150 }
 151
 152 void board_add_ram_info(int use_default)
 153 {
 154         struct ccsr_ddr __iomem *ddr =
 155                 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
 156
 157 #if     defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
 158         u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 159 #endif
 160 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 161         uint32_t cs0_config = ddr_in32(&ddr->cs0_config);
 162 #endif
 163         uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 164         int cas_lat;
 165
 166 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
 167         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
 168                 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
 169                 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 170         }
 171 #endif
 172 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
 173         if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
 174                 ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
 175                 sdram_cfg = ddr_in32(&ddr->sdram_cfg);
 176         }
 177 #endif
 178         puts(" (DDR");
 179         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 180                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 181         case SDRAM_TYPE_DDR1:
 182                 puts("1");
 183                 break;
 184         case SDRAM_TYPE_DDR2:
 185                 puts("2");
 186                 break;
 187         case SDRAM_TYPE_DDR3:
 188                 puts("3");
 189                 break;
 190         case SDRAM_TYPE_DDR4:
 191                 puts("4");
 192                 break;
 193         default:
 194                 puts("?");
 195                 break;
 196         }
 197
 198         if (sdram_cfg & SDRAM_CFG_32_BE)
 199                 puts(", 32-bit");
 200         else if (sdram_cfg & SDRAM_CFG_16_BE)
 201                 puts(", 16-bit");
 202         else
 203                 puts(", 64-bit");
 204
 205         /* Calculate CAS latency based on timing cfg values */
 206         cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
 207         if (fsl_ddr_get_version() <= 0x40400)
 208                 cas_lat += 1;
 209         else
 210                 cas_lat += 2;
 211         cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
 212         printf(", CL=%d", cas_lat >> 1);
 213         if (cas_lat & 0x1)
 214                 puts(".5");
 215
 216         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 217                 puts(", ECC on)");
 218         else
 219                 puts(", ECC off)");
 220
 221 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
 222 #ifdef CONFIG_E6500
 223         if (*mcintl3r & 0x80000000) {
 224                 puts("\n");
 225                 puts("       DDR Controller Interleaving Mode: ");
 226                 switch (*mcintl3r & 0x1f) {
 227                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 228                         puts("3-way 1KB");
 229                         break;
 230                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 231                         puts("3-way 4KB");
 232                         break;
 233                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 234                         puts("3-way 8KB");
 235                         break;
 236                 default:
 237                         puts("3-way UNKNOWN");
 238                         break;
 239                 }
 240         }
 241 #endif
 242 #endif
 243 #if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
 244         if (cs0_config & 0x20000000) {
 245                 puts("\n");
 246                 puts("       DDR Controller Interleaving Mode: ");
 247
 248                 switch ((cs0_config >> 24) & 0xf) {
 249                 case FSL_DDR_256B_INTERLEAVING:
 250                         puts("256B");
 251                         break;
 252                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 253                         puts("cache line");
 254                         break;
 255                 case FSL_DDR_PAGE_INTERLEAVING:
 256                         puts("page");
 257                         break;
 258                 case FSL_DDR_BANK_INTERLEAVING:
 259                         puts("bank");
 260                         break;
 261                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 262                         puts("super-bank");
 263                         break;
 264                 default:
 265                         puts("invalid");
 266                         break;
 267                 }
 268         }
 269 #endif
 270
 271         if ((sdram_cfg >> 8) & 0x7f) {
 272                 puts("\n");
 273                 puts("       DDR Chip-Select Interleaving Mode: ");
 274                 switch(sdram_cfg >> 8 & 0x7f) {
 275                 case FSL_DDR_CS0_CS1_CS2_CS3:
 276                         puts("CS0+CS1+CS2+CS3");
 277                         break;
 278                 case FSL_DDR_CS0_CS1:
 279                         puts("CS0+CS1");
 280                         break;
 281                 case FSL_DDR_CS2_CS3:
 282                         puts("CS2+CS3");
 283                         break;
 284                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 285                         puts("CS0+CS1 and CS2+CS3");
 286                         break;
 287                 default:
 288                         puts("invalid");
 289                         break;
 290                 }
 291         }
 292 }