2 * Freescale i.MX28 APBH DMA driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/list.h>
17 #include <asm/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/imx-common/dma.h>
23 #include <asm/imx-common/regs-apbh.h>
25 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
26 static struct mxs_apbh_regs *apbh_regs = (struct mxs_apbh_regs *)MXS_APBH_BASE;
29 * Test is the DMA channel is valid channel
31 int mxs_dma_validate_chan(int channel)
33 struct mxs_dma_chan *pchan;
35 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS)) {
36 printf("Invalid DMA channel %d\n", channel);
40 pchan = mxs_dma_channels + channel;
41 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) {
42 printf("DMA channel %d not allocated\n", channel);
50 * Return the address of the command within a descriptor.
52 static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
54 return desc->address + offsetof(struct mxs_dma_desc, cmd);
58 * Read a DMA channel's hardware semaphore.
60 * As used by the MXS platform's DMA software, the DMA channel's hardware
61 * semaphore reflects the number of DMA commands the hardware will process, but
62 * has not yet finished. This is a volatile value read directly from hardware,
63 * so it must be be viewed as immediately stale.
65 * If the channel is not marked busy, or has finished processing all its
66 * commands, this value should be zero.
68 * See mxs_dma_append() for details on how DMA command blocks must be configured
69 * to maintain the expected behavior of the semaphore's value.
71 static int mxs_dma_read_semaphore(int channel)
76 ret = mxs_dma_validate_chan(channel);
80 tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
82 tmp &= APBH_CHn_SEMA_PHORE_MASK;
83 tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
88 #ifndef CONFIG_SYS_DCACHE_OFF
89 void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
94 addr = (uint32_t)desc;
95 size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
97 flush_dcache_range(addr, addr + size);
100 inline void mxs_dma_flush_desc(struct mxs_dma_desc *desc) {}
104 * Enable a DMA channel.
106 * If the given channel has any DMA descriptors on its active list, this
107 * function causes the DMA hardware to begin processing them.
109 * This function marks the DMA channel as "busy," whether or not there are any
110 * descriptors to process.
112 static int mxs_dma_enable(int channel)
115 struct mxs_dma_chan *pchan;
116 struct mxs_dma_desc *pdesc;
119 ret = mxs_dma_validate_chan(channel);
123 pchan = mxs_dma_channels + channel;
125 if (pchan->pending_num == 0) {
126 pchan->flags |= MXS_DMA_FLAGS_BUSY;
130 pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
134 if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
135 if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
138 sem = mxs_dma_read_semaphore(channel);
143 pdesc = list_entry(pdesc->node.next,
144 struct mxs_dma_desc, node);
145 writel(mxs_dma_cmd_address(pdesc),
146 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
148 writel(pchan->pending_num,
149 &apbh_regs->ch[channel].hw_apbh_ch_sema);
150 pchan->active_num += pchan->pending_num;
151 pchan->pending_num = 0;
153 pchan->active_num += pchan->pending_num;
154 pchan->pending_num = 0;
155 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
156 &apbh_regs->hw_apbh_ctrl0_clr);
157 writel(mxs_dma_cmd_address(pdesc),
158 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
159 writel(pchan->active_num,
160 &apbh_regs->ch[channel].hw_apbh_ch_sema);
163 pchan->flags |= MXS_DMA_FLAGS_BUSY;
168 * Disable a DMA channel.
170 * This function shuts down a DMA channel and marks it as "not busy." Any
171 * descriptors on the active list are immediately moved to the head of the
172 * "done" list, whether or not they have actually been processed by the
173 * hardware. The "ready" flags of these descriptors are NOT cleared, so they
174 * still appear to be active.
176 * This function immediately shuts down a DMA channel's hardware, aborting any
177 * I/O that may be in progress, potentially leaving I/O hardware in an undefined
178 * state. It is unwise to call this function if there is ANY chance the hardware
179 * is still processing a command.
181 static int mxs_dma_disable(int channel)
183 struct mxs_dma_chan *pchan;
186 ret = mxs_dma_validate_chan(channel);
190 pchan = mxs_dma_channels + channel;
192 if ((pchan->flags & MXS_DMA_FLAGS_BUSY)) {
193 printf("%s: DMA channel %d busy\n", __func__, channel);
196 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
197 &apbh_regs->hw_apbh_ctrl0_set);
198 pchan->active_num = 0;
199 pchan->pending_num = 0;
200 list_splice_init(&pchan->active, &pchan->done);
206 * Resets the DMA channel hardware.
208 static int mxs_dma_reset(int channel)
211 #if defined(CONFIG_MX23)
212 uint32_t *setreg = &apbh_regs->hw_apbh_ctrl0_set;
213 uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
214 #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
215 uint32_t *setreg = &apbh_regs->hw_apbh_channel_ctrl_set;
216 uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
219 ret = mxs_dma_validate_chan(channel);
223 writel(1 << (channel + offset), setreg);
229 * Enable or disable DMA interrupt.
231 * This function enables the given DMA channel to interrupt the CPU.
233 static int mxs_dma_enable_irq(int channel, int enable)
237 ret = mxs_dma_validate_chan(channel);
242 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
243 &apbh_regs->hw_apbh_ctrl1_set);
245 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
246 &apbh_regs->hw_apbh_ctrl1_clr);
252 * Clear DMA interrupt.
254 * The software that is using the DMA channel must register to receive its
255 * interrupts and, when they arrive, must call this function to clear them.
257 static int mxs_dma_ack_irq(int channel)
261 ret = mxs_dma_validate_chan(channel);
265 writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
266 writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
272 * Request to reserve a DMA channel
274 static int mxs_dma_request(int channel)
276 struct mxs_dma_chan *pchan;
278 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
281 pchan = mxs_dma_channels + channel;
282 if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
285 if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
288 pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
289 pchan->active_num = 0;
290 pchan->pending_num = 0;
292 INIT_LIST_HEAD(&pchan->active);
293 INIT_LIST_HEAD(&pchan->done);
299 * Release a DMA channel.
301 * This function releases a DMA channel from its current owner.
303 * The channel will NOT be released if it's marked "busy" (see
306 int mxs_dma_release(int channel)
308 struct mxs_dma_chan *pchan;
311 ret = mxs_dma_validate_chan(channel);
315 pchan = mxs_dma_channels + channel;
317 if (pchan->flags & MXS_DMA_FLAGS_BUSY)
321 pchan->active_num = 0;
322 pchan->pending_num = 0;
323 pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
329 * Allocate DMA descriptor
331 struct mxs_dma_desc *mxs_dma_desc_alloc(void)
333 struct mxs_dma_desc *pdesc;
336 size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
337 pdesc = memalign(MXS_DMA_ALIGNMENT, size);
342 memset(pdesc, 0, sizeof(*pdesc));
343 pdesc->address = (dma_addr_t)pdesc;
349 * Free DMA descriptor
351 void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
360 * Add a DMA descriptor to a channel.
362 * If the descriptor list for this channel is not empty, this function sets the
363 * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
364 * it will chain to the new descriptor's command.
366 * Then, this function marks the new descriptor as "ready," adds it to the end
367 * of the active descriptor list, and increments the count of pending
370 * The MXS platform DMA software imposes some rules on DMA commands to maintain
371 * important invariants. These rules are NOT checked, but they must be carefully
372 * applied by software that uses MXS DMA channels.
375 * The DMA channel's hardware semaphore must reflect the number of DMA
376 * commands the hardware will process, but has not yet finished.
379 * A DMA channel begins processing commands when its hardware semaphore is
380 * written with a value greater than zero, and it stops processing commands
381 * when the semaphore returns to zero.
383 * When a channel finishes a DMA command, it will decrement its semaphore if
384 * the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
386 * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
387 * unless it suits the purposes of the software. For example, one could
388 * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
389 * bit set only in the last one. Then, setting the DMA channel's hardware
390 * semaphore to one would cause the entire series of five commands to be
391 * processed. However, this example would violate the invariant given above.
394 * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
395 * channel's hardware semaphore will be decremented EVERY time a command is
398 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
400 struct mxs_dma_chan *pchan;
401 struct mxs_dma_desc *last;
404 ret = mxs_dma_validate_chan(channel);
408 pchan = mxs_dma_channels + channel;
410 pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
411 pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
413 if (!list_empty(&pchan->active)) {
414 last = list_entry(pchan->active.prev, struct mxs_dma_desc,
417 pdesc->flags &= ~MXS_DMA_DESC_FIRST;
418 last->flags &= ~MXS_DMA_DESC_LAST;
420 last->cmd.next = mxs_dma_cmd_address(pdesc);
421 last->cmd.data |= MXS_DMA_DESC_CHAIN;
423 mxs_dma_flush_desc(last);
425 pdesc->flags |= MXS_DMA_DESC_READY;
426 if (pdesc->flags & MXS_DMA_DESC_FIRST)
427 pchan->pending_num++;
428 list_add_tail(&pdesc->node, &pchan->active);
430 mxs_dma_flush_desc(pdesc);
436 * Clean up processed DMA descriptors.
438 * This function removes processed DMA descriptors from the "active" list. Pass
439 * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
440 * to get the descriptors moved to the channel's "done" list. Descriptors on
441 * the "done" list can be retrieved with mxs_dma_get_finished().
443 * This function marks the DMA channel as "not busy" if no unprocessed
444 * descriptors remain on the "active" list.
446 static int mxs_dma_finish(int channel, struct list_head *head)
449 struct mxs_dma_chan *pchan;
450 struct list_head *p, *q;
451 struct mxs_dma_desc *pdesc;
454 ret = mxs_dma_validate_chan(channel);
458 pchan = mxs_dma_channels + channel;
460 sem = mxs_dma_read_semaphore(channel);
464 if (sem == pchan->active_num)
467 list_for_each_safe(p, q, &pchan->active) {
468 if ((pchan->active_num) <= sem)
471 pdesc = list_entry(p, struct mxs_dma_desc, node);
472 pdesc->flags &= ~MXS_DMA_DESC_READY;
475 list_move_tail(p, head);
477 list_move_tail(p, &pchan->done);
479 if (pdesc->flags & MXS_DMA_DESC_LAST)
484 pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
490 * Wait for DMA channel to complete
492 static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
496 ret = mxs_dma_validate_chan(chan);
500 if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
501 1 << chan, timeout)) {
510 * Execute the DMA channel
512 int mxs_dma_go(int chan)
514 uint32_t timeout = 10000;
517 LIST_HEAD(tmp_desc_list);
519 mxs_dma_enable_irq(chan, 1);
520 mxs_dma_enable(chan);
522 /* Wait for DMA to finish. */
523 ret = mxs_dma_wait_complete(timeout, chan);
525 /* Clear out the descriptors we just ran. */
526 mxs_dma_finish(chan, &tmp_desc_list);
528 /* Shut the DMA channel down. */
529 mxs_dma_ack_irq(chan);
531 mxs_dma_enable_irq(chan, 0);
532 mxs_dma_disable(chan);
538 * Initialize the DMA hardware
540 void mxs_dma_init(void)
542 mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
544 #ifdef CONFIG_APBH_DMA_BURST8
545 writel(APBH_CTRL0_AHB_BURST8_EN,
546 &apbh_regs->hw_apbh_ctrl0_set);
548 writel(APBH_CTRL0_AHB_BURST8_EN,
549 &apbh_regs->hw_apbh_ctrl0_clr);
552 #ifdef CONFIG_APBH_DMA_BURST
553 writel(APBH_CTRL0_APB_BURST_EN,
554 &apbh_regs->hw_apbh_ctrl0_set);
556 writel(APBH_CTRL0_APB_BURST_EN,
557 &apbh_regs->hw_apbh_ctrl0_clr);
561 int mxs_dma_init_channel(int channel)
563 struct mxs_dma_chan *pchan;
566 pchan = mxs_dma_channels + channel;
567 pchan->flags = MXS_DMA_FLAGS_VALID;
569 ret = mxs_dma_request(channel);
572 printf("MXS DMA: Can't acquire DMA channel %i\n",
577 mxs_dma_reset(channel);
578 mxs_dma_ack_irq(channel);