2 * Freescale i.MX28 GPIO control code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/errno.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/imx-regs.h>
18 #if defined(CONFIG_SOC_MX23)
19 #define PINCTRL_BANKS 3
20 #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
21 #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
22 #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
23 #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
24 #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
25 #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
26 #elif defined(CONFIG_SOC_MX28)
27 #define PINCTRL_BANKS 5
28 #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
29 #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
30 #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
31 #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
32 #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
33 #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
35 #error "Please select CONFIG_SOC_MX23 or CONFIG_SOC_MX28"
38 void mxs_gpio_init(void)
42 for (i = 0; i < PINCTRL_BANKS; i++) {
43 writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
44 writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
45 /* Use SCT address here to clear the IRQSTAT bits */
46 writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
50 int gpio_get_value(unsigned gpio)
52 uint32_t bank = PAD_BANK(gpio);
53 uint32_t offset = PINCTRL_DIN(bank);
54 struct mxs_register_32 *reg =
55 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
57 return (readl(®->reg) >> PAD_PIN(gpio)) & 1;
60 int gpio_set_value(unsigned gpio, int value)
62 uint32_t bank = PAD_BANK(gpio);
63 uint32_t offset = PINCTRL_DOUT(bank);
64 struct mxs_register_32 *reg =
65 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
68 writel(1 << PAD_PIN(gpio), ®->reg_set);
70 writel(1 << PAD_PIN(gpio), ®->reg_clr);
75 int gpio_direction_input(unsigned gpio)
77 uint32_t bank = PAD_BANK(gpio);
78 uint32_t offset = PINCTRL_DOE(bank);
79 struct mxs_register_32 *reg =
80 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
82 writel(1 << PAD_PIN(gpio), ®->reg_clr);
87 int gpio_direction_output(unsigned gpio, int value)
89 uint32_t bank = PAD_BANK(gpio);
90 uint32_t offset = PINCTRL_DOE(bank);
91 struct mxs_register_32 *reg =
92 (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
94 gpio_set_value(gpio, value);
96 writel(1 << PAD_PIN(gpio), ®->reg_set);
101 int gpio_request(unsigned gpio, const char *label)
103 if (PAD_BANK(gpio) >= PINCTRL_BANKS)
109 int gpio_free(unsigned gpio)