drivers/i2c/s3c24x0_i2c.c

   1 /*
   2  * (C) Copyright 2002
   3  * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* This code should work for both the S3C2400 and the S3C2410
  25  * as they seem to have the same I2C controller inside.
  26  * The different address mapping is handled by the s3c24xx.h files below.
  27  */
  28
  29 #include <common.h>
  30 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  31 #include <asm/arch/clk.h>
  32 #include <asm/arch/cpu.h>
  33 #else
  34 #include <asm/arch/s3c24x0_cpu.h>
  35 #endif
  36 #include <asm/io.h>
  37 #include <i2c.h>
  38 #include "s3c24x0_i2c.h"
  39
  40 #ifdef CONFIG_HARD_I2C
  41
  42 #define I2C_WRITE       0
  43 #define I2C_READ        1
  44
  45 #define I2C_OK          0
  46 #define I2C_NOK         1
  47 #define I2C_NACK        2
  48 #define I2C_NOK_LA      3       /* Lost arbitration */
  49 #define I2C_NOK_TOUT    4       /* time out */
  50
  51 #define I2CSTAT_BSY     0x20    /* Busy bit */
  52 #define I2CSTAT_NACK    0x01    /* Nack bit */
  53 #define I2CCON_ACKGEN   0x80    /* Acknowledge generation */
  54 #define I2CCON_IRPND    0x10    /* Interrupt pending bit */
  55 #define I2C_MODE_MT     0xC0    /* Master Transmit Mode */
  56 #define I2C_MODE_MR     0x80    /* Master Receive Mode */
  57 #define I2C_START_STOP  0x20    /* START / STOP */
  58 #define I2C_TXRX_ENA    0x10    /* I2C Tx/Rx enable */
  59
  60 #define I2C_TIMEOUT 1           /* 1 second */
  61
  62
  63 static unsigned int g_current_bus;      /* Stores Current I2C Bus */
  64
  65 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
  66 static int GetI2CSDA(void)
  67 {
  68         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  69
  70 #ifdef CONFIG_S3C2410
  71         return (readl(&gpio->gpedat) & 0x8000) >> 15;
  72 #endif
  73 #ifdef CONFIG_S3C2400
  74         return (readl(&gpio->pgdat) & 0x0020) >> 5;
  75 #endif
  76 }
  77
  78 #if 0
  79 static void SetI2CSDA(int x)
  80 {
  81         rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
  82 }
  83 #endif
  84
  85 static void SetI2CSCL(int x)
  86 {
  87         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
  88
  89 #ifdef CONFIG_S3C2410
  90         writel((readl(&gpio->gpedat) & ~0x4000) |
  91                                         (x & 1) << 14, &gpio->gpedat);
  92 #endif
  93 #ifdef CONFIG_S3C2400
  94         writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
  95 #endif
  96 }
  97 #endif
  98
  99 static int WaitForXfer(struct s3c24x0_i2c *i2c)
 100 {
 101         int i;
 102
 103         i = I2C_TIMEOUT * 10000;
 104         while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) {
 105                 udelay(100);
 106                 i--;
 107         }
 108
 109         return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
 110 }
 111
 112 static int IsACK(struct s3c24x0_i2c *i2c)
 113 {
 114         return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
 115 }
 116
 117 static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 118 {
 119         writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 120 }
 121
 122 static struct s3c24x0_i2c *get_base_i2c(void)
 123 {
 124 #ifdef CONFIG_EXYNOS4
 125         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 126                                                         + (EXYNOS4_I2C_SPACING
 127                                                         * g_current_bus));
 128         return i2c;
 129 #elif defined CONFIG_EXYNOS5
 130         struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
 131                                                         + (EXYNOS5_I2C_SPACING
 132                                                         * g_current_bus));
 133         return i2c;
 134 #else
 135         return s3c24x0_get_base_i2c();
 136 #endif
 137 }
 138
 139 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
 140 {
 141         ulong freq, pres = 16, div;
 142 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 143         freq = get_i2c_clk();
 144 #else
 145         freq = get_PCLK();
 146 #endif
 147         /* calculate prescaler and divisor values */
 148         if ((freq / pres / (16 + 1)) > speed)
 149                 /* set prescaler to 512 */
 150                 pres = 512;
 151
 152         div = 0;
 153         while ((freq / pres / (div + 1)) > speed)
 154                 div++;
 155
 156         /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
 157         writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
 158
 159         /* init to SLAVE REVEIVE and set slaveaddr */
 160         writel(0, &i2c->iicstat);
 161         writel(slaveadd, &i2c->iicadd);
 162         /* program Master Transmit (and implicit STOP) */
 163         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 164 }
 165
 166 /*
 167  * MULTI BUS I2C support
 168  */
 169
 170 #ifdef CONFIG_I2C_MULTI_BUS
 171 int i2c_set_bus_num(unsigned int bus)
 172 {
 173         struct s3c24x0_i2c *i2c;
 174
 175         if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
 176                 debug("Bad bus: %d\n", bus);
 177                 return -1;
 178         }
 179
 180         g_current_bus = bus;
 181         i2c = get_base_i2c();
 182         i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 183
 184         return 0;
 185 }
 186
 187 unsigned int i2c_get_bus_num(void)
 188 {
 189         return g_current_bus;
 190 }
 191 #endif
 192
 193 void i2c_init(int speed, int slaveadd)
 194 {
 195         struct s3c24x0_i2c *i2c;
 196 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 197         struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 198 #endif
 199         int i;
 200
 201         /* By default i2c channel 0 is the current bus */
 202         g_current_bus = 0;
 203         i2c = get_base_i2c();
 204
 205         /* wait for some time to give previous transfer a chance to finish */
 206         i = I2C_TIMEOUT * 1000;
 207         while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 208                 udelay(1000);
 209                 i--;
 210         }
 211
 212 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 213         if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
 214 #ifdef CONFIG_S3C2410
 215                 ulong old_gpecon = readl(&gpio->gpecon);
 216 #endif
 217 #ifdef CONFIG_S3C2400
 218                 ulong old_gpecon = readl(&gpio->pgcon);
 219 #endif
 220                 /* bus still busy probably by (most) previously interrupted
 221                    transfer */
 222
 223 #ifdef CONFIG_S3C2410
 224                 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
 225                 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000,
 226                        &gpio->gpecon);
 227 #endif
 228 #ifdef CONFIG_S3C2400
 229                 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
 230                 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000,
 231                        &gpio->pgcon);
 232 #endif
 233
 234                 /* toggle I2CSCL until bus idle */
 235                 SetI2CSCL(0);
 236                 udelay(1000);
 237                 i = 10;
 238                 while ((i > 0) && (GetI2CSDA() != 1)) {
 239                         SetI2CSCL(1);
 240                         udelay(1000);
 241                         SetI2CSCL(0);
 242                         udelay(1000);
 243                         i--;
 244                 }
 245                 SetI2CSCL(1);
 246                 udelay(1000);
 247
 248                 /* restore pin functions */
 249 #ifdef CONFIG_S3C2410
 250                 writel(old_gpecon, &gpio->gpecon);
 251 #endif
 252 #ifdef CONFIG_S3C2400
 253                 writel(old_gpecon, &gpio->pgcon);
 254 #endif
 255         }
 256 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
 257         i2c_ch_init(i2c, speed, slaveadd);
 258 }
 259
 260 /*
 261  * cmd_type is 0 for write, 1 for read.
 262  *
 263  * addr_len can take any value from 0-255, it is only limited
 264  * by the char, we could make it larger if needed. If it is
 265  * 0 we skip the address write cycle.
 266  */
 267 static int i2c_transfer(struct s3c24x0_i2c *i2c,
 268                         unsigned char cmd_type,
 269                         unsigned char chip,
 270                         unsigned char addr[],
 271                         unsigned char addr_len,
 272                         unsigned char data[],
 273                         unsigned short data_len)
 274 {
 275         int i, result;
 276
 277         if (data == 0 || data_len == 0) {
 278                 /*Don't support data transfer of no length or to address 0 */
 279                 debug("i2c_transfer: bad call\n");
 280                 return I2C_NOK;
 281         }
 282
 283         /* Check I2C bus idle */
 284         i = I2C_TIMEOUT * 1000;
 285         while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) {
 286                 udelay(1000);
 287                 i--;
 288         }
 289
 290         if (readl(&i2c->iicstat) & I2CSTAT_BSY)
 291                 return I2C_NOK_TOUT;
 292
 293         writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
 294         result = I2C_OK;
 295
 296         switch (cmd_type) {
 297         case I2C_WRITE:
 298                 if (addr && addr_len) {
 299                         writel(chip, &i2c->iicds);
 300                         /* send START */
 301                         writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 302                                &i2c->iicstat);
 303                         i = 0;
 304                         while ((i < addr_len) && (result == I2C_OK)) {
 305                                 result = WaitForXfer(i2c);
 306                                 writel(addr[i], &i2c->iicds);
 307                                 ReadWriteByte(i2c);
 308                                 i++;
 309                         }
 310                         i = 0;
 311                         while ((i < data_len) && (result == I2C_OK)) {
 312                                 result = WaitForXfer(i2c);
 313                                 writel(data[i], &i2c->iicds);
 314                                 ReadWriteByte(i2c);
 315                                 i++;
 316                         }
 317                 } else {
 318                         writel(chip, &i2c->iicds);
 319                         /* send START */
 320                         writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
 321                                &i2c->iicstat);
 322                         i = 0;
 323                         while ((i < data_len) && (result = I2C_OK)) {
 324                                 result = WaitForXfer(i2c);
 325                                 writel(data[i], &i2c->iicds);
 326                                 ReadWriteByte(i2c);
 327                                 i++;
 328                         }
 329                 }
 330
 331                 if (result == I2C_OK)
 332                         result = WaitForXfer(i2c);
 333
 334                 /* send STOP */
 335                 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 336                 ReadWriteByte(i2c);
 337                 break;
 338
 339         case I2C_READ:
 340                 if (addr && addr_len) {
 341                         writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 342                         writel(chip, &i2c->iicds);
 343                         /* send START */
 344                         writel(readl(&i2c->iicstat) | I2C_START_STOP,
 345                                &i2c->iicstat);
 346                         result = WaitForXfer(i2c);
 347                         if (IsACK(i2c)) {
 348                                 i = 0;
 349                                 while ((i < addr_len) && (result == I2C_OK)) {
 350                                         writel(addr[i], &i2c->iicds);
 351                                         ReadWriteByte(i2c);
 352                                         result = WaitForXfer(i2c);
 353                                         i++;
 354                                 }
 355
 356                                 writel(chip, &i2c->iicds);
 357                                 /* resend START */
 358                                 writel(I2C_MODE_MR | I2C_TXRX_ENA |
 359                                        I2C_START_STOP, &i2c->iicstat);
 360                         ReadWriteByte(i2c);
 361                         result = WaitForXfer(i2c);
 362                                 i = 0;
 363                                 while ((i < data_len) && (result == I2C_OK)) {
 364                                         /* disable ACK for final READ */
 365                                         if (i == data_len - 1)
 366                                                 writel(readl(&i2c->iiccon)
 367                                                         & ~I2CCON_ACKGEN,
 368                                                         &i2c->iiccon);
 369                                 ReadWriteByte(i2c);
 370                                 result = WaitForXfer(i2c);
 371                                         data[i] = readl(&i2c->iicds);
 372                                         i++;
 373                                 }
 374                         } else {
 375                                 result = I2C_NACK;
 376                         }
 377
 378                 } else {
 379                         writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 380                         writel(chip, &i2c->iicds);
 381                         /* send START */
 382                         writel(readl(&i2c->iicstat) | I2C_START_STOP,
 383                                &i2c->iicstat);
 384                         result = WaitForXfer(i2c);
 385
 386                         if (IsACK(i2c)) {
 387                                 i = 0;
 388                                 while ((i < data_len) && (result == I2C_OK)) {
 389                                         /* disable ACK for final READ */
 390                                         if (i == data_len - 1)
 391                                                 writel(readl(&i2c->iiccon) &
 392                                                         ~I2CCON_ACKGEN,
 393                                                         &i2c->iiccon);
 394                                         ReadWriteByte(i2c);
 395                                         result = WaitForXfer(i2c);
 396                                         data[i] = readl(&i2c->iicds);
 397                                         i++;
 398                                 }
 399                         } else {
 400                                 result = I2C_NACK;
 401                         }
 402                 }
 403
 404                 /* send STOP */
 405                 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
 406                 ReadWriteByte(i2c);
 407                 break;
 408
 409         default:
 410                 debug("i2c_transfer: bad call\n");
 411                 result = I2C_NOK;
 412                 break;
 413         }
 414
 415         return result;
 416 }
 417
 418 int i2c_probe(uchar chip)
 419 {
 420         struct s3c24x0_i2c *i2c;
 421         uchar buf[1];
 422
 423         i2c = get_base_i2c();
 424         buf[0] = 0;
 425
 426         /*
 427          * What is needed is to send the chip address and verify that the
 428          * address was <ACK>ed (i.e. there was a chip at that address which
 429          * drove the data line low).
 430          */
 431         return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
 432 }
 433
 434 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 435 {
 436         struct s3c24x0_i2c *i2c;
 437         uchar xaddr[4];
 438         int ret;
 439
 440         if (alen > 4) {
 441                 debug("I2C read: addr len %d not supported\n", alen);
 442                 return 1;
 443         }
 444
 445         if (alen > 0) {
 446                 xaddr[0] = (addr >> 24) & 0xFF;
 447                 xaddr[1] = (addr >> 16) & 0xFF;
 448                 xaddr[2] = (addr >> 8) & 0xFF;
 449                 xaddr[3] = addr & 0xFF;
 450         }
 451
 452 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 453         /*
 454          * EEPROM chips that implement "address overflow" are ones
 455          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 456          * address and the extra bits end up in the "chip address"
 457          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 458          * four 256 byte chips.
 459          *
 460          * Note that we consider the length of the address field to
 461          * still be one byte because the extra address bits are
 462          * hidden in the chip address.
 463          */
 464         if (alen > 0)
 465                 chip |= ((addr >> (alen * 8)) &
 466                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 467 #endif
 468         i2c = get_base_i2c();
 469         ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen,
 470                         buffer, len);
 471         if (ret != 0) {
 472                 debug("I2c read: failed %d\n", ret);
 473                 return 1;
 474         }
 475         return 0;
 476 }
 477
 478 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 479 {
 480         struct s3c24x0_i2c *i2c;
 481         uchar xaddr[4];
 482
 483         if (alen > 4) {
 484                 debug("I2C write: addr len %d not supported\n", alen);
 485                 return 1;
 486         }
 487
 488         if (alen > 0) {
 489                 xaddr[0] = (addr >> 24) & 0xFF;
 490                 xaddr[1] = (addr >> 16) & 0xFF;
 491                 xaddr[2] = (addr >> 8) & 0xFF;
 492                 xaddr[3] = addr & 0xFF;
 493         }
 494 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 495         /*
 496          * EEPROM chips that implement "address overflow" are ones
 497          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 498          * address and the extra bits end up in the "chip address"
 499          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 500          * four 256 byte chips.
 501          *
 502          * Note that we consider the length of the address field to
 503          * still be one byte because the extra address bits are
 504          * hidden in the chip address.
 505          */
 506         if (alen > 0)
 507                 chip |= ((addr >> (alen * 8)) &
 508                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 509 #endif
 510         i2c = get_base_i2c();
 511         return (i2c_transfer
 512                 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
 513                  len) != 0);
 514 }
 515 #endif /* CONFIG_HARD_I2C */