drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <mmc.h>
  28 #include <part.h>
  29 #include <i2c.h>
  30 #include <twl4030.h>
  31 #include <twl6030.h>
  32 #include <palmas.h>
  33 #include <asm/gpio.h>
  34 #include <asm/io.h>
  35 #include <asm/arch/mmc_host_def.h>
  36 #include <asm/arch/sys_proto.h>
  37
  38 /* common definitions for all OMAPs */
  39 #define SYSCTL_SRC      (1 << 25)
  40 #define SYSCTL_SRD      (1 << 26)
  41
  42 struct omap_hsmmc_data {
  43         struct hsmmc *base_addr;
  44         int cd_gpio;
  45         int wp_gpio;
  46 };
  47
  48 /* If we fail after 1 second wait, something is really bad */
  49 #define MAX_RETRY_MS    1000
  50
  51 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  52 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  53                         unsigned int siz);
  54 static struct mmc hsmmc_dev[3];
  55 static struct omap_hsmmc_data hsmmc_dev_data[3];
  56
  57 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  58         (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
  59 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  60 {
  61         if (!gpio_is_valid(gpio))
  62                 return -1;
  63
  64         if (gpio_request(gpio, label) < 0)
  65                 return -1;
  66
  67         if (gpio_direction_input(gpio) < 0)
  68                 return -1;
  69
  70         return gpio;
  71 }
  72
  73 static int omap_mmc_getcd(struct mmc *mmc)
  74 {
  75         int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
  76         return gpio_get_value(cd_gpio);
  77 }
  78
  79 static int omap_mmc_getwp(struct mmc *mmc)
  80 {
  81         int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio;
  82         return gpio_get_value(wp_gpio);
  83 }
  84 #else
  85 static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
  86 {
  87         return -1;
  88 }
  89
  90 #define omap_mmc_getcd NULL
  91 #define omap_mmc_getwp NULL
  92 #endif
  93
  94 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  95 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  96 {
  97         u32 value = 0;
  98
  99         value = readl((*ctrl)->control_pbiaslite);
 100         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
 101         writel(value, (*ctrl)->control_pbiaslite);
 102         /* set VMMC to 3V */
 103         twl6030_power_mmc_init();
 104         value = readl((*ctrl)->control_pbiaslite);
 105         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 106         writel(value, (*ctrl)->control_pbiaslite);
 107 }
 108 #endif
 109
 110 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 111 static void omap5_pbias_config(struct mmc *mmc)
 112 {
 113         u32 value = 0;
 114
 115         value = readl((*ctrl)->control_pbias);
 116         value &= ~SDCARD_PWRDNZ;
 117         writel(value, (*ctrl)->control_pbias);
 118         udelay(10); /* wait 10 us */
 119         value &= ~SDCARD_BIAS_PWRDNZ;
 120         writel(value, (*ctrl)->control_pbias);
 121
 122         palmas_mmc1_poweron_ldo();
 123
 124         value = readl((*ctrl)->control_pbias);
 125         value |= SDCARD_BIAS_PWRDNZ;
 126         writel(value, (*ctrl)->control_pbias);
 127         udelay(150); /* wait 150 us */
 128         value |= SDCARD_PWRDNZ;
 129         writel(value, (*ctrl)->control_pbias);
 130         udelay(150); /* wait 150 us */
 131 }
 132 #endif
 133
 134 static void mmc_board_init(struct mmc *mmc)
 135 {
 136 #if defined(CONFIG_OMAP34XX)
 137         t2_t *t2_base = (t2_t *)T2_BASE;
 138         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 139         u32 pbias_lite;
 140
 141         pbias_lite = readl(&t2_base->pbias_lite);
 142         pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
 143         writel(pbias_lite, &t2_base->pbias_lite);
 144 #endif
 145 #if defined(CONFIG_TWL4030_POWER)
 146         twl4030_power_mmc_init();
 147         mdelay(100);    /* ramp-up delay from Linux code */
 148 #endif
 149 #if defined(CONFIG_OMAP34XX)
 150         writel(pbias_lite | PBIASLITEPWRDNZ1 |
 151                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
 152                 &t2_base->pbias_lite);
 153
 154         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 155                 &t2_base->devconf0);
 156
 157         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
 158                 &t2_base->devconf1);
 159
 160         /* Change from default of 52MHz to 26MHz if necessary */
 161         if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
 162                 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
 163                         &t2_base->ctl_prog_io1);
 164
 165         writel(readl(&prcm_base->fclken1_core) |
 166                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 167                 &prcm_base->fclken1_core);
 168
 169         writel(readl(&prcm_base->iclken1_core) |
 170                 EN_MMC1 | EN_MMC2 | EN_MMC3,
 171                 &prcm_base->iclken1_core);
 172 #endif
 173
 174 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
 175         /* PBIAS config needed for MMC1 only */
 176         if (mmc->block_dev.dev == 0)
 177                 omap4_vmmc_pbias_config(mmc);
 178 #endif
 179 #if defined(CONFIG_OMAP54XX) && defined(CONFIG_PALMAS_POWER)
 180         if (mmc->block_dev.dev == 0)
 181                 omap5_pbias_config(mmc);
 182 #endif
 183 }
 184
 185 void mmc_init_stream(struct hsmmc *mmc_base)
 186 {
 187         ulong start;
 188
 189         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 190
 191         writel(MMC_CMD0, &mmc_base->cmd);
 192         start = get_timer(0);
 193         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 194                 if (get_timer(start) > MAX_RETRY_MS)
 195                         break;
 196         }
 197         if (!(readl(&mmc_base->stat) & CC_MASK)) {
 198                 printf("%s: timeout waiting for cc!\n", __func__);
 199                 return;
 200         }
 201
 202         writel(CC_MASK, &mmc_base->stat);
 203         writel(MMC_CMD0, &mmc_base->cmd);
 204
 205         start = get_timer(0);
 206         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 207                 if (get_timer(start) > MAX_RETRY_MS)
 208                         break;
 209         }
 210         if (!(readl(&mmc_base->stat) & CC_MASK)) {
 211                 printf("%s: timeout waiting for cc2!\n", __func__);
 212                 return;
 213         }
 214         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 215 }
 216
 217 static int mmc_init_setup(struct mmc *mmc)
 218 {
 219         struct omap_hsmmc_data *priv_data = mmc->priv;
 220         struct hsmmc *mmc_base = priv_data->base_addr;
 221         unsigned int reg_val;
 222         unsigned int dsor;
 223         ulong start;
 224
 225         mmc_board_init(mmc);
 226
 227         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 228                 &mmc_base->sysconfig);
 229         start = get_timer(0);
 230         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 231                 if (get_timer(start) > MAX_RETRY_MS)
 232                         break;
 233         }
 234         if ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 235                 printf("%s: timeout %08x waiting for softreset done!\n", __func__,
 236                         readl(&mmc_base->sysstatus));
 237                 return TIMEOUT;
 238         }
 239         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 240         start = get_timer(0);
 241         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0) {
 242                 if (get_timer(start) > MAX_RETRY_MS)
 243                         break;
 244         }
 245         if ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0) {
 246                 printf("%s: timeout waiting for softresetall!\n", __func__);
 247                 return TIMEOUT;
 248         }
 249         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 250         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 251                 &mmc_base->capa);
 252
 253         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 254
 255         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 256                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 257                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 258
 259         dsor = 240;
 260         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 261                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 262         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 263                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 264         start = get_timer(0);
 265         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 266                 if (get_timer(start) > MAX_RETRY_MS)
 267                         break;
 268         }
 269         if ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 270                 printf("%s: timeout waiting for ics!\n", __func__);
 271                 return TIMEOUT;
 272         }
 273         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 274
 275         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 276
 277         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 278                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 279                 &mmc_base->ie);
 280
 281         mmc_init_stream(mmc_base);
 282
 283         return 0;
 284 }
 285
 286 /*
 287  * MMC controller internal finite state machine reset
 288  *
 289  * Used to reset command or data internal state machines, using respectively
 290  * SRC or SRD bit of SYSCTL register
 291  */
 292 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
 293 {
 294         ulong start;
 295
 296         mmc_reg_out(&mmc_base->sysctl, bit, bit);
 297
 298         start = get_timer(0);
 299         while ((readl(&mmc_base->sysctl) & bit) != 0) {
 300                 if (get_timer(0) - start > MAX_RETRY_MS)
 301                         break;
 302         }
 303         if ((readl(&mmc_base->sysctl) & bit) != 0) {
 304                 printf("%s: timedout waiting for sysctl %x to clear\n", __func__, bit);
 305                 return;
 306         }
 307 }
 308
 309 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 310                         struct mmc_data *data)
 311 {
 312         struct omap_hsmmc_data *priv_data = mmc->priv;
 313         struct hsmmc *mmc_base = priv_data->base_addr;
 314         unsigned int flags, mmc_stat;
 315         ulong start;
 316
 317         start = get_timer(0);
 318         while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 319                 if (get_timer(start) > MAX_RETRY_MS)
 320                         break;
 321         }
 322         if ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
 323                 printf("%s: timeout waiting on cmd inhibit to clear\n", __func__);
 324                 return TIMEOUT;
 325         }
 326         writel(0xFFFFFFFF, &mmc_base->stat);
 327         start = get_timer(0);
 328         while (readl(&mmc_base->stat)) {
 329                 if (get_timer(start) > MAX_RETRY_MS)
 330                         break;
 331         }
 332         if (readl(&mmc_base->stat)) {
 333                 printf("%s: timeout waiting for stat!\n", __func__);
 334                 return TIMEOUT;
 335         }
 336         /*
 337          * CMDREG
 338          * CMDIDX[13:8] : Command index
 339          * DATAPRNT[5]  : Data Present Select
 340          * ENCMDIDX[4]  : Command Index Check Enable
 341          * ENCMDCRC[3]  : Command CRC Check Enable
 342          * RSPTYP[1:0]
 343          *      00 = No Response
 344          *      01 = Length 136
 345          *      10 = Length 48
 346          *      11 = Length 48 Check busy after response
 347          */
 348         /* Delay added before checking the status of frq change
 349          * retry not supported by mmc.c(core file)
 350          */
 351         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 352                 udelay(50000); /* wait 50 ms */
 353
 354         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 355                 flags = 0;
 356         else if (cmd->resp_type & MMC_RSP_136)
 357                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 358         else if (cmd->resp_type & MMC_RSP_BUSY)
 359                 flags = RSP_TYPE_LGHT48B;
 360         else
 361                 flags = RSP_TYPE_LGHT48;
 362
 363         /* enable default flags */
 364         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 365                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 366
 367         if (cmd->resp_type & MMC_RSP_CRC)
 368                 flags |= CCCE_CHECK;
 369         if (cmd->resp_type & MMC_RSP_OPCODE)
 370                 flags |= CICE_CHECK;
 371
 372         if (data) {
 373                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 374                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 375                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 376                         data->blocksize = 512;
 377                         writel(data->blocksize | (data->blocks << 16),
 378                                                         &mmc_base->blk);
 379                 } else
 380                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 381
 382                 if (data->flags & MMC_DATA_READ)
 383                         flags |= (DP_DATA | DDIR_READ);
 384                 else
 385                         flags |= (DP_DATA | DDIR_WRITE);
 386         }
 387
 388         writel(cmd->cmdarg, &mmc_base->arg);
 389         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 390
 391         start = get_timer(0);
 392         while (!(mmc_stat = readl(&mmc_base->stat))) {
 393                 if (get_timer(start) > MAX_RETRY_MS)
 394                         break;
 395         }
 396         if (!mmc_stat) {
 397                 printf("%s : timeout: No status update\n", __func__);
 398                 return TIMEOUT;
 399         }
 400
 401         if ((mmc_stat & IE_CTO) != 0) {
 402                 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
 403                 return TIMEOUT;
 404         } else if ((mmc_stat & ERRI_MASK) != 0)
 405                 return -1;
 406
 407         if (mmc_stat & CC_MASK) {
 408                 writel(CC_MASK, &mmc_base->stat);
 409                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 410                         if (cmd->resp_type & MMC_RSP_136) {
 411                                 /* response type 2 */
 412                                 cmd->response[3] = readl(&mmc_base->rsp10);
 413                                 cmd->response[2] = readl(&mmc_base->rsp32);
 414                                 cmd->response[1] = readl(&mmc_base->rsp54);
 415                                 cmd->response[0] = readl(&mmc_base->rsp76);
 416                         } else
 417                                 /* response types 1, 1b, 3, 4, 5, 6 */
 418                                 cmd->response[0] = readl(&mmc_base->rsp10);
 419                 }
 420         }
 421
 422         if (data && (data->flags & MMC_DATA_READ)) {
 423                 mmc_read_data(mmc_base, data->dest,
 424                                 data->blocksize * data->blocks);
 425         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 426                 mmc_write_data(mmc_base, data->src,
 427                                 data->blocksize * data->blocks);
 428         }
 429         return 0;
 430 }
 431
 432 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 433 {
 434         unsigned int *output_buf = (unsigned int *)buf;
 435         unsigned int mmc_stat;
 436         unsigned int count;
 437
 438         /*
 439          * Start Polled Read
 440          */
 441         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 442         count /= 4;
 443
 444         while (size) {
 445                 ulong start = get_timer(0);
 446
 447                 while (!(mmc_stat = readl(&mmc_base->stat))) {
 448                         if (get_timer(start) > MAX_RETRY_MS)
 449                                 break;
 450                 }
 451                 if (!mmc_stat) {
 452                         printf("%s: timeout waiting for status!\n", __func__);
 453                         return TIMEOUT;
 454                 }
 455
 456                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 457                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 458
 459                 if ((mmc_stat & ERRI_MASK) != 0)
 460                         return 1;
 461
 462                 if (mmc_stat & BRR_MASK) {
 463                         unsigned int k;
 464
 465                         writel(readl(&mmc_base->stat) | BRR_MASK,
 466                                 &mmc_base->stat);
 467                         for (k = 0; k < count; k++) {
 468                                 *output_buf = readl(&mmc_base->data);
 469                                 output_buf++;
 470                         }
 471                         size -= (count*4);
 472                 }
 473
 474                 if (mmc_stat & BWR_MASK)
 475                         writel(readl(&mmc_base->stat) | BWR_MASK,
 476                                 &mmc_base->stat);
 477
 478                 if (mmc_stat & TC_MASK) {
 479                         writel(readl(&mmc_base->stat) | TC_MASK,
 480                                 &mmc_base->stat);
 481                         break;
 482                 }
 483         }
 484         return 0;
 485 }
 486
 487 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 488                                 unsigned int size)
 489 {
 490         unsigned int *input_buf = (unsigned int *)buf;
 491         unsigned int mmc_stat;
 492         unsigned int count;
 493
 494         /*
 495          * Start Polled Read
 496          */
 497         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 498         count /= 4;
 499
 500         while (size) {
 501                 ulong start = get_timer(0);
 502
 503                 while (!(mmc_stat = readl(&mmc_base->stat))) {
 504                         if (get_timer(start) > MAX_RETRY_MS)
 505                                 break;
 506                 }
 507                 if (!mmc_stat) {
 508                         printf("%s: timeout waiting for status!\n", __func__);
 509                         return TIMEOUT;
 510                 }
 511
 512                 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
 513                         mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
 514
 515                 if ((mmc_stat & ERRI_MASK) != 0)
 516                         return 1;
 517
 518                 if (mmc_stat & BWR_MASK) {
 519                         unsigned int k;
 520
 521                         writel(readl(&mmc_base->stat) | BWR_MASK,
 522                                         &mmc_base->stat);
 523                         for (k = 0; k < count; k++) {
 524                                 writel(*input_buf, &mmc_base->data);
 525                                 input_buf++;
 526                         }
 527                         size -= (count*4);
 528                 }
 529
 530                 if (mmc_stat & BRR_MASK)
 531                         writel(readl(&mmc_base->stat) | BRR_MASK,
 532                                 &mmc_base->stat);
 533
 534                 if (mmc_stat & TC_MASK) {
 535                         writel(readl(&mmc_base->stat) | TC_MASK,
 536                                 &mmc_base->stat);
 537                         break;
 538                 }
 539         }
 540         return 0;
 541 }
 542
 543 static void mmc_set_ios(struct mmc *mmc)
 544 {
 545         struct omap_hsmmc_data *priv_data = mmc->priv;
 546         struct hsmmc *mmc_base = priv_data->base_addr;
 547         unsigned int dsor = 0;
 548         ulong start;
 549
 550         /* configue bus width */
 551         switch (mmc->bus_width) {
 552         case 8:
 553                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 554                         &mmc_base->con);
 555                 break;
 556
 557         case 4:
 558                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 559                         &mmc_base->con);
 560                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 561                         &mmc_base->hctl);
 562                 break;
 563
 564         case 1:
 565         default:
 566                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 567                         &mmc_base->con);
 568                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 569                         &mmc_base->hctl);
 570                 break;
 571         }
 572
 573         /* configure clock with 96Mhz system clock.
 574          */
 575         if (mmc->clock != 0) {
 576                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 577                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 578                         dsor++;
 579         }
 580
 581         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 582                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 583
 584         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 585                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 586
 587         start = get_timer(0);
 588         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 589                 if (get_timer(start) > MAX_RETRY_MS)
 590                         break;
 591         }
 592         if ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 593                 printf("%s: timeout waiting for ics!\n", __func__);
 594                 return;
 595         }
 596         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 597 }
 598
 599 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 600                 int wp_gpio)
 601 {
 602         struct mmc *mmc;
 603         struct omap_hsmmc_data *priv_data;
 604         unsigned long base_addr;
 605
 606         switch (dev_index) {
 607         case 0:
 608                 base_addr = OMAP_HSMMC1_BASE;
 609                 break;
 610 #ifdef OMAP_HSMMC2_BASE
 611         case 1:
 612                 base_addr = OMAP_HSMMC2_BASE;
 613                 break;
 614 #endif
 615 #ifdef OMAP_HSMMC3_BASE
 616         case 2:
 617                 base_addr = OMAP_HSMMC3_BASE;
 618                 break;
 619 #endif
 620         default:
 621                 printf("Invalid MMC device index: %d\n", dev_index);
 622                 return 1;
 623         }
 624
 625         mmc = &hsmmc_dev[dev_index];
 626         priv_data = &hsmmc_dev_data[dev_index];
 627         priv_data->base_addr = (void *)base_addr;
 628
 629         sprintf(mmc->name, "OMAP SD/MMC");
 630         mmc->send_cmd = mmc_send_cmd;
 631         mmc->set_ios = mmc_set_ios;
 632         mmc->init = mmc_init_setup;
 633         mmc->priv = priv_data;
 634
 635         priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
 636         if (priv_data->cd_gpio != -1)
 637                 mmc->getcd = omap_mmc_getcd;
 638
 639         priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
 640         if (priv_data->wp_gpio != -1)
 641                 mmc->getwp = omap_mmc_getwp;
 642
 643         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 644         mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
 645                                 MMC_MODE_HC) & ~host_caps_mask;
 646
 647         mmc->f_min = 400000;
 648
 649         if (f_max != 0)
 650                 mmc->f_max = f_max;
 651         else {
 652                 if (mmc->host_caps & MMC_MODE_HS) {
 653                         if (mmc->host_caps & MMC_MODE_HS_52MHz)
 654                                 mmc->f_max = 52000000;
 655                         else
 656                                 mmc->f_max = 26000000;
 657                 } else
 658                         mmc->f_max = 20000000;
 659         }
 660
 661         mmc->b_max = 0;
 662
 663 #if defined(CONFIG_OMAP34XX)
 664         /*
 665          * Silicon revs 2.1 and older do not support multiblock transfers.
 666          */
 667         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 668                 mmc->b_max = 1;
 669 #endif
 670
 671         mmc_register(mmc);
 672
 673         return 0;
 674 }