drivers/mmc/omap_hsmmc.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Sukumar Ghorai <s-ghorai@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <config.h>
  26 #include <common.h>
  27 #include <mmc.h>
  28 #include <part.h>
  29 #include <i2c.h>
  30 #include <twl4030.h>
  31 #include <twl6030.h>
  32 #include <asm/io.h>
  33 #include <asm/arch/mmc_host_def.h>
  34 #include <asm/arch/sys_proto.h>
  35
  36 /* If we fail after 1 second wait, something is really bad */
  37 #define MAX_RETRY_MS    1000
  38
  39 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  40 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  41                         unsigned int siz);
  42 static struct mmc hsmmc_dev[2];
  43
  44 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  45 static void omap4_vmmc_pbias_config(struct mmc *mmc)
  46 {
  47         u32 value = 0;
  48         struct omap4_sys_ctrl_regs *const ctrl =
  49                 (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
  50
  51
  52         value = readl(&ctrl->control_pbiaslite);
  53         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
  54         writel(value, &ctrl->control_pbiaslite);
  55         /* set VMMC to 3V */
  56         twl6030_power_mmc_init();
  57         value = readl(&ctrl->control_pbiaslite);
  58         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
  59         writel(value, &ctrl->control_pbiaslite);
  60 }
  61 #endif
  62
  63 unsigned char mmc_board_init(struct mmc *mmc)
  64 {
  65 #if defined(CONFIG_TWL4030_POWER)
  66         twl4030_power_mmc_init();
  67 #endif
  68
  69 #if defined(CONFIG_OMAP34XX)
  70         t2_t *t2_base = (t2_t *)T2_BASE;
  71         struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  72
  73         writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
  74                 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
  75                 &t2_base->pbias_lite);
  76
  77         writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
  78                 &t2_base->devconf0);
  79
  80         writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
  81                 &t2_base->devconf1);
  82
  83         writel(readl(&prcm_base->fclken1_core) |
  84                 EN_MMC1 | EN_MMC2 | EN_MMC3,
  85                 &prcm_base->fclken1_core);
  86
  87         writel(readl(&prcm_base->iclken1_core) |
  88                 EN_MMC1 | EN_MMC2 | EN_MMC3,
  89                 &prcm_base->iclken1_core);
  90 #endif
  91
  92 #if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
  93         /* PBIAS config needed for MMC1 only */
  94         if (mmc->block_dev.dev == 0)
  95                 omap4_vmmc_pbias_config(mmc);
  96 #endif
  97
  98         return 0;
  99 }
 100
 101 void mmc_init_stream(struct hsmmc *mmc_base)
 102 {
 103         ulong start;
 104
 105         writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
 106
 107         writel(MMC_CMD0, &mmc_base->cmd);
 108         start = get_timer(0);
 109         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 110                 if (get_timer(0) - start > MAX_RETRY_MS) {
 111                         printf("%s: timedout waiting for cc!\n", __func__);
 112                         return;
 113                 }
 114         }
 115         writel(CC_MASK, &mmc_base->stat)
 116                 ;
 117         writel(MMC_CMD0, &mmc_base->cmd)
 118                 ;
 119         start = get_timer(0);
 120         while (!(readl(&mmc_base->stat) & CC_MASK)) {
 121                 if (get_timer(0) - start > MAX_RETRY_MS) {
 122                         printf("%s: timedout waiting for cc2!\n", __func__);
 123                         return;
 124                 }
 125         }
 126         writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
 127 }
 128
 129
 130 static int mmc_init_setup(struct mmc *mmc)
 131 {
 132         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 133         unsigned int reg_val;
 134         unsigned int dsor;
 135         ulong start;
 136
 137         mmc_board_init(mmc);
 138
 139         writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
 140                 &mmc_base->sysconfig);
 141         start = get_timer(0);
 142         while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
 143                 if (get_timer(0) - start > MAX_RETRY_MS) {
 144                         printf("%s: timedout waiting for cc2!\n", __func__);
 145                         return TIMEOUT;
 146                 }
 147         }
 148         writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
 149         start = get_timer(0);
 150         while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
 151                 if (get_timer(0) - start > MAX_RETRY_MS) {
 152                         printf("%s: timedout waiting for softresetall!\n",
 153                                 __func__);
 154                         return TIMEOUT;
 155                 }
 156         }
 157         writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
 158         writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
 159                 &mmc_base->capa);
 160
 161         reg_val = readl(&mmc_base->con) & RESERVED_MASK;
 162
 163         writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
 164                 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
 165                 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
 166
 167         dsor = 240;
 168         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 169                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 170         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 171                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 172         start = get_timer(0);
 173         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 174                 if (get_timer(0) - start > MAX_RETRY_MS) {
 175                         printf("%s: timedout waiting for ics!\n", __func__);
 176                         return TIMEOUT;
 177                 }
 178         }
 179         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 180
 181         writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
 182
 183         writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
 184                 IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
 185                 &mmc_base->ie);
 186
 187         mmc_init_stream(mmc_base);
 188
 189         return 0;
 190 }
 191
 192
 193 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 194                         struct mmc_data *data)
 195 {
 196         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 197         unsigned int flags, mmc_stat;
 198         ulong start;
 199
 200         start = get_timer(0);
 201         while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) {
 202                 if (get_timer(0) - start > MAX_RETRY_MS) {
 203                         printf("%s: timedout waiting for cmddis!\n", __func__);
 204                         return TIMEOUT;
 205                 }
 206         }
 207         writel(0xFFFFFFFF, &mmc_base->stat);
 208         start = get_timer(0);
 209         while (readl(&mmc_base->stat)) {
 210                 if (get_timer(0) - start > MAX_RETRY_MS) {
 211                         printf("%s: timedout waiting for stat!\n", __func__);
 212                         return TIMEOUT;
 213                 }
 214         }
 215         /*
 216          * CMDREG
 217          * CMDIDX[13:8] : Command index
 218          * DATAPRNT[5]  : Data Present Select
 219          * ENCMDIDX[4]  : Command Index Check Enable
 220          * ENCMDCRC[3]  : Command CRC Check Enable
 221          * RSPTYP[1:0]
 222          *      00 = No Response
 223          *      01 = Length 136
 224          *      10 = Length 48
 225          *      11 = Length 48 Check busy after response
 226          */
 227         /* Delay added before checking the status of frq change
 228          * retry not supported by mmc.c(core file)
 229          */
 230         if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
 231                 udelay(50000); /* wait 50 ms */
 232
 233         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 234                 flags = 0;
 235         else if (cmd->resp_type & MMC_RSP_136)
 236                 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
 237         else if (cmd->resp_type & MMC_RSP_BUSY)
 238                 flags = RSP_TYPE_LGHT48B;
 239         else
 240                 flags = RSP_TYPE_LGHT48;
 241
 242         /* enable default flags */
 243         flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
 244                         MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
 245
 246         if (cmd->resp_type & MMC_RSP_CRC)
 247                 flags |= CCCE_CHECK;
 248         if (cmd->resp_type & MMC_RSP_OPCODE)
 249                 flags |= CICE_CHECK;
 250
 251         if (data) {
 252                 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
 253                          (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
 254                         flags |= (MSBS_MULTIBLK | BCE_ENABLE);
 255                         data->blocksize = 512;
 256                         writel(data->blocksize | (data->blocks << 16),
 257                                                         &mmc_base->blk);
 258                 } else
 259                         writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
 260
 261                 if (data->flags & MMC_DATA_READ)
 262                         flags |= (DP_DATA | DDIR_READ);
 263                 else
 264                         flags |= (DP_DATA | DDIR_WRITE);
 265         }
 266
 267         writel(cmd->cmdarg, &mmc_base->arg);
 268         writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
 269
 270         start = get_timer(0);
 271         do {
 272                 mmc_stat = readl(&mmc_base->stat);
 273                 if (get_timer(0) - start > MAX_RETRY_MS) {
 274                         printf("%s : timeout: No status update\n", __func__);
 275                         return TIMEOUT;
 276                 }
 277         } while (!mmc_stat);
 278
 279         if ((mmc_stat & IE_CTO) != 0)
 280                 return TIMEOUT;
 281         else if ((mmc_stat & ERRI_MASK) != 0)
 282                 return -1;
 283
 284         if (mmc_stat & CC_MASK) {
 285                 writel(CC_MASK, &mmc_base->stat);
 286                 if (cmd->resp_type & MMC_RSP_PRESENT) {
 287                         if (cmd->resp_type & MMC_RSP_136) {
 288                                 /* response type 2 */
 289                                 cmd->response[3] = readl(&mmc_base->rsp10);
 290                                 cmd->response[2] = readl(&mmc_base->rsp32);
 291                                 cmd->response[1] = readl(&mmc_base->rsp54);
 292                                 cmd->response[0] = readl(&mmc_base->rsp76);
 293                         } else
 294                                 /* response types 1, 1b, 3, 4, 5, 6 */
 295                                 cmd->response[0] = readl(&mmc_base->rsp10);
 296                 }
 297         }
 298
 299         if (data && (data->flags & MMC_DATA_READ)) {
 300                 mmc_read_data(mmc_base, data->dest,
 301                                 data->blocksize * data->blocks);
 302         } else if (data && (data->flags & MMC_DATA_WRITE)) {
 303                 mmc_write_data(mmc_base, data->src,
 304                                 data->blocksize * data->blocks);
 305         }
 306         return 0;
 307 }
 308
 309 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
 310 {
 311         unsigned int *output_buf = (unsigned int *)buf;
 312         unsigned int mmc_stat;
 313         unsigned int count;
 314
 315         /*
 316          * Start Polled Read
 317          */
 318         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 319         count /= 4;
 320
 321         while (size) {
 322                 ulong start = get_timer(0);
 323                 do {
 324                         mmc_stat = readl(&mmc_base->stat);
 325                         if (get_timer(0) - start > MAX_RETRY_MS) {
 326                                 printf("%s: timedout waiting for status!\n",
 327                                                 __func__);
 328                                 return TIMEOUT;
 329                         }
 330                 } while (mmc_stat == 0);
 331
 332                 if ((mmc_stat & ERRI_MASK) != 0)
 333                         return 1;
 334
 335                 if (mmc_stat & BRR_MASK) {
 336                         unsigned int k;
 337
 338                         writel(readl(&mmc_base->stat) | BRR_MASK,
 339                                 &mmc_base->stat);
 340                         for (k = 0; k < count; k++) {
 341                                 *output_buf = readl(&mmc_base->data);
 342                                 output_buf++;
 343                         }
 344                         size -= (count*4);
 345                 }
 346
 347                 if (mmc_stat & BWR_MASK)
 348                         writel(readl(&mmc_base->stat) | BWR_MASK,
 349                                 &mmc_base->stat);
 350
 351                 if (mmc_stat & TC_MASK) {
 352                         writel(readl(&mmc_base->stat) | TC_MASK,
 353                                 &mmc_base->stat);
 354                         break;
 355                 }
 356         }
 357         return 0;
 358 }
 359
 360 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
 361                                 unsigned int size)
 362 {
 363         unsigned int *input_buf = (unsigned int *)buf;
 364         unsigned int mmc_stat;
 365         unsigned int count;
 366
 367         /*
 368          * Start Polled Read
 369          */
 370         count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
 371         count /= 4;
 372
 373         while (size) {
 374                 ulong start = get_timer(0);
 375                 do {
 376                         mmc_stat = readl(&mmc_base->stat);
 377                         if (get_timer(0) - start > MAX_RETRY_MS) {
 378                                 printf("%s: timedout waiting for status!\n",
 379                                                 __func__);
 380                                 return TIMEOUT;
 381                         }
 382                 } while (mmc_stat == 0);
 383
 384                 if ((mmc_stat & ERRI_MASK) != 0)
 385                         return 1;
 386
 387                 if (mmc_stat & BWR_MASK) {
 388                         unsigned int k;
 389
 390                         writel(readl(&mmc_base->stat) | BWR_MASK,
 391                                         &mmc_base->stat);
 392                         for (k = 0; k < count; k++) {
 393                                 writel(*input_buf, &mmc_base->data);
 394                                 input_buf++;
 395                         }
 396                         size -= (count*4);
 397                 }
 398
 399                 if (mmc_stat & BRR_MASK)
 400                         writel(readl(&mmc_base->stat) | BRR_MASK,
 401                                 &mmc_base->stat);
 402
 403                 if (mmc_stat & TC_MASK) {
 404                         writel(readl(&mmc_base->stat) | TC_MASK,
 405                                 &mmc_base->stat);
 406                         break;
 407                 }
 408         }
 409         return 0;
 410 }
 411
 412 static void mmc_set_ios(struct mmc *mmc)
 413 {
 414         struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
 415         unsigned int dsor = 0;
 416         ulong start;
 417
 418         /* configue bus width */
 419         switch (mmc->bus_width) {
 420         case 8:
 421                 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
 422                         &mmc_base->con);
 423                 break;
 424
 425         case 4:
 426                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 427                         &mmc_base->con);
 428                 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
 429                         &mmc_base->hctl);
 430                 break;
 431
 432         case 1:
 433         default:
 434                 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
 435                         &mmc_base->con);
 436                 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
 437                         &mmc_base->hctl);
 438                 break;
 439         }
 440
 441         /* configure clock with 96Mhz system clock.
 442          */
 443         if (mmc->clock != 0) {
 444                 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
 445                 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
 446                         dsor++;
 447         }
 448
 449         mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
 450                                 (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
 451
 452         mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
 453                                 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
 454
 455         start = get_timer(0);
 456         while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
 457                 if (get_timer(0) - start > MAX_RETRY_MS) {
 458                         printf("%s: timedout waiting for ics!\n", __func__);
 459                         return;
 460                 }
 461         }
 462         writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
 463 }
 464
 465 int omap_mmc_init(int dev_index)
 466 {
 467         struct mmc *mmc;
 468
 469         mmc = &hsmmc_dev[dev_index];
 470
 471         sprintf(mmc->name, "OMAP SD/MMC");
 472         mmc->send_cmd = mmc_send_cmd;
 473         mmc->set_ios = mmc_set_ios;
 474         mmc->init = mmc_init_setup;
 475
 476         switch (dev_index) {
 477         case 0:
 478                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
 479                 break;
 480 #ifdef OMAP_HSMMC2_BASE
 481         case 1:
 482                 mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
 483                 break;
 484 #endif
 485 #ifdef OMAP_HSMMC3_BASE
 486         case 2:
 487                 mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
 488                 break;
 489 #endif
 490         default:
 491                 mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
 492                 return 1;
 493         }
 494         mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 495         mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
 496                                 MMC_MODE_HC;
 497
 498         mmc->f_min = 400000;
 499         mmc->f_max = 52000000;
 500
 501         mmc->b_max = 0;
 502
 503 #if defined(CONFIG_OMAP34XX)
 504         /*
 505          * Silicon revs 2.1 and older do not support multiblock transfers.
 506          */
 507         if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
 508                 mmc->b_max = 1;
 509 #endif
 510
 511         mmc_register(mmc);
 512
 513         return 0;
 514 }