drivers/mtd/nand/am335x_spl_bch.c

   1 /*
   2  * (C) Copyright 2012
   3  * Konstantin Kozhevnikov, Cogent Embedded
   4  *
   5  * based on nand_spl_simple code
   6  *
   7  * (C) Copyright 2006-2008
   8  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <nand.h>
  15 #include <asm/io.h>
  16 #include <linux/mtd/nand_ecc.h>
  17
  18 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  19 nand_info_t nand_info[1];
  20 static struct nand_chip nand_chip;
  21
  22 #define ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / \
  23                                         CONFIG_SYS_NAND_ECCSIZE)
  24 #define ECCTOTAL        (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  25
  26
  27 /*
  28  * NAND command for large page NAND devices (2k)
  29  */
  30 static int nand_command(int block, int page, uint32_t offs,
  31         u8 cmd)
  32 {
  33         struct nand_chip *this = nand_info[0].priv;
  34         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  35         void (*hwctrl)(struct mtd_info *mtd, int cmd,
  36                         unsigned int ctrl) = this->cmd_ctrl;
  37
  38         while (!this->dev_ready(&nand_info[0]))
  39                 ;
  40
  41         /* Emulate NAND_CMD_READOOB */
  42         if (cmd == NAND_CMD_READOOB) {
  43                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
  44                 cmd = NAND_CMD_READ0;
  45         }
  46
  47         /* Begin command latch cycle */
  48         hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  49
  50         if (cmd == NAND_CMD_RESET) {
  51                 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  52                 while (!this->dev_ready(&nand_info[0]))
  53                         ;
  54                 return 0;
  55         }
  56
  57         /* Shift the offset from byte addressing to word addressing. */
  58         if (this->options & NAND_BUSWIDTH_16)
  59                 offs >>= 1;
  60
  61         /* Set ALE and clear CLE to start address cycle */
  62         /* Column address */
  63         hwctrl(&nand_info[0], offs & 0xff,
  64                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  65         hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  66         /* Row address */
  67         hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
  68         hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
  69                        NAND_CTRL_ALE); /* A[27:20] */
  70 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  71         /* One more address cycle for devices > 128MiB */
  72         hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
  73                        NAND_CTRL_ALE); /* A[31:28] */
  74 #endif
  75         hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  76
  77         if (cmd == NAND_CMD_READ0) {
  78                 /* Latch in address */
  79                 hwctrl(&nand_info[0], NAND_CMD_READSTART,
  80                            NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  81                 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  82
  83                 /*
  84                  * Wait a while for the data to be ready
  85                  */
  86                 while (!this->dev_ready(&nand_info[0]))
  87                         ;
  88         } else if (cmd == NAND_CMD_RNDOUT) {
  89                 hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
  90                                         NAND_CTRL_CHANGE);
  91                 hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  92         }
  93
  94         return 0;
  95 }
  96
  97 static int nand_is_bad_block(int block)
  98 {
  99         struct nand_chip *this = nand_info[0].priv;
 100
 101         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 102                 NAND_CMD_READOOB);
 103
 104         /*
 105          * Read one byte (or two if it's a 16 bit chip).
 106          */
 107         if (this->options & NAND_BUSWIDTH_16) {
 108                 if (readw(this->IO_ADDR_R) != 0xffff)
 109                         return 1;
 110         } else {
 111                 if (readb(this->IO_ADDR_R) != 0xff)
 112                         return 1;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int nand_read_page(int block, int page, void *dst)
 119 {
 120         struct nand_chip *this = nand_info[0].priv;
 121         u_char ecc_calc[ECCTOTAL];
 122         u_char ecc_code[ECCTOTAL];
 123         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
 124         int i;
 125         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 126         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 127         int eccsteps = ECCSTEPS;
 128         uint8_t *p = dst;
 129         uint32_t data_pos = 0;
 130         uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
 131         uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
 132
 133         nand_command(block, page, 0, NAND_CMD_READ0);
 134
 135         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 136                 this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
 137                 nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
 138
 139                 this->read_buf(&nand_info[0], p, eccsize);
 140
 141                 nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
 142
 143                 this->read_buf(&nand_info[0], oob, eccbytes);
 144                 this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
 145
 146                 data_pos += eccsize;
 147                 oob_pos += eccbytes;
 148                 oob += eccbytes;
 149         }
 150
 151         /* Pick the ECC bytes out of the oob data */
 152         for (i = 0; i < ECCTOTAL; i++)
 153                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 154
 155         eccsteps = ECCSTEPS;
 156         p = dst;
 157
 158         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 159                 /* No chance to do something with the possible error message
 160                  * from correct_data(). We just hope that all possible errors
 161                  * are corrected by this routine.
 162                  */
 163                 this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
 164         }
 165
 166         return 0;
 167 }
 168
 169 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 170 {
 171         unsigned int block, lastblock;
 172         unsigned int page;
 173
 174         /*
 175          * offs has to be aligned to a page address!
 176          */
 177         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 178         lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 179         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
 180
 181         while (block <= lastblock) {
 182                 if (!nand_is_bad_block(block)) {
 183                         /*
 184                          * Skip bad blocks
 185                          */
 186                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 187                                 nand_read_page(block, page, dst);
 188                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
 189                                 page++;
 190                         }
 191
 192                         page = 0;
 193                 } else {
 194                         lastblock++;
 195                 }
 196
 197                 block++;
 198         }
 199
 200         return 0;
 201 }
 202
 203 /* nand_init() - initialize data to make nand usable by SPL */
 204 void nand_init(void)
 205 {
 206         /*
 207          * Init board specific nand support
 208          */
 209         nand_info[0].priv = &nand_chip;
 210         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 211                 (void  __iomem *)CONFIG_SYS_NAND_BASE;
 212         board_nand_init(&nand_chip);
 213
 214         if (nand_chip.select_chip)
 215                 nand_chip.select_chip(&nand_info[0], 0);
 216
 217         /* NAND chip may require reset after power-on */
 218         nand_command(0, 0, 0, NAND_CMD_RESET);
 219 }
 220
 221 /* Unselect after operation */
 222 void nand_deselect(void)
 223 {
 224         if (nand_chip.select_chip)
 225                 nand_chip.select_chip(&nand_info[0], -1);
 226 }