drivers/mtd/nand/denali_spl.c

   1 /*
   2  * Copyright (C) 2014       Panasonic Corporation
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/unaligned.h>
  10 #include <linux/mtd/nand.h>
  11 #include "denali.h"
  12
  13 #define SPARE_ACCESS            0x41
  14 #define MAIN_ACCESS             0x42
  15 #define PIPELINE_ACCESS         0x2000
  16
  17 #define BANK(x) ((x) << 24)
  18
  19 static void __iomem *denali_flash_mem =
  20                         (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
  21 static void __iomem *denali_flash_reg =
  22                         (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
  23
  24 static const int flash_bank;
  25 static uint8_t page_buffer[NAND_MAX_PAGESIZE];
  26 static int page_size, oob_size, pages_per_block;
  27
  28 static void index_addr(uint32_t address, uint32_t data)
  29 {
  30         writel(address, denali_flash_mem + INDEX_CTRL_REG);
  31         writel(data, denali_flash_mem + INDEX_DATA_REG);
  32 }
  33
  34 static int wait_for_irq(uint32_t irq_mask)
  35 {
  36         unsigned long timeout = 1000000;
  37         uint32_t intr_status;
  38
  39         do {
  40                 intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
  41
  42                 if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
  43                         debug("Uncorrected ECC detected\n");
  44                         return -EIO;
  45                 }
  46
  47                 if (intr_status & irq_mask)
  48                         break;
  49
  50                 udelay(1);
  51                 timeout--;
  52         } while (timeout);
  53
  54         if (!timeout) {
  55                 debug("Timeout with interrupt status %08x\n", intr_status);
  56                 return -EIO;
  57         }
  58
  59         return 0;
  60 }
  61
  62 static void read_data_from_flash_mem(uint8_t *buf, int len)
  63 {
  64         int i;
  65         uint32_t *buf32;
  66
  67         /* transfer the data from the flash */
  68         buf32 = (uint32_t *)buf;
  69
  70         /*
  71          * Let's take care of unaligned access although it rarely happens.
  72          * Avoid put_unaligned() for the normal use cases since it leads to
  73          * a bit performance regression.
  74          */
  75         if ((unsigned long)buf32 % 4) {
  76                 for (i = 0; i < len / 4; i++)
  77                         put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG),
  78                                       buf32++);
  79         } else {
  80                 for (i = 0; i < len / 4; i++)
  81                         *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
  82         }
  83
  84         if (len % 4) {
  85                 u32 tmp;
  86
  87                 tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG));
  88                 buf = (uint8_t *)buf32;
  89                 for (i = 0; i < len % 4; i++) {
  90                         *buf++ = tmp;
  91                         tmp >>= 8;
  92                 }
  93         }
  94 }
  95
  96 int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
  97 {
  98         uint32_t addr, cmd;
  99         static uint32_t page_count = 1;
 100
 101         writel(ecc_en, denali_flash_reg + ECC_ENABLE);
 102
 103         /* clear all bits of intr_status. */
 104         writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank));
 105
 106         addr = BANK(flash_bank) | page;
 107
 108         /* setup the acccess type */
 109         cmd = MODE_10 | addr;
 110         index_addr(cmd, access_type);
 111
 112         /* setup the pipeline command */
 113         index_addr(cmd, PIPELINE_ACCESS | page_count);
 114
 115         cmd = MODE_01 | addr;
 116         writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
 117
 118         return wait_for_irq(INTR_STATUS__LOAD_COMP);
 119 }
 120
 121 static int nand_read_oob(void *buf, int page)
 122 {
 123         int ret;
 124
 125         ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS);
 126         if (ret < 0)
 127                 return ret;
 128
 129         read_data_from_flash_mem(buf, oob_size);
 130
 131         return 0;
 132 }
 133
 134 static int nand_read_page(void *buf, int page)
 135 {
 136         int ret;
 137
 138         ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS);
 139         if (ret < 0)
 140                 return ret;
 141
 142         read_data_from_flash_mem(buf, page_size);
 143
 144         return 0;
 145 }
 146
 147 static int nand_block_isbad(int block)
 148 {
 149         int ret;
 150
 151         ret = nand_read_oob(page_buffer, block * pages_per_block);
 152         if (ret < 0)
 153                 return ret;
 154
 155         return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff;
 156 }
 157
 158 /* nand_init() - initialize data to make nand usable by SPL */
 159 void nand_init(void)
 160 {
 161         /* access to main area */
 162         writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
 163
 164         /*
 165          * These registers are expected to be already set by the hardware
 166          * or earlier boot code.  So we read these values out.
 167          */
 168         page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
 169         oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
 170         pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
 171 }
 172
 173 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 174 {
 175         int block, page, column, readlen;
 176         int ret;
 177         int force_bad_block_check = 1;
 178
 179         page = offs / page_size;
 180         column = offs % page_size;
 181
 182         block = page / pages_per_block;
 183         page = page % pages_per_block;
 184
 185         while (size) {
 186                 if (force_bad_block_check || page == 0) {
 187                         ret = nand_block_isbad(block);
 188                         if (ret < 0)
 189                                 return ret;
 190
 191                         if (ret) {
 192                                 block++;
 193                                 continue;
 194                         }
 195                 }
 196
 197                 force_bad_block_check = 0;
 198
 199                 if (unlikely(column || size < page_size)) {
 200                         /* Partial page read */
 201                         ret = nand_read_page(page_buffer,
 202                                              block * pages_per_block + page);
 203                         if (ret < 0)
 204                                 return ret;
 205
 206                         readlen = min(page_size - column, (int)size);
 207                         memcpy(dst, page_buffer, readlen);
 208
 209                         column = 0;
 210                 } else {
 211                         ret = nand_read_page(dst,
 212                                              block * pages_per_block + page);
 213                         if (ret < 0)
 214                                 return ret;
 215
 216                         readlen = page_size;
 217                 }
 218
 219                 size -= readlen;
 220                 dst += readlen;
 221                 page++;
 222                 if (page == pages_per_block) {
 223                         block++;
 224                         page = 0;
 225                 }
 226         }
 227
 228         return 0;
 229 }
 230
 231 void nand_deselect(void) {}