drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <nand.h>
  11 #include <linux/err.h>
  12 #include <asm/io.h>
  13 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
  14         defined(CONFIG_MX51) || defined(CONFIG_MX53)
  15 #include <asm/arch/imx-regs.h>
  16 #endif
  17 #include "mxc_nand.h"
  18
  19 #define DRIVER_NAME "mxc_nand"
  20
  21 struct mxc_nand_host {
  22         struct mtd_info                 mtd;
  23         struct nand_chip                *nand;
  24
  25         struct mxc_nand_regs __iomem    *regs;
  26 #ifdef MXC_NFC_V3_2
  27         struct mxc_nand_ip_regs __iomem *ip_regs;
  28 #endif
  29         int                             spare_only;
  30         int                             status_request;
  31         int                             pagesize_2k;
  32         int                             clk_act;
  33         uint16_t                        col_addr;
  34         unsigned int                    page_addr;
  35 };
  36
  37 static struct mxc_nand_host mxc_host;
  38 static struct mxc_nand_host *host = &mxc_host;
  39
  40 /* Define delays in microsec for NAND device operations */
  41 #define TROP_US_DELAY   2000
  42 /* Macros to get byte and bit positions of ECC */
  43 #define COLPOS(x)  ((x) >> 3)
  44 #define BITPOS(x) ((x) & 0xf)
  45
  46 /* Define single bit Error positions in Main & Spare area */
  47 #define MAIN_SINGLEBIT_ERROR 0x4
  48 #define SPARE_SINGLEBIT_ERROR 0x1
  49
  50 /* OOB placement block for use with hardware ecc generation */
  51 #if defined(MXC_NFC_V1)
  52 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  53 static struct nand_ecclayout nand_hw_eccoob = {
  54         .eccbytes = 5,
  55         .eccpos = {6, 7, 8, 9, 10},
  56         .oobfree = { {0, 5}, {11, 5}, }
  57 };
  58 #else
  59 static struct nand_ecclayout nand_hw_eccoob2k = {
  60         .eccbytes = 20,
  61         .eccpos = {
  62                 6, 7, 8, 9, 10,
  63                 22, 23, 24, 25, 26,
  64                 38, 39, 40, 41, 42,
  65                 54, 55, 56, 57, 58,
  66         },
  67         .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  68 };
  69 #endif
  70 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  71 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  72 static struct nand_ecclayout nand_hw_eccoob = {
  73         .eccbytes = 9,
  74         .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  75         .oobfree = { {2, 5} }
  76 };
  77 #else
  78 static struct nand_ecclayout nand_hw_eccoob2k = {
  79         .eccbytes = 36,
  80         .eccpos = {
  81                 7, 8, 9, 10, 11, 12, 13, 14, 15,
  82                 23, 24, 25, 26, 27, 28, 29, 30, 31,
  83                 39, 40, 41, 42, 43, 44, 45, 46, 47,
  84                 55, 56, 57, 58, 59, 60, 61, 62, 63,
  85         },
  86         .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  87 };
  88 #endif
  89 #endif
  90
  91 static int is_16bit_nand(void)
  92 {
  93 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  94         return 1;
  95 #else
  96         return 0;
  97 #endif
  98 }
  99
 100 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
 101 {
 102         uint32_t *d = dest;
 103
 104         size >>= 2;
 105         while (size--)
 106                 __raw_writel(__raw_readl(source++), d++);
 107         return dest;
 108 }
 109
 110 /*
 111  * This function polls the NANDFC to wait for the basic operation to
 112  * complete by checking the INT bit.
 113  */
 114 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 115                                 uint16_t param)
 116 {
 117         uint32_t tmp;
 118
 119         while (max_retries-- > 0) {
 120 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 121                 tmp = readnfc(&host->regs->config2);
 122                 if (tmp & NFC_V1_V2_CONFIG2_INT) {
 123                         tmp &= ~NFC_V1_V2_CONFIG2_INT;
 124                         writenfc(tmp, &host->regs->config2);
 125 #elif defined(MXC_NFC_V3_2)
 126                 tmp = readnfc(&host->ip_regs->ipc);
 127                 if (tmp & NFC_V3_IPC_INT) {
 128                         tmp &= ~NFC_V3_IPC_INT;
 129                         writenfc(tmp, &host->ip_regs->ipc);
 130 #endif
 131                         break;
 132                 }
 133                 udelay(1);
 134         }
 135         if (max_retries < 0) {
 136                 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
 137                                 __func__, param);
 138         }
 139 }
 140
 141 /*
 142  * This function issues the specified command to the NAND device and
 143  * waits for completion.
 144  */
 145 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
 146 {
 147         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
 148
 149         writenfc(cmd, &host->regs->flash_cmd);
 150         writenfc(NFC_CMD, &host->regs->operation);
 151
 152         /* Wait for operation to complete */
 153         wait_op_done(host, TROP_US_DELAY, cmd);
 154 }
 155
 156 /*
 157  * This function sends an address (or partial address) to the
 158  * NAND device. The address is used to select the source/destination for
 159  * a NAND command.
 160  */
 161 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 162 {
 163         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
 164
 165         writenfc(addr, &host->regs->flash_addr);
 166         writenfc(NFC_ADDR, &host->regs->operation);
 167
 168         /* Wait for operation to complete */
 169         wait_op_done(host, TROP_US_DELAY, addr);
 170 }
 171
 172 /*
 173  * This function requests the NANDFC to initiate the transfer
 174  * of data currently in the NANDFC RAM buffer to the NAND device.
 175  */
 176 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 177                         int spare_only)
 178 {
 179         if (spare_only)
 180                 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
 181
 182         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 183                 int i;
 184                 /*
 185                  *  The controller copies the 64 bytes of spare data from
 186                  *  the first 16 bytes of each of the 4 64 byte spare buffers.
 187                  *  Copy the contiguous data starting in spare_area[0] to
 188                  *  the four spare area buffers.
 189                  */
 190                 for (i = 1; i < 4; i++) {
 191                         void __iomem *src = &host->regs->spare_area[0][i * 16];
 192                         void __iomem *dst = &host->regs->spare_area[i][0];
 193
 194                         mxc_nand_memcpy32(dst, src, 16);
 195                 }
 196         }
 197
 198 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 199         writenfc(buf_id, &host->regs->buf_addr);
 200 #elif defined(MXC_NFC_V3_2)
 201         uint32_t tmp = readnfc(&host->regs->config1);
 202         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 203         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 204         writenfc(tmp, &host->regs->config1);
 205 #endif
 206
 207         /* Configure spare or page+spare access */
 208         if (!host->pagesize_2k) {
 209                 uint32_t config1 = readnfc(&host->regs->config1);
 210                 if (spare_only)
 211                         config1 |= NFC_CONFIG1_SP_EN;
 212                 else
 213                         config1 &= ~NFC_CONFIG1_SP_EN;
 214                 writenfc(config1, &host->regs->config1);
 215         }
 216
 217         writenfc(NFC_INPUT, &host->regs->operation);
 218
 219         /* Wait for operation to complete */
 220         wait_op_done(host, TROP_US_DELAY, spare_only);
 221 }
 222
 223 /*
 224  * Requests NANDFC to initiate the transfer of data from the
 225  * NAND device into in the NANDFC ram buffer.
 226  */
 227 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 228                 int spare_only)
 229 {
 230         MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
 231
 232 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 233         writenfc(buf_id, &host->regs->buf_addr);
 234 #elif defined(MXC_NFC_V3_2)
 235         uint32_t tmp = readnfc(&host->regs->config1);
 236         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 237         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 238         writenfc(tmp, &host->regs->config1);
 239 #endif
 240
 241         /* Configure spare or page+spare access */
 242         if (!host->pagesize_2k) {
 243                 uint32_t config1 = readnfc(&host->regs->config1);
 244                 if (spare_only)
 245                         config1 |= NFC_CONFIG1_SP_EN;
 246                 else
 247                         config1 &= ~NFC_CONFIG1_SP_EN;
 248                 writenfc(config1, &host->regs->config1);
 249         }
 250
 251         writenfc(NFC_OUTPUT, &host->regs->operation);
 252
 253         /* Wait for operation to complete */
 254         wait_op_done(host, TROP_US_DELAY, spare_only);
 255
 256         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 257                 int i;
 258
 259                 /*
 260                  *  The controller copies the 64 bytes of spare data to
 261                  *  the first 16 bytes of each of the 4 spare buffers.
 262                  *  Make the data contiguous starting in spare_area[0].
 263                  */
 264                 for (i = 1; i < 4; i++) {
 265                         void __iomem *src = &host->regs->spare_area[i][0];
 266                         void __iomem *dst = &host->regs->spare_area[0][i * 16];
 267
 268                         mxc_nand_memcpy32(dst, src, 16);
 269                 }
 270         }
 271 }
 272
 273 /* Request the NANDFC to perform a read of the NAND device ID. */
 274 static void send_read_id(struct mxc_nand_host *host)
 275 {
 276         uint32_t tmp;
 277
 278 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 279         /* NANDFC buffer 0 is used for device ID output */
 280         writenfc(0x0, &host->regs->buf_addr);
 281 #elif defined(MXC_NFC_V3_2)
 282         tmp = readnfc(&host->regs->config1);
 283         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 284         writenfc(tmp, &host->regs->config1);
 285 #endif
 286
 287         /* Read ID into main buffer */
 288         tmp = readnfc(&host->regs->config1);
 289         tmp &= ~NFC_CONFIG1_SP_EN;
 290         writenfc(tmp, &host->regs->config1);
 291
 292         writenfc(NFC_ID, &host->regs->operation);
 293
 294         /* Wait for operation to complete */
 295         wait_op_done(host, TROP_US_DELAY, 0);
 296 }
 297
 298 /*
 299  * This function requests the NANDFC to perform a read of the
 300  * NAND device status and returns the current status.
 301  */
 302 static uint16_t get_dev_status(struct mxc_nand_host *host)
 303 {
 304 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 305         void __iomem *main_buf = host->regs->main_area[1];
 306         uint32_t store;
 307 #endif
 308         uint32_t ret, tmp;
 309         /* Issue status request to NAND device */
 310
 311 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 312         /* store the main area1 first word, later do recovery */
 313         store = readl(main_buf);
 314         /* NANDFC buffer 1 is used for device status */
 315         writenfc(1, &host->regs->buf_addr);
 316 #endif
 317
 318         /* Read status into main buffer */
 319         tmp = readnfc(&host->regs->config1);
 320         tmp &= ~NFC_CONFIG1_SP_EN;
 321         writenfc(tmp, &host->regs->config1);
 322
 323         writenfc(NFC_STATUS, &host->regs->operation);
 324
 325         /* Wait for operation to complete */
 326         wait_op_done(host, TROP_US_DELAY, 0);
 327
 328 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 329         /*
 330          *  Status is placed in first word of main buffer
 331          * get status, then recovery area 1 data
 332          */
 333         ret = readw(main_buf);
 334         writel(store, main_buf);
 335 #elif defined(MXC_NFC_V3_2)
 336         ret = readnfc(&host->regs->config1) >> 16;
 337 #endif
 338
 339         return ret;
 340 }
 341
 342 /* This function is used by upper layer to checks if device is ready */
 343 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 344 {
 345         /*
 346          * NFC handles R/B internally. Therefore, this function
 347          * always returns status as ready.
 348          */
 349         return 1;
 350 }
 351
 352 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 353 {
 354         struct nand_chip *nand_chip = mtd->priv;
 355         struct mxc_nand_host *host = nand_chip->priv;
 356 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 357         uint16_t tmp = readnfc(&host->regs->config1);
 358
 359         if (on)
 360                 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
 361         else
 362                 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 363         writenfc(tmp, &host->regs->config1);
 364 #elif defined(MXC_NFC_V3_2)
 365         uint32_t tmp = readnfc(&host->ip_regs->config2);
 366
 367         if (on)
 368                 tmp |= NFC_V3_CONFIG2_ECC_EN;
 369         else
 370                 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
 371         writenfc(tmp, &host->ip_regs->config2);
 372 #endif
 373 }
 374
 375 #ifdef CONFIG_MXC_NAND_HWECC
 376 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 377 {
 378         /*
 379          * If HW ECC is enabled, we turn it on during init. There is
 380          * no need to enable again here.
 381          */
 382 }
 383
 384 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
 385 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 386                                       struct nand_chip *chip,
 387                                       int page)
 388 {
 389         struct mxc_nand_host *host = chip->priv;
 390         uint8_t *buf = chip->oob_poi;
 391         int length = mtd->oobsize;
 392         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 393         uint8_t *bufpoi = buf;
 394         int i, toread;
 395
 396         MTDDEBUG(MTD_DEBUG_LEVEL0,
 397                         "%s: Reading OOB area of page %u to oob %p\n",
 398                          __func__, page, buf);
 399
 400         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 401         for (i = 0; i < chip->ecc.steps; i++) {
 402                 toread = min_t(int, length, chip->ecc.prepad);
 403                 if (toread) {
 404                         chip->read_buf(mtd, bufpoi, toread);
 405                         bufpoi += toread;
 406                         length -= toread;
 407                 }
 408                 bufpoi += chip->ecc.bytes;
 409                 host->col_addr += chip->ecc.bytes;
 410                 length -= chip->ecc.bytes;
 411
 412                 toread = min_t(int, length, chip->ecc.postpad);
 413                 if (toread) {
 414                         chip->read_buf(mtd, bufpoi, toread);
 415                         bufpoi += toread;
 416                         length -= toread;
 417                 }
 418         }
 419         if (length > 0)
 420                 chip->read_buf(mtd, bufpoi, length);
 421
 422         _mxc_nand_enable_hwecc(mtd, 0);
 423         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 424                         mtd->writesize + chip->ecc.prepad, page);
 425         bufpoi = buf + chip->ecc.prepad;
 426         length = mtd->oobsize - chip->ecc.prepad;
 427         for (i = 0; i < chip->ecc.steps; i++) {
 428                 toread = min_t(int, length, chip->ecc.bytes);
 429                 chip->read_buf(mtd, bufpoi, toread);
 430                 bufpoi += eccpitch;
 431                 length -= eccpitch;
 432                 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
 433         }
 434         _mxc_nand_enable_hwecc(mtd, 1);
 435         return 1;
 436 }
 437
 438 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 439                                            struct nand_chip *chip,
 440                                            uint8_t *buf,
 441                                            int oob_required,
 442                                            int page)
 443 {
 444         struct mxc_nand_host *host = chip->priv;
 445         int eccsize = chip->ecc.size;
 446         int eccbytes = chip->ecc.bytes;
 447         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 448         uint8_t *oob = chip->oob_poi;
 449         int steps, size;
 450         int n;
 451
 452         _mxc_nand_enable_hwecc(mtd, 0);
 453         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 454
 455         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 456                 host->col_addr = n * eccsize;
 457                 chip->read_buf(mtd, buf, eccsize);
 458                 buf += eccsize;
 459
 460                 host->col_addr = mtd->writesize + n * eccpitch;
 461                 if (chip->ecc.prepad) {
 462                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 463                         oob += chip->ecc.prepad;
 464                 }
 465
 466                 chip->read_buf(mtd, oob, eccbytes);
 467                 oob += eccbytes;
 468
 469                 if (chip->ecc.postpad) {
 470                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 471                         oob += chip->ecc.postpad;
 472                 }
 473         }
 474
 475         size = mtd->oobsize - (oob - chip->oob_poi);
 476         if (size)
 477                 chip->read_buf(mtd, oob, size);
 478         _mxc_nand_enable_hwecc(mtd, 1);
 479
 480         return 0;
 481 }
 482
 483 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 484                                        struct nand_chip *chip,
 485                                        uint8_t *buf,
 486                                        int oob_required,
 487                                        int page)
 488 {
 489         struct mxc_nand_host *host = chip->priv;
 490         int n, eccsize = chip->ecc.size;
 491         int eccbytes = chip->ecc.bytes;
 492         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 493         int eccsteps = chip->ecc.steps;
 494         uint8_t *p = buf;
 495         uint8_t *oob = chip->oob_poi;
 496
 497         MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
 498               page, buf, oob);
 499
 500         /* first read the data area and the available portion of OOB */
 501         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 502                 int stat;
 503
 504                 host->col_addr = n * eccsize;
 505
 506                 chip->read_buf(mtd, p, eccsize);
 507
 508                 host->col_addr = mtd->writesize + n * eccpitch;
 509
 510                 if (chip->ecc.prepad) {
 511                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 512                         oob += chip->ecc.prepad;
 513                 }
 514
 515                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 516
 517                 if (stat < 0)
 518                         mtd->ecc_stats.failed++;
 519                 else
 520                         mtd->ecc_stats.corrected += stat;
 521                 oob += eccbytes;
 522
 523                 if (chip->ecc.postpad) {
 524                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 525                         oob += chip->ecc.postpad;
 526                 }
 527         }
 528
 529         /* Calculate remaining oob bytes */
 530         n = mtd->oobsize - (oob - chip->oob_poi);
 531         if (n)
 532                 chip->read_buf(mtd, oob, n);
 533
 534         /* Then switch ECC off and read the OOB area to get the ECC code */
 535         _mxc_nand_enable_hwecc(mtd, 0);
 536         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 537         eccsteps = chip->ecc.steps;
 538         oob = chip->oob_poi + chip->ecc.prepad;
 539         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 540                 host->col_addr = mtd->writesize +
 541                                  n * eccpitch +
 542                                  chip->ecc.prepad;
 543                 chip->read_buf(mtd, oob, eccbytes);
 544                 oob += eccbytes + chip->ecc.postpad;
 545         }
 546         _mxc_nand_enable_hwecc(mtd, 1);
 547         return 0;
 548 }
 549
 550 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 551                                        struct nand_chip *chip, int page)
 552 {
 553         struct mxc_nand_host *host = chip->priv;
 554         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 555         int length = mtd->oobsize;
 556         int i, len, status, steps = chip->ecc.steps;
 557         const uint8_t *bufpoi = chip->oob_poi;
 558
 559         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 560         for (i = 0; i < steps; i++) {
 561                 len = min_t(int, length, eccpitch);
 562
 563                 chip->write_buf(mtd, bufpoi, len);
 564                 bufpoi += len;
 565                 length -= len;
 566                 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
 567         }
 568         if (length > 0)
 569                 chip->write_buf(mtd, bufpoi, length);
 570
 571         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 572         status = chip->waitfunc(mtd, chip);
 573         return status & NAND_STATUS_FAIL ? -EIO : 0;
 574 }
 575
 576 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 577                                              struct nand_chip *chip,
 578                                              const uint8_t *buf,
 579                                              int oob_required)
 580 {
 581         struct mxc_nand_host *host = chip->priv;
 582         int eccsize = chip->ecc.size;
 583         int eccbytes = chip->ecc.bytes;
 584         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 585         uint8_t *oob = chip->oob_poi;
 586         int steps, size;
 587         int n;
 588
 589         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 590                 host->col_addr = n * eccsize;
 591                 chip->write_buf(mtd, buf, eccsize);
 592                 buf += eccsize;
 593
 594                 host->col_addr = mtd->writesize + n * eccpitch;
 595
 596                 if (chip->ecc.prepad) {
 597                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 598                         oob += chip->ecc.prepad;
 599                 }
 600
 601                 host->col_addr += eccbytes;
 602                 oob += eccbytes;
 603
 604                 if (chip->ecc.postpad) {
 605                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 606                         oob += chip->ecc.postpad;
 607                 }
 608         }
 609
 610         size = mtd->oobsize - (oob - chip->oob_poi);
 611         if (size)
 612                 chip->write_buf(mtd, oob, size);
 613         return 0;
 614 }
 615
 616 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 617                                          struct nand_chip *chip,
 618                                          const uint8_t *buf,
 619                                          int oob_required)
 620 {
 621         struct mxc_nand_host *host = chip->priv;
 622         int i, n, eccsize = chip->ecc.size;
 623         int eccbytes = chip->ecc.bytes;
 624         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 625         int eccsteps = chip->ecc.steps;
 626         const uint8_t *p = buf;
 627         uint8_t *oob = chip->oob_poi;
 628
 629         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 630
 631         for (i = n = 0;
 632              eccsteps;
 633              n++, eccsteps--, i += eccbytes, p += eccsize) {
 634                 host->col_addr = n * eccsize;
 635
 636                 chip->write_buf(mtd, p, eccsize);
 637
 638                 host->col_addr = mtd->writesize + n * eccpitch;
 639
 640                 if (chip->ecc.prepad) {
 641                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 642                         oob += chip->ecc.prepad;
 643                 }
 644
 645                 chip->write_buf(mtd, oob, eccbytes);
 646                 oob += eccbytes;
 647
 648                 if (chip->ecc.postpad) {
 649                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 650                         oob += chip->ecc.postpad;
 651                 }
 652         }
 653
 654         /* Calculate remaining oob bytes */
 655         i = mtd->oobsize - (oob - chip->oob_poi);
 656         if (i)
 657                 chip->write_buf(mtd, oob, i);
 658         return 0;
 659 }
 660
 661 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 662                                  u_char *read_ecc, u_char *calc_ecc)
 663 {
 664         struct nand_chip *nand_chip = mtd->priv;
 665         struct mxc_nand_host *host = nand_chip->priv;
 666         uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 667         int subpages = mtd->writesize / nand_chip->subpagesize;
 668         int pg2blk_shift = nand_chip->phys_erase_shift -
 669                            nand_chip->page_shift;
 670
 671         do {
 672                 if ((ecc_status & 0xf) > 4) {
 673                         static int last_bad = -1;
 674
 675                         if (last_bad != host->page_addr >> pg2blk_shift) {
 676                                 last_bad = host->page_addr >> pg2blk_shift;
 677                                 printk(KERN_DEBUG
 678                                        "MXC_NAND: HWECC uncorrectable ECC error"
 679                                        " in block %u page %u subpage %d\n",
 680                                        last_bad, host->page_addr,
 681                                        mtd->writesize / nand_chip->subpagesize
 682                                             - subpages);
 683                         }
 684                         return -1;
 685                 }
 686                 ecc_status >>= 4;
 687                 subpages--;
 688         } while (subpages > 0);
 689
 690         return 0;
 691 }
 692 #else
 693 #define mxc_nand_read_page_syndrome NULL
 694 #define mxc_nand_read_page_raw_syndrome NULL
 695 #define mxc_nand_read_oob_syndrome NULL
 696 #define mxc_nand_write_page_syndrome NULL
 697 #define mxc_nand_write_page_raw_syndrome NULL
 698 #define mxc_nand_write_oob_syndrome NULL
 699
 700 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 701                                  u_char *read_ecc, u_char *calc_ecc)
 702 {
 703         struct nand_chip *nand_chip = mtd->priv;
 704         struct mxc_nand_host *host = nand_chip->priv;
 705
 706         /*
 707          * 1-Bit errors are automatically corrected in HW.  No need for
 708          * additional correction.  2-Bit errors cannot be corrected by
 709          * HW ECC, so we need to return failure
 710          */
 711         uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
 712
 713         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 714                 MTDDEBUG(MTD_DEBUG_LEVEL0,
 715                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 716                 return -1;
 717         }
 718
 719         return 0;
 720 }
 721 #endif
 722
 723 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 724                                   u_char *ecc_code)
 725 {
 726         return 0;
 727 }
 728 #endif
 729
 730 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 731 {
 732         struct nand_chip *nand_chip = mtd->priv;
 733         struct mxc_nand_host *host = nand_chip->priv;
 734         uint8_t ret = 0;
 735         uint16_t col;
 736         uint16_t __iomem *main_buf =
 737                 (uint16_t __iomem *)host->regs->main_area[0];
 738         uint16_t __iomem *spare_buf =
 739                 (uint16_t __iomem *)host->regs->spare_area[0];
 740         union {
 741                 uint16_t word;
 742                 uint8_t bytes[2];
 743         } nfc_word;
 744
 745         /* Check for status request */
 746         if (host->status_request)
 747                 return get_dev_status(host) & 0xFF;
 748
 749         /* Get column for 16-bit access */
 750         col = host->col_addr >> 1;
 751
 752         /* If we are accessing the spare region */
 753         if (host->spare_only)
 754                 nfc_word.word = readw(&spare_buf[col]);
 755         else
 756                 nfc_word.word = readw(&main_buf[col]);
 757
 758         /* Pick upper/lower byte of word from RAM buffer */
 759         ret = nfc_word.bytes[host->col_addr & 0x1];
 760
 761         /* Update saved column address */
 762         if (nand_chip->options & NAND_BUSWIDTH_16)
 763                 host->col_addr += 2;
 764         else
 765                 host->col_addr++;
 766
 767         return ret;
 768 }
 769
 770 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 771 {
 772         struct nand_chip *nand_chip = mtd->priv;
 773         struct mxc_nand_host *host = nand_chip->priv;
 774         uint16_t col, ret;
 775         uint16_t __iomem *p;
 776
 777         MTDDEBUG(MTD_DEBUG_LEVEL3,
 778               "mxc_nand_read_word(col = %d)\n", host->col_addr);
 779
 780         col = host->col_addr;
 781         /* Adjust saved column address */
 782         if (col < mtd->writesize && host->spare_only)
 783                 col += mtd->writesize;
 784
 785         if (col < mtd->writesize) {
 786                 p = (uint16_t __iomem *)(host->regs->main_area[0] +
 787                                 (col >> 1));
 788         } else {
 789                 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
 790                                 ((col - mtd->writesize) >> 1));
 791         }
 792
 793         if (col & 1) {
 794                 union {
 795                         uint16_t word;
 796                         uint8_t bytes[2];
 797                 } nfc_word[3];
 798
 799                 nfc_word[0].word = readw(p);
 800                 nfc_word[1].word = readw(p + 1);
 801
 802                 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
 803                 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
 804
 805                 ret = nfc_word[2].word;
 806         } else {
 807                 ret = readw(p);
 808         }
 809
 810         /* Update saved column address */
 811         host->col_addr = col + 2;
 812
 813         return ret;
 814 }
 815
 816 /*
 817  * Write data of length len to buffer buf. The data to be
 818  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 819  * Operation by the NFC, the data is written to NAND Flash
 820  */
 821 static void mxc_nand_write_buf(struct mtd_info *mtd,
 822                                 const u_char *buf, int len)
 823 {
 824         struct nand_chip *nand_chip = mtd->priv;
 825         struct mxc_nand_host *host = nand_chip->priv;
 826         int n, col, i = 0;
 827
 828         MTDDEBUG(MTD_DEBUG_LEVEL3,
 829               "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 830               len);
 831
 832         col = host->col_addr;
 833
 834         /* Adjust saved column address */
 835         if (col < mtd->writesize && host->spare_only)
 836                 col += mtd->writesize;
 837
 838         n = mtd->writesize + mtd->oobsize - col;
 839         n = min(len, n);
 840
 841         MTDDEBUG(MTD_DEBUG_LEVEL3,
 842               "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 843
 844         while (n > 0) {
 845                 void __iomem *p;
 846
 847                 if (col < mtd->writesize) {
 848                         p = host->regs->main_area[0] + (col & ~3);
 849                 } else {
 850                         p = host->regs->spare_area[0] -
 851                                                 mtd->writesize + (col & ~3);
 852                 }
 853
 854                 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
 855                       __LINE__, p);
 856
 857                 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
 858                         union {
 859                                 uint32_t word;
 860                                 uint8_t bytes[4];
 861                         } nfc_word;
 862
 863                         nfc_word.word = readl(p);
 864                         nfc_word.bytes[col & 3] = buf[i++];
 865                         n--;
 866                         col++;
 867
 868                         writel(nfc_word.word, p);
 869                 } else {
 870                         int m = mtd->writesize - col;
 871
 872                         if (col >= mtd->writesize)
 873                                 m += mtd->oobsize;
 874
 875                         m = min(n, m) & ~3;
 876
 877                         MTDDEBUG(MTD_DEBUG_LEVEL3,
 878                               "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 879                               __func__,  __LINE__, n, m, i, col);
 880
 881                         mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
 882                         col += m;
 883                         i += m;
 884                         n -= m;
 885                 }
 886         }
 887         /* Update saved column address */
 888         host->col_addr = col;
 889 }
 890
 891 /*
 892  * Read the data buffer from the NAND Flash. To read the data from NAND
 893  * Flash first the data output cycle is initiated by the NFC, which copies
 894  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 895  */
 896 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 897 {
 898         struct nand_chip *nand_chip = mtd->priv;
 899         struct mxc_nand_host *host = nand_chip->priv;
 900         int n, col, i = 0;
 901
 902         MTDDEBUG(MTD_DEBUG_LEVEL3,
 903               "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
 904
 905         col = host->col_addr;
 906
 907         /* Adjust saved column address */
 908         if (col < mtd->writesize && host->spare_only)
 909                 col += mtd->writesize;
 910
 911         n = mtd->writesize + mtd->oobsize - col;
 912         n = min(len, n);
 913
 914         while (n > 0) {
 915                 void __iomem *p;
 916
 917                 if (col < mtd->writesize) {
 918                         p = host->regs->main_area[0] + (col & ~3);
 919                 } else {
 920                         p = host->regs->spare_area[0] -
 921                                         mtd->writesize + (col & ~3);
 922                 }
 923
 924                 if (((col | (int)&buf[i]) & 3) || n < 4) {
 925                         union {
 926                                 uint32_t word;
 927                                 uint8_t bytes[4];
 928                         } nfc_word;
 929
 930                         nfc_word.word = readl(p);
 931                         buf[i++] = nfc_word.bytes[col & 3];
 932                         n--;
 933                         col++;
 934                 } else {
 935                         int m = mtd->writesize - col;
 936
 937                         if (col >= mtd->writesize)
 938                                 m += mtd->oobsize;
 939
 940                         m = min(n, m) & ~3;
 941                         mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
 942
 943                         col += m;
 944                         i += m;
 945                         n -= m;
 946                 }
 947         }
 948         /* Update saved column address */
 949         host->col_addr = col;
 950 }
 951
 952 #ifdef __UBOOT__
 953 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 954 /*
 955  * Used by the upper layer to verify the data in NAND Flash
 956  * with the data in the buf.
 957  */
 958 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 959                                 const u_char *buf, int len)
 960 {
 961         u_char tmp[256];
 962         uint bsize;
 963
 964         while (len) {
 965                 bsize = min(len, 256);
 966                 mxc_nand_read_buf(mtd, tmp, bsize);
 967
 968                 if (memcmp(buf, tmp, bsize))
 969                         return 1;
 970
 971                 buf += bsize;
 972                 len -= bsize;
 973         }
 974
 975         return 0;
 976 }
 977 #endif
 978 #endif
 979
 980 /*
 981  * This function is used by upper layer for select and
 982  * deselect of the NAND chip
 983  */
 984 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 985 {
 986         struct nand_chip *nand_chip = mtd->priv;
 987         struct mxc_nand_host *host = nand_chip->priv;
 988
 989         switch (chip) {
 990         case -1:
 991                 /* TODO: Disable the NFC clock */
 992                 if (host->clk_act)
 993                         host->clk_act = 0;
 994                 break;
 995         case 0:
 996                 /* TODO: Enable the NFC clock */
 997                 if (!host->clk_act)
 998                         host->clk_act = 1;
 999                 break;
1000
1001         default:
1002                 break;
1003         }
1004 }
1005
1006 /*
1007  * Used by the upper layer to write command to NAND Flash for
1008  * different operations to be carried out on NAND Flash
1009  */
1010 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1011                                 int column, int page_addr)
1012 {
1013         struct nand_chip *nand_chip = mtd->priv;
1014         struct mxc_nand_host *host = nand_chip->priv;
1015
1016         MTDDEBUG(MTD_DEBUG_LEVEL3,
1017               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1018               command, column, page_addr);
1019
1020         /* Reset command state information */
1021         host->status_request = false;
1022
1023         /* Command pre-processing step */
1024         switch (command) {
1025
1026         case NAND_CMD_STATUS:
1027                 host->col_addr = 0;
1028                 host->status_request = true;
1029                 break;
1030
1031         case NAND_CMD_READ0:
1032                 host->page_addr = page_addr;
1033                 host->col_addr = column;
1034                 host->spare_only = false;
1035                 break;
1036
1037         case NAND_CMD_READOOB:
1038                 host->col_addr = column;
1039                 host->spare_only = true;
1040                 if (host->pagesize_2k)
1041                         command = NAND_CMD_READ0; /* only READ0 is valid */
1042                 break;
1043
1044         case NAND_CMD_SEQIN:
1045                 if (column >= mtd->writesize) {
1046                         /*
1047                          * before sending SEQIN command for partial write,
1048                          * we need read one page out. FSL NFC does not support
1049                          * partial write. It always sends out 512+ecc+512+ecc
1050                          * for large page nand flash. But for small page nand
1051                          * flash, it does support SPARE ONLY operation.
1052                          */
1053                         if (host->pagesize_2k) {
1054                                 /* call ourself to read a page */
1055                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1056                                                 page_addr);
1057                         }
1058
1059                         host->col_addr = column - mtd->writesize;
1060                         host->spare_only = true;
1061
1062                         /* Set program pointer to spare region */
1063                         if (!host->pagesize_2k)
1064                                 send_cmd(host, NAND_CMD_READOOB);
1065                 } else {
1066                         host->spare_only = false;
1067                         host->col_addr = column;
1068
1069                         /* Set program pointer to page start */
1070                         if (!host->pagesize_2k)
1071                                 send_cmd(host, NAND_CMD_READ0);
1072                 }
1073                 break;
1074
1075         case NAND_CMD_PAGEPROG:
1076                 send_prog_page(host, 0, host->spare_only);
1077
1078                 if (host->pagesize_2k && is_mxc_nfc_1()) {
1079                         /* data in 4 areas */
1080                         send_prog_page(host, 1, host->spare_only);
1081                         send_prog_page(host, 2, host->spare_only);
1082                         send_prog_page(host, 3, host->spare_only);
1083                 }
1084
1085                 break;
1086         }
1087
1088         /* Write out the command to the device. */
1089         send_cmd(host, command);
1090
1091         /* Write out column address, if necessary */
1092         if (column != -1) {
1093                 /*
1094                  * MXC NANDFC can only perform full page+spare or
1095                  * spare-only read/write. When the upper layers perform
1096                  * a read/write buffer operation, we will use the saved
1097                  * column address to index into the full page.
1098                  */
1099                 send_addr(host, 0);
1100                 if (host->pagesize_2k)
1101                         /* another col addr cycle for 2k page */
1102                         send_addr(host, 0);
1103         }
1104
1105         /* Write out page address, if necessary */
1106         if (page_addr != -1) {
1107                 u32 page_mask = nand_chip->pagemask;
1108                 do {
1109                         send_addr(host, page_addr & 0xFF);
1110                         page_addr >>= 8;
1111                         page_mask >>= 8;
1112                 } while (page_mask);
1113         }
1114
1115         /* Command post-processing step */
1116         switch (command) {
1117
1118         case NAND_CMD_RESET:
1119                 break;
1120
1121         case NAND_CMD_READOOB:
1122         case NAND_CMD_READ0:
1123                 if (host->pagesize_2k) {
1124                         /* send read confirm command */
1125                         send_cmd(host, NAND_CMD_READSTART);
1126                         /* read for each AREA */
1127                         send_read_page(host, 0, host->spare_only);
1128                         if (is_mxc_nfc_1()) {
1129                                 send_read_page(host, 1, host->spare_only);
1130                                 send_read_page(host, 2, host->spare_only);
1131                                 send_read_page(host, 3, host->spare_only);
1132                         }
1133                 } else {
1134                         send_read_page(host, 0, host->spare_only);
1135                 }
1136                 break;
1137
1138         case NAND_CMD_READID:
1139                 host->col_addr = 0;
1140                 send_read_id(host);
1141                 break;
1142
1143         case NAND_CMD_PAGEPROG:
1144                 break;
1145
1146         case NAND_CMD_STATUS:
1147                 break;
1148
1149         case NAND_CMD_ERASE2:
1150                 break;
1151         }
1152 }
1153
1154 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1155
1156 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1157 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1158
1159 static struct nand_bbt_descr bbt_main_descr = {
1160         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1161                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1162         .offs = 0,
1163         .len = 4,
1164         .veroffs = 4,
1165         .maxblocks = 4,
1166         .pattern = bbt_pattern,
1167 };
1168
1169 static struct nand_bbt_descr bbt_mirror_descr = {
1170         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1171                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1172         .offs = 0,
1173         .len = 4,
1174         .veroffs = 4,
1175         .maxblocks = 4,
1176         .pattern = mirror_pattern,
1177 };
1178
1179 #endif
1180
1181 int board_nand_init(struct nand_chip *this)
1182 {
1183         struct mtd_info *mtd;
1184 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1185         uint32_t tmp;
1186 #endif
1187
1188 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1189         this->bbt_options |= NAND_BBT_USE_FLASH;
1190         this->bbt_td = &bbt_main_descr;
1191         this->bbt_md = &bbt_mirror_descr;
1192 #endif
1193
1194         /* structures must be linked */
1195         mtd = &host->mtd;
1196         mtd->priv = this;
1197         host->nand = this;
1198
1199         /* 5 us command delay time */
1200         this->chip_delay = 5;
1201
1202         this->priv = host;
1203         this->dev_ready = mxc_nand_dev_ready;
1204         this->cmdfunc = mxc_nand_command;
1205         this->select_chip = mxc_nand_select_chip;
1206         this->read_byte = mxc_nand_read_byte;
1207         this->read_word = mxc_nand_read_word;
1208         this->write_buf = mxc_nand_write_buf;
1209         this->read_buf = mxc_nand_read_buf;
1210 #ifdef __UBOOT__
1211 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
1212         this->verify_buf = mxc_nand_verify_buf;
1213 #endif
1214 #endif
1215
1216         host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1217 #ifdef MXC_NFC_V3_2
1218         host->ip_regs =
1219                 (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1220 #endif
1221         host->clk_act = 1;
1222
1223 #ifdef CONFIG_MXC_NAND_HWECC
1224         this->ecc.calculate = mxc_nand_calculate_ecc;
1225         this->ecc.hwctl = mxc_nand_enable_hwecc;
1226         this->ecc.correct = mxc_nand_correct_data;
1227         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1228                 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1229                 this->ecc.read_page = mxc_nand_read_page_syndrome;
1230                 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1231                 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1232                 this->ecc.write_page = mxc_nand_write_page_syndrome;
1233                 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1234                 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1235                 this->ecc.bytes = 9;
1236                 this->ecc.prepad = 7;
1237         } else {
1238                 this->ecc.mode = NAND_ECC_HW;
1239         }
1240
1241         if (is_mxc_nfc_1())
1242                 this->ecc.strength = 1;
1243         else
1244                 this->ecc.strength = 4;
1245
1246         host->pagesize_2k = 0;
1247
1248         this->ecc.size = 512;
1249         _mxc_nand_enable_hwecc(mtd, 1);
1250 #else
1251         this->ecc.layout = &nand_soft_eccoob;
1252         this->ecc.mode = NAND_ECC_SOFT;
1253         _mxc_nand_enable_hwecc(mtd, 0);
1254 #endif
1255         /* Reset NAND */
1256         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1257
1258         /* NAND bus width determines access functions used by upper layer */
1259         if (is_16bit_nand())
1260                 this->options |= NAND_BUSWIDTH_16;
1261
1262 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1263         host->pagesize_2k = 1;
1264         this->ecc.layout = &nand_hw_eccoob2k;
1265 #else
1266         host->pagesize_2k = 0;
1267         this->ecc.layout = &nand_hw_eccoob;
1268 #endif
1269
1270 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1271 #ifdef MXC_NFC_V2_1
1272         tmp = readnfc(&host->regs->config1);
1273         tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1274         tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1275         writenfc(tmp, &host->regs->config1);
1276         if (host->pagesize_2k)
1277                 writenfc(64/2, &host->regs->spare_area_size);
1278         else
1279                 writenfc(16/2, &host->regs->spare_area_size);
1280 #endif
1281
1282         /*
1283          * preset operation
1284          * Unlock the internal RAM Buffer
1285          */
1286         writenfc(0x2, &host->regs->config);
1287
1288         /* Blocks to be unlocked */
1289         writenfc(0x0, &host->regs->unlockstart_blkaddr);
1290         /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1291          * unlockend_blkaddr, but the magic 0x4000 does not always work
1292          * when writing more than some 32 megabytes (on 2k page nands)
1293          * However 0xFFFF doesn't seem to have this kind
1294          * of limitation (tried it back and forth several times).
1295          * The linux kernel driver sets this to 0xFFFF for the v2 controller
1296          * only, but probably this was not tested there for v1.
1297          * The very same limitation seems to apply to this kernel driver.
1298          * This might be NAND chip specific and the i.MX31 datasheet is
1299          * extremely vague about the semantics of this register.
1300          */
1301         writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1302
1303         /* Unlock Block Command for given address range */
1304         writenfc(0x4, &host->regs->wrprot);
1305 #elif defined(MXC_NFC_V3_2)
1306         writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1307         writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1308
1309         /* Unlock the internal RAM Buffer */
1310         writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1311                         &host->ip_regs->wrprot);
1312
1313         /* Blocks to be unlocked */
1314         for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1315                 writenfc(0x0 | 0xFFFF << 16,
1316                                 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1317
1318         writenfc(0, &host->ip_regs->ipc);
1319
1320         tmp = readnfc(&host->ip_regs->config2);
1321         tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1322                         NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1323         tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1324
1325         if (host->pagesize_2k) {
1326                 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1327                 tmp |= NFC_V3_CONFIG2_PS_2048;
1328         } else {
1329                 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1330                 tmp |= NFC_V3_CONFIG2_PS_512;
1331         }
1332
1333         writenfc(tmp, &host->ip_regs->config2);
1334
1335         tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1336                         NFC_V3_CONFIG3_NO_SDMA |
1337                         NFC_V3_CONFIG3_RBB_MODE |
1338                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1339                         NFC_V3_CONFIG3_ADD_OP(0);
1340
1341         if (!(this->options & NAND_BUSWIDTH_16))
1342                 tmp |= NFC_V3_CONFIG3_FW8;
1343
1344         writenfc(tmp, &host->ip_regs->config3);
1345
1346         writenfc(0, &host->ip_regs->delay_line);
1347 #endif
1348
1349         return 0;
1350 }