2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/types.h>
33 #include <asm/errno.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/imx-common/regs-bch.h>
38 #include <asm/imx-common/regs-gpmi.h>
39 #include <asm/arch/sys_proto.h>
40 #include <asm/imx-common/dma.h>
42 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
44 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
45 #define MXS_NAND_METADATA_SIZE 10
47 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
49 #define MXS_NAND_BCH_TIMEOUT 10000
51 struct mxs_nand_info {
54 uint32_t cmd_queue_len;
55 uint32_t data_buf_size;
61 uint8_t marking_block_bad;
64 /* Functions with altered behaviour */
65 int (*hooked_read_oob)(struct mtd_info *mtd,
66 loff_t from, struct mtd_oob_ops *ops);
67 int (*hooked_write_oob)(struct mtd_info *mtd,
68 loff_t to, struct mtd_oob_ops *ops);
69 int (*hooked_block_markbad)(struct mtd_info *mtd,
73 struct mxs_dma_desc **desc;
77 struct nand_ecclayout fake_ecc_layout;
80 * Cache management functions
82 #ifndef CONFIG_SYS_DCACHE_OFF
83 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
85 uint32_t addr = (uint32_t)info->data_buf;
87 flush_dcache_range(addr, addr + info->data_buf_size);
90 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
92 uint32_t addr = (uint32_t)info->data_buf;
94 invalidate_dcache_range(addr, addr + info->data_buf_size);
97 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
99 uint32_t addr = (uint32_t)info->cmd_buf;
101 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
104 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
105 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
106 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
109 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
111 struct mxs_dma_desc *desc;
113 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
114 printf("MXS NAND: Too many DMA descriptors requested\n");
118 desc = info->desc[info->desc_index];
124 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
127 struct mxs_dma_desc *desc;
129 for (i = 0; i < info->desc_index; i++) {
130 desc = info->desc[i];
131 memset(desc, 0, sizeof(struct mxs_dma_desc));
132 desc->address = (dma_addr_t)desc;
135 info->desc_index = 0;
138 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
140 return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
143 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
145 return ecc_strength * 13;
148 static uint32_t mxs_nand_aux_status_offset(void)
150 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
153 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
154 uint32_t page_oob_size)
156 if (page_data_size == 2048)
159 if (page_data_size == 4096) {
160 if (page_oob_size == 128)
163 if (page_oob_size == 218)
170 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
171 uint32_t ecc_strength)
173 uint32_t chunk_data_size_in_bits;
174 uint32_t chunk_ecc_size_in_bits;
175 uint32_t chunk_total_size_in_bits;
176 uint32_t block_mark_chunk_number;
177 uint32_t block_mark_chunk_bit_offset;
178 uint32_t block_mark_bit_offset;
180 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
181 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
183 chunk_total_size_in_bits =
184 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
186 /* Compute the bit offset of the block mark within the physical page. */
187 block_mark_bit_offset = page_data_size * 8;
189 /* Subtract the metadata bits. */
190 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
193 * Compute the chunk number (starting at zero) in which the block mark
196 block_mark_chunk_number =
197 block_mark_bit_offset / chunk_total_size_in_bits;
200 * Compute the bit offset of the block mark within its chunk, and
203 block_mark_chunk_bit_offset = block_mark_bit_offset -
204 (block_mark_chunk_number * chunk_total_size_in_bits);
206 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
210 * Now that we know the chunk number in which the block mark appears,
211 * we can subtract all the ECC bits that appear before it.
213 block_mark_bit_offset -=
214 block_mark_chunk_number * chunk_ecc_size_in_bits;
216 return block_mark_bit_offset;
219 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
221 uint32_t ecc_strength;
222 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
223 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
226 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
228 uint32_t ecc_strength;
229 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
230 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
234 * Wait for BCH complete IRQ and clear the IRQ
236 static int mxs_nand_wait_for_bch_complete(void)
238 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
239 int timeout = MXS_NAND_BCH_TIMEOUT;
242 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
243 BCH_CTRL_COMPLETE_IRQ, timeout);
245 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
251 * This is the function that we install in the cmd_ctrl function pointer of the
252 * owning struct nand_chip. The only functions in the reference implementation
253 * that use these functions pointers are cmdfunc and select_chip.
255 * In this driver, we implement our own select_chip, so this function will only
256 * be called by the reference implementation's cmdfunc. For this reason, we can
257 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
260 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
262 struct nand_chip *nand = mtd->priv;
263 struct mxs_nand_info *nand_info = nand->priv;
264 struct mxs_dma_desc *d;
265 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
269 * If this condition is true, something is _VERY_ wrong in MTD
272 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
273 printf("MXS NAND: Command queue too long\n");
278 * Every operation begins with a command byte and a series of zero or
279 * more address bytes. These are distinguished by either the Address
280 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
281 * asserted. When MTD is ready to execute the command, it will
282 * deasert both latch enables.
284 * Rather than run a separate DMA operation for every single byte, we
285 * queue them up and run a single DMA operation for the entire series
286 * of command and data bytes.
288 if (ctrl & (NAND_ALE | NAND_CLE)) {
289 if (data != NAND_CMD_NONE)
290 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
295 * If control arrives here, MTD has deasserted both the ALE and CLE,
296 * which means it's ready to run an operation. Check if we have any
299 if (nand_info->cmd_queue_len == 0)
302 /* Compile the DMA descriptor -- a descriptor that sends command. */
303 d = mxs_nand_get_dma_desc(nand_info);
305 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
306 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
307 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
308 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
310 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
312 d->cmd.pio_words[0] =
313 GPMI_CTRL0_COMMAND_MODE_WRITE |
314 GPMI_CTRL0_WORD_LENGTH |
315 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
316 GPMI_CTRL0_ADDRESS_NAND_CLE |
317 GPMI_CTRL0_ADDRESS_INCREMENT |
318 nand_info->cmd_queue_len;
320 mxs_dma_desc_append(channel, d);
323 mxs_nand_flush_cmd_buf(nand_info);
325 /* Execute the DMA chain. */
326 ret = mxs_dma_go(channel);
328 printf("MXS NAND: Error sending command\n");
330 mxs_nand_return_dma_descs(nand_info);
332 /* Reset the command queue. */
333 nand_info->cmd_queue_len = 0;
337 * Test if the NAND flash is ready.
339 static int mxs_nand_device_ready(struct mtd_info *mtd)
341 struct nand_chip *chip = mtd->priv;
342 struct mxs_nand_info *nand_info = chip->priv;
343 struct mxs_gpmi_regs *gpmi_regs =
344 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
347 tmp = readl(&gpmi_regs->hw_gpmi_stat);
348 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
354 * Select the NAND chip.
356 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
358 struct nand_chip *nand = mtd->priv;
359 struct mxs_nand_info *nand_info = nand->priv;
361 nand_info->cur_chip = chip;
365 * Handle block mark swapping.
367 * Note that, when this function is called, it doesn't know whether it's
368 * swapping the block mark, or swapping it *back* -- but it doesn't matter
369 * because the the operation is the same.
371 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
372 uint8_t *data_buf, uint8_t *oob_buf)
380 bit_offset = mxs_nand_mark_bit_offset(mtd);
381 buf_offset = mxs_nand_mark_byte_offset(mtd);
384 * Get the byte from the data area that overlays the block mark. Since
385 * the ECC engine applies its own view to the bits in the page, the
386 * physical block mark won't (in general) appear on a byte boundary in
389 src = data_buf[buf_offset] >> bit_offset;
390 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
396 data_buf[buf_offset] &= ~(0xff << bit_offset);
397 data_buf[buf_offset + 1] &= 0xff << bit_offset;
399 data_buf[buf_offset] |= dst << bit_offset;
400 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
404 * Read data from NAND.
406 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
408 struct nand_chip *nand = mtd->priv;
409 struct mxs_nand_info *nand_info = nand->priv;
410 struct mxs_dma_desc *d;
411 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
414 if (length > NAND_MAX_PAGESIZE) {
415 printf("MXS NAND: DMA buffer too big\n");
420 printf("MXS NAND: DMA buffer is NULL\n");
424 /* Compile the DMA descriptor - a descriptor that reads data. */
425 d = mxs_nand_get_dma_desc(nand_info);
427 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
428 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
429 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
430 (length << MXS_DMA_DESC_BYTES_OFFSET);
432 d->cmd.address = (dma_addr_t)nand_info->data_buf;
434 d->cmd.pio_words[0] =
435 GPMI_CTRL0_COMMAND_MODE_READ |
436 GPMI_CTRL0_WORD_LENGTH |
437 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
438 GPMI_CTRL0_ADDRESS_NAND_DATA |
441 mxs_dma_desc_append(channel, d);
444 * A DMA descriptor that waits for the command to end and the chip to
447 * I think we actually should *not* be waiting for the chip to become
448 * ready because, after all, we don't care. I think the original code
449 * did that and no one has re-thought it yet.
451 d = mxs_nand_get_dma_desc(nand_info);
453 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
454 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
455 MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
459 d->cmd.pio_words[0] =
460 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
461 GPMI_CTRL0_WORD_LENGTH |
462 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
463 GPMI_CTRL0_ADDRESS_NAND_DATA;
465 mxs_dma_desc_append(channel, d);
467 /* Execute the DMA chain. */
468 ret = mxs_dma_go(channel);
470 printf("MXS NAND: DMA read error\n");
474 /* Invalidate caches */
475 mxs_nand_inval_data_buf(nand_info);
477 memcpy(buf, nand_info->data_buf, length);
480 mxs_nand_return_dma_descs(nand_info);
484 * Write data to NAND.
486 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
489 struct nand_chip *nand = mtd->priv;
490 struct mxs_nand_info *nand_info = nand->priv;
491 struct mxs_dma_desc *d;
492 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
495 if (length > NAND_MAX_PAGESIZE) {
496 printf("MXS NAND: DMA buffer too big\n");
501 printf("MXS NAND: DMA buffer is NULL\n");
505 memcpy(nand_info->data_buf, buf, length);
507 /* Compile the DMA descriptor - a descriptor that writes data. */
508 d = mxs_nand_get_dma_desc(nand_info);
510 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
511 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
512 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
513 (length << MXS_DMA_DESC_BYTES_OFFSET);
515 d->cmd.address = (dma_addr_t)nand_info->data_buf;
517 d->cmd.pio_words[0] =
518 GPMI_CTRL0_COMMAND_MODE_WRITE |
519 GPMI_CTRL0_WORD_LENGTH |
520 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
521 GPMI_CTRL0_ADDRESS_NAND_DATA |
524 mxs_dma_desc_append(channel, d);
527 mxs_nand_flush_data_buf(nand_info);
529 /* Execute the DMA chain. */
530 ret = mxs_dma_go(channel);
532 printf("MXS NAND: DMA write error\n");
534 mxs_nand_return_dma_descs(nand_info);
538 * Read a single byte from NAND.
540 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
543 mxs_nand_read_buf(mtd, &buf, 1);
548 * Read a page from NAND.
550 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
551 uint8_t *buf, int page)
553 struct mxs_nand_info *nand_info = nand->priv;
554 struct mxs_dma_desc *d;
555 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
556 uint32_t corrected = 0, failed = 0;
560 /* Compile the DMA descriptor - wait for ready. */
561 d = mxs_nand_get_dma_desc(nand_info);
563 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
564 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
565 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
569 d->cmd.pio_words[0] =
570 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
571 GPMI_CTRL0_WORD_LENGTH |
572 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
573 GPMI_CTRL0_ADDRESS_NAND_DATA;
575 mxs_dma_desc_append(channel, d);
577 /* Compile the DMA descriptor - enable the BCH block and read. */
578 d = mxs_nand_get_dma_desc(nand_info);
580 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
581 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
585 d->cmd.pio_words[0] =
586 GPMI_CTRL0_COMMAND_MODE_READ |
587 GPMI_CTRL0_WORD_LENGTH |
588 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
589 GPMI_CTRL0_ADDRESS_NAND_DATA |
590 (mtd->writesize + mtd->oobsize);
591 d->cmd.pio_words[1] = 0;
592 d->cmd.pio_words[2] =
593 GPMI_ECCCTRL_ENABLE_ECC |
594 GPMI_ECCCTRL_ECC_CMD_DECODE |
595 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
596 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
597 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
598 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
600 mxs_dma_desc_append(channel, d);
602 /* Compile the DMA descriptor - disable the BCH block. */
603 d = mxs_nand_get_dma_desc(nand_info);
605 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
606 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
607 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
611 d->cmd.pio_words[0] =
612 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
613 GPMI_CTRL0_WORD_LENGTH |
614 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
615 GPMI_CTRL0_ADDRESS_NAND_DATA |
616 (mtd->writesize + mtd->oobsize);
617 d->cmd.pio_words[1] = 0;
618 d->cmd.pio_words[2] = 0;
620 mxs_dma_desc_append(channel, d);
622 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
623 d = mxs_nand_get_dma_desc(nand_info);
625 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
626 MXS_DMA_DESC_DEC_SEM;
630 mxs_dma_desc_append(channel, d);
632 /* Execute the DMA chain. */
633 ret = mxs_dma_go(channel);
635 printf("MXS NAND: DMA read error\n");
639 ret = mxs_nand_wait_for_bch_complete();
641 printf("MXS NAND: BCH read timeout\n");
645 /* Invalidate caches */
646 mxs_nand_inval_data_buf(nand_info);
648 /* Read DMA completed, now do the mark swapping. */
649 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
651 /* Loop over status bytes, accumulating ECC status. */
652 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
653 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
654 if (status[i] == 0x00)
657 if (status[i] == 0xff)
660 if (status[i] == 0xfe) {
665 corrected += status[i];
668 /* Propagate ECC status to the owning MTD. */
669 mtd->ecc_stats.failed += failed;
670 mtd->ecc_stats.corrected += corrected;
673 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
674 * details about our policy for delivering the OOB.
676 * We fill the caller's buffer with set bits, and then copy the block
677 * mark to the caller's buffer. Note that, if block mark swapping was
678 * necessary, it has already been done, so we can rely on the first
679 * byte of the auxiliary buffer to contain the block mark.
681 memset(nand->oob_poi, 0xff, mtd->oobsize);
683 nand->oob_poi[0] = nand_info->oob_buf[0];
685 memcpy(buf, nand_info->data_buf, mtd->writesize);
688 mxs_nand_return_dma_descs(nand_info);
694 * Write a page to NAND.
696 static void mxs_nand_ecc_write_page(struct mtd_info *mtd,
697 struct nand_chip *nand, const uint8_t *buf)
699 struct mxs_nand_info *nand_info = nand->priv;
700 struct mxs_dma_desc *d;
701 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
704 memcpy(nand_info->data_buf, buf, mtd->writesize);
705 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
707 /* Handle block mark swapping. */
708 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
710 /* Compile the DMA descriptor - write data. */
711 d = mxs_nand_get_dma_desc(nand_info);
713 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
714 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
715 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
719 d->cmd.pio_words[0] =
720 GPMI_CTRL0_COMMAND_MODE_WRITE |
721 GPMI_CTRL0_WORD_LENGTH |
722 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
723 GPMI_CTRL0_ADDRESS_NAND_DATA;
724 d->cmd.pio_words[1] = 0;
725 d->cmd.pio_words[2] =
726 GPMI_ECCCTRL_ENABLE_ECC |
727 GPMI_ECCCTRL_ECC_CMD_ENCODE |
728 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
729 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
730 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
731 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
733 mxs_dma_desc_append(channel, d);
736 mxs_nand_flush_data_buf(nand_info);
738 /* Execute the DMA chain. */
739 ret = mxs_dma_go(channel);
741 printf("MXS NAND: DMA write error\n");
745 ret = mxs_nand_wait_for_bch_complete();
747 printf("MXS NAND: BCH write timeout\n");
752 mxs_nand_return_dma_descs(nand_info);
756 * Read OOB from NAND.
758 * This function is a veneer that replaces the function originally installed by
759 * the NAND Flash MTD code.
761 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
762 struct mtd_oob_ops *ops)
764 struct nand_chip *chip = mtd->priv;
765 struct mxs_nand_info *nand_info = chip->priv;
768 if (ops->mode == MTD_OOB_RAW)
769 nand_info->raw_oob_mode = 1;
771 nand_info->raw_oob_mode = 0;
773 ret = nand_info->hooked_read_oob(mtd, from, ops);
775 nand_info->raw_oob_mode = 0;
783 * This function is a veneer that replaces the function originally installed by
784 * the NAND Flash MTD code.
786 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
787 struct mtd_oob_ops *ops)
789 struct nand_chip *chip = mtd->priv;
790 struct mxs_nand_info *nand_info = chip->priv;
793 if (ops->mode == MTD_OOB_RAW)
794 nand_info->raw_oob_mode = 1;
796 nand_info->raw_oob_mode = 0;
798 ret = nand_info->hooked_write_oob(mtd, to, ops);
800 nand_info->raw_oob_mode = 0;
806 * Mark a block bad in NAND.
808 * This function is a veneer that replaces the function originally installed by
809 * the NAND Flash MTD code.
811 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
813 struct nand_chip *chip = mtd->priv;
814 struct mxs_nand_info *nand_info = chip->priv;
817 nand_info->marking_block_bad = 1;
819 ret = nand_info->hooked_block_markbad(mtd, ofs);
821 nand_info->marking_block_bad = 0;
827 * There are several places in this driver where we have to handle the OOB and
828 * block marks. This is the function where things are the most complicated, so
829 * this is where we try to explain it all. All the other places refer back to
832 * These are the rules, in order of decreasing importance:
834 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
835 * write operations take measures to protect it.
837 * 2) In read operations, the first byte of the OOB we return must reflect the
838 * true state of the block mark, no matter where that block mark appears in
841 * 3) ECC-based read operations return an OOB full of set bits (since we never
842 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
845 * 4) "Raw" read operations return a direct view of the physical bytes in the
846 * page, using the conventional definition of which bytes are data and which
847 * are OOB. This gives the caller a way to see the actual, physical bytes
848 * in the page, without the distortions applied by our ECC engine.
850 * What we do for this specific read operation depends on whether we're doing
851 * "raw" read, or an ECC-based read.
853 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
854 * easy. When reading a page, for example, the NAND Flash MTD code calls our
855 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
856 * ECC-based or raw view of the page is implicit in which function it calls
857 * (there is a similar pair of ECC-based/raw functions for writing).
859 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
860 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
861 * caller wants an ECC-based or raw view of the page is not propagated down to
864 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
865 * ecc.read_oob and ecc.write_oob function pointers in the owning
866 * struct mtd_info with our own functions. These hook functions set the
867 * raw_oob_mode field so that, when control finally arrives here, we'll know
870 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
873 struct mxs_nand_info *nand_info = nand->priv;
876 * First, fill in the OOB buffer. If we're doing a raw read, we need to
877 * get the bytes from the physical page. If we're not doing a raw read,
878 * we need to fill the buffer with set bits.
880 if (nand_info->raw_oob_mode) {
882 * If control arrives here, we're doing a "raw" read. Send the
883 * command to read the conventional OOB and read it.
885 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
886 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
889 * If control arrives here, we're not doing a "raw" read. Fill
890 * the OOB buffer with set bits and correct the block mark.
892 memset(nand->oob_poi, 0xff, mtd->oobsize);
894 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
895 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
903 * Write OOB data to NAND.
905 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
908 struct mxs_nand_info *nand_info = nand->priv;
909 uint8_t block_mark = 0;
912 * There are fundamental incompatibilities between the i.MX GPMI NFC and
913 * the NAND Flash MTD model that make it essentially impossible to write
914 * the out-of-band bytes.
916 * We permit *ONE* exception. If the *intent* of writing the OOB is to
917 * mark a block bad, we can do that.
920 if (!nand_info->marking_block_bad) {
921 printf("NXS NAND: Writing OOB isn't supported\n");
925 /* Write the block mark. */
926 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
927 nand->write_buf(mtd, &block_mark, 1);
928 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
930 /* Check if it worked. */
931 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
938 * Claims all blocks are good.
940 * In principle, this function is *only* called when the NAND Flash MTD system
941 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
942 * the driver for bad block information.
944 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
945 * this function is *only* called when we take it away.
947 * Thus, this function is only called when we want *all* blocks to look good,
948 * so it *always* return success.
950 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
956 * Nominally, the purpose of this function is to look for or create the bad
957 * block table. In fact, since the we call this function at the very end of
958 * the initialization process started by nand_scan(), and we doesn't have a
959 * more formal mechanism, we "hook" this function to continue init process.
961 * At this point, the physical NAND Flash chips have been identified and
962 * counted, so we know the physical geometry. This enables us to make some
963 * important configuration decisions.
965 * The return value of this function propogates directly back to this driver's
966 * call to nand_scan(). Anything other than zero will cause this driver to
967 * tear everything down and declare failure.
969 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
971 struct nand_chip *nand = mtd->priv;
972 struct mxs_nand_info *nand_info = nand->priv;
973 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
976 /* Configure BCH and set NFC geometry */
977 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
979 /* Configure layout 0 */
980 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
981 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
982 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
983 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
984 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
985 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
986 writel(tmp, &bch_regs->hw_bch_flash0layout0);
988 tmp = (mtd->writesize + mtd->oobsize)
989 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
990 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
991 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
992 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
993 writel(tmp, &bch_regs->hw_bch_flash0layout1);
995 /* Set *all* chip selects to use layout 0 */
996 writel(0, &bch_regs->hw_bch_layoutselect);
998 /* Enable BCH complete interrupt */
999 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1001 /* Hook some operations at the MTD level. */
1002 if (mtd->read_oob != mxs_nand_hook_read_oob) {
1003 nand_info->hooked_read_oob = mtd->read_oob;
1004 mtd->read_oob = mxs_nand_hook_read_oob;
1007 if (mtd->write_oob != mxs_nand_hook_write_oob) {
1008 nand_info->hooked_write_oob = mtd->write_oob;
1009 mtd->write_oob = mxs_nand_hook_write_oob;
1012 if (mtd->block_markbad != mxs_nand_hook_block_markbad) {
1013 nand_info->hooked_block_markbad = mtd->block_markbad;
1014 mtd->block_markbad = mxs_nand_hook_block_markbad;
1017 /* We use the reference implementation for bad block management. */
1018 return nand_default_bbt(mtd);
1022 * Allocate DMA buffers
1024 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1027 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1029 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1032 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1034 printf("MXS NAND: Error allocating DMA buffers\n");
1038 memset(buf, 0, nand_info->data_buf_size);
1040 nand_info->data_buf = buf;
1041 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1042 /* Command buffers */
1043 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1044 MXS_NAND_COMMAND_BUFFER_SIZE);
1045 if (!nand_info->cmd_buf) {
1047 printf("MXS NAND: Error allocating command buffers\n");
1050 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1051 nand_info->cmd_queue_len = 0;
1057 * Initializes the NFC hardware.
1059 int mxs_nand_init(struct mxs_nand_info *info)
1061 struct mxs_gpmi_regs *gpmi_regs =
1062 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1063 struct mxs_bch_regs *bch_regs =
1064 (struct mxs_bch_regs *)MXS_BCH_BASE;
1067 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1068 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1072 /* Allocate the DMA descriptors. */
1073 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1074 info->desc[i] = mxs_dma_desc_alloc();
1079 /* Init the DMA controller. */
1080 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1081 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1082 if (mxs_dma_init_channel(j))
1086 /* Reset the GPMI block. */
1087 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1088 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1091 * Choose NAND mode, set IRQ polarity, disable write protection and
1094 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1095 GPMI_CTRL1_GPMI_MODE,
1096 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1097 GPMI_CTRL1_BCH_MODE);
1102 for (--j; j >= 0; j--)
1107 for (--i; i >= 0; i--)
1108 mxs_dma_desc_free(info->desc[i]);
1109 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1114 * This function is called during the driver binding process.
1116 * @param pdev the device structure used to store device specific
1117 * information that is used by the suspend, resume and
1120 * @return The function always returns 0.
1122 int board_nand_init(struct nand_chip *nand)
1124 struct mxs_nand_info *nand_info;
1127 nand_info = malloc(sizeof(struct mxs_nand_info));
1129 printf("MXS NAND: Failed to allocate private data\n");
1132 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1134 err = mxs_nand_alloc_buffers(nand_info);
1138 err = mxs_nand_init(nand_info);
1142 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1144 nand->priv = nand_info;
1145 nand->options |= NAND_NO_SUBPAGE_WRITE;
1147 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1149 nand->dev_ready = mxs_nand_device_ready;
1150 nand->select_chip = mxs_nand_select_chip;
1151 nand->block_bad = mxs_nand_block_bad;
1152 nand->scan_bbt = mxs_nand_scan_bbt;
1154 nand->read_byte = mxs_nand_read_byte;
1156 nand->read_buf = mxs_nand_read_buf;
1157 nand->write_buf = mxs_nand_write_buf;
1159 nand->ecc.read_page = mxs_nand_ecc_read_page;
1160 nand->ecc.write_page = mxs_nand_ecc_write_page;
1161 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1162 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1164 nand->ecc.layout = &fake_ecc_layout;
1165 nand->ecc.mode = NAND_ECC_HW;
1166 nand->ecc.bytes = 9;
1167 nand->ecc.size = 512;
1172 free(nand_info->data_buf);
1173 free(nand_info->cmd_buf);