drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *
   8  *      Additional technical information is available on
   9  *      http://www.linux-mtd.infradead.org/doc/nand.html
  10  *
  11  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  12  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  13  *
  14  *  Credits:
  15  *      David Woodhouse for adding multichip support
  16  *
  17  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  18  *      rework for 2K page size chips
  19  *
  20  *  TODO:
  21  *      Enable cached programming for 2k page size chips
  22  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  23  *      if we have HW ECC support.
  24  *      BBT table is not serialized, has to be fixed
  25  *
  26  * This program is free software; you can redistribute it and/or modify
  27  * it under the terms of the GNU General Public License version 2 as
  28  * published by the Free Software Foundation.
  29  *
  30  */
  31
  32 #define __UBOOT__
  33 #ifndef __UBOOT__
  34 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  35
  36 #include <linux/module.h>
  37 #include <linux/delay.h>
  38 #include <linux/errno.h>
  39 #include <linux/err.h>
  40 #include <linux/sched.h>
  41 #include <linux/slab.h>
  42 #include <linux/types.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/nand_bch.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/bitops.h>
  49 #include <linux/leds.h>
  50 #include <linux/io.h>
  51 #include <linux/mtd/partitions.h>
  52 #else
  53 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  54 #include <common.h>
  55 #include <malloc.h>
  56 #include <watchdog.h>
  57 #include <linux/err.h>
  58 #include <linux/compat.h>
  59 #include <linux/mtd/mtd.h>
  60 #include <linux/mtd/nand.h>
  61 #include <linux/mtd/nand_ecc.h>
  62 #include <linux/mtd/nand_bch.h>
  63 #ifdef CONFIG_MTD_PARTITIONS
  64 #include <linux/mtd/partitions.h>
  65 #endif
  66 #include <asm/io.h>
  67 #include <asm/errno.h>
  68
  69 /*
  70  * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
  71  * a flash.  NAND flash is initialized prior to interrupts so standard timers
  72  * can't be used.  CONFIG_SYS_NAND_RESET_CNT should be set to a value
  73  * which is greater than (max NAND reset time / NAND status read time).
  74  * A conservative default of 200000 (500 us / 25 ns) is used as a default.
  75  */
  76 #ifndef CONFIG_SYS_NAND_RESET_CNT
  77 #define CONFIG_SYS_NAND_RESET_CNT 200000
  78 #endif
  79
  80 static bool is_module_text_address(unsigned long addr) {return 0;}
  81 #endif
  82
  83 /* Define default oob placement schemes for large and small page devices */
  84 static struct nand_ecclayout nand_oob_8 = {
  85         .eccbytes = 3,
  86         .eccpos = {0, 1, 2},
  87         .oobfree = {
  88                 {.offset = 3,
  89                  .length = 2},
  90                 {.offset = 6,
  91                  .length = 2} }
  92 };
  93
  94 static struct nand_ecclayout nand_oob_16 = {
  95         .eccbytes = 6,
  96         .eccpos = {0, 1, 2, 3, 6, 7},
  97         .oobfree = {
  98                 {.offset = 8,
  99                  . length = 8} }
 100 };
 101
 102 static struct nand_ecclayout nand_oob_64 = {
 103         .eccbytes = 24,
 104         .eccpos = {
 105                    40, 41, 42, 43, 44, 45, 46, 47,
 106                    48, 49, 50, 51, 52, 53, 54, 55,
 107                    56, 57, 58, 59, 60, 61, 62, 63},
 108         .oobfree = {
 109                 {.offset = 2,
 110                  .length = 38} }
 111 };
 112
 113 static struct nand_ecclayout nand_oob_128 = {
 114         .eccbytes = 48,
 115         .eccpos = {
 116                    80, 81, 82, 83, 84, 85, 86, 87,
 117                    88, 89, 90, 91, 92, 93, 94, 95,
 118                    96, 97, 98, 99, 100, 101, 102, 103,
 119                    104, 105, 106, 107, 108, 109, 110, 111,
 120                    112, 113, 114, 115, 116, 117, 118, 119,
 121                    120, 121, 122, 123, 124, 125, 126, 127},
 122         .oobfree = {
 123                 {.offset = 2,
 124                  .length = 78} }
 125 };
 126
 127 static int nand_get_device(struct mtd_info *mtd, int new_state);
 128
 129 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 130                              struct mtd_oob_ops *ops);
 131
 132 /*
 133  * For devices which display every fart in the system on a separate LED. Is
 134  * compiled away when LED support is disabled.
 135  */
 136 DEFINE_LED_TRIGGER(nand_led_trigger);
 137
 138 static int check_offs_len(struct mtd_info *mtd,
 139                                         loff_t ofs, uint64_t len)
 140 {
 141         struct nand_chip *chip = mtd->priv;
 142         int ret = 0;
 143
 144         /* Start address must align on block boundary */
 145         if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
 146                 pr_debug("%s: unaligned address\n", __func__);
 147                 ret = -EINVAL;
 148         }
 149
 150         /* Length must align on block boundary */
 151         if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
 152                 pr_debug("%s: length not block aligned\n", __func__);
 153                 ret = -EINVAL;
 154         }
 155
 156         return ret;
 157 }
 158
 159 /**
 160  * nand_release_device - [GENERIC] release chip
 161  * @mtd: MTD device structure
 162  *
 163  * Release chip lock and wake up anyone waiting on the device.
 164  */
 165 static void nand_release_device(struct mtd_info *mtd)
 166 {
 167         struct nand_chip *chip = mtd->priv;
 168
 169 #ifndef __UBOOT__
 170         /* Release the controller and the chip */
 171         spin_lock(&chip->controller->lock);
 172         chip->controller->active = NULL;
 173         chip->state = FL_READY;
 174         wake_up(&chip->controller->wq);
 175         spin_unlock(&chip->controller->lock);
 176 #else
 177         /* De-select the NAND device */
 178         chip->select_chip(mtd, -1);
 179 #endif
 180 }
 181
 182 /**
 183  * nand_read_byte - [DEFAULT] read one byte from the chip
 184  * @mtd: MTD device structure
 185  *
 186  * Default read function for 8bit buswidth
 187  */
 188 #ifndef __UBOOT__
 189 static uint8_t nand_read_byte(struct mtd_info *mtd)
 190 #else
 191 uint8_t nand_read_byte(struct mtd_info *mtd)
 192 #endif
 193 {
 194         struct nand_chip *chip = mtd->priv;
 195         return readb(chip->IO_ADDR_R);
 196 }
 197
 198 /**
 199  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 200  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 201  * @mtd: MTD device structure
 202  *
 203  * Default read function for 16bit buswidth with endianness conversion.
 204  *
 205  */
 206 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 207 {
 208         struct nand_chip *chip = mtd->priv;
 209         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 210 }
 211
 212 /**
 213  * nand_read_word - [DEFAULT] read one word from the chip
 214  * @mtd: MTD device structure
 215  *
 216  * Default read function for 16bit buswidth without endianness conversion.
 217  */
 218 static u16 nand_read_word(struct mtd_info *mtd)
 219 {
 220         struct nand_chip *chip = mtd->priv;
 221         return readw(chip->IO_ADDR_R);
 222 }
 223
 224 /**
 225  * nand_select_chip - [DEFAULT] control CE line
 226  * @mtd: MTD device structure
 227  * @chipnr: chipnumber to select, -1 for deselect
 228  *
 229  * Default select function for 1 chip devices.
 230  */
 231 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 232 {
 233         struct nand_chip *chip = mtd->priv;
 234
 235         switch (chipnr) {
 236         case -1:
 237                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 238                 break;
 239         case 0:
 240                 break;
 241
 242         default:
 243                 BUG();
 244         }
 245 }
 246
 247 /**
 248  * nand_write_byte - [DEFAULT] write single byte to chip
 249  * @mtd: MTD device structure
 250  * @byte: value to write
 251  *
 252  * Default function to write a byte to I/O[7:0]
 253  */
 254 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
 255 {
 256         struct nand_chip *chip = mtd->priv;
 257
 258         chip->write_buf(mtd, &byte, 1);
 259 }
 260
 261 /**
 262  * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
 263  * @mtd: MTD device structure
 264  * @byte: value to write
 265  *
 266  * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
 267  */
 268 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
 269 {
 270         struct nand_chip *chip = mtd->priv;
 271         uint16_t word = byte;
 272
 273         /*
 274          * It's not entirely clear what should happen to I/O[15:8] when writing
 275          * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
 276          *
 277          *    When the host supports a 16-bit bus width, only data is
 278          *    transferred at the 16-bit width. All address and command line
 279          *    transfers shall use only the lower 8-bits of the data bus. During
 280          *    command transfers, the host may place any value on the upper
 281          *    8-bits of the data bus. During address transfers, the host shall
 282          *    set the upper 8-bits of the data bus to 00h.
 283          *
 284          * One user of the write_byte callback is nand_onfi_set_features. The
 285          * four parameters are specified to be written to I/O[7:0], but this is
 286          * neither an address nor a command transfer. Let's assume a 0 on the
 287          * upper I/O lines is OK.
 288          */
 289         chip->write_buf(mtd, (uint8_t *)&word, 2);
 290 }
 291
 292 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
 293 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
 294 {
 295         int i;
 296
 297         for (i = 0; i < len; i++)
 298                 writeb(buf[i], addr);
 299 }
 300 static void ioread8_rep(void *addr, uint8_t *buf, int len)
 301 {
 302         int i;
 303
 304         for (i = 0; i < len; i++)
 305                 buf[i] = readb(addr);
 306 }
 307
 308 static void ioread16_rep(void *addr, void *buf, int len)
 309 {
 310         int i;
 311         u16 *p = (u16 *) buf;
 312         len >>= 1;
 313
 314         for (i = 0; i < len; i++)
 315                 p[i] = readw(addr);
 316 }
 317
 318 static void iowrite16_rep(void *addr, void *buf, int len)
 319 {
 320         int i;
 321         u16 *p = (u16 *) buf;
 322         len >>= 1;
 323
 324         for (i = 0; i < len; i++)
 325                 writew(p[i], addr);
 326 }
 327 #endif
 328
 329 /**
 330  * nand_write_buf - [DEFAULT] write buffer to chip
 331  * @mtd: MTD device structure
 332  * @buf: data buffer
 333  * @len: number of bytes to write
 334  *
 335  * Default write function for 8bit buswidth.
 336  */
 337 #ifndef __UBOOT__
 338 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 339 #else
 340 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 341 #endif
 342 {
 343         struct nand_chip *chip = mtd->priv;
 344
 345         iowrite8_rep(chip->IO_ADDR_W, buf, len);
 346 }
 347
 348 /**
 349  * nand_read_buf - [DEFAULT] read chip data into buffer
 350  * @mtd: MTD device structure
 351  * @buf: buffer to store date
 352  * @len: number of bytes to read
 353  *
 354  * Default read function for 8bit buswidth.
 355  */
 356 #ifndef __UBOOT__
 357 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 358 #else
 359 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 360 #endif
 361 {
 362         struct nand_chip *chip = mtd->priv;
 363
 364         ioread8_rep(chip->IO_ADDR_R, buf, len);
 365 }
 366
 367 #ifdef __UBOOT__
 368 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
 369 /**
 370  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 371  * @mtd: MTD device structure
 372  * @buf: buffer containing the data to compare
 373  * @len: number of bytes to compare
 374  *
 375  * Default verify function for 8bit buswidth.
 376  */
 377 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 378 {
 379         int i;
 380         struct nand_chip *chip = mtd->priv;
 381
 382         for (i = 0; i < len; i++)
 383                 if (buf[i] != readb(chip->IO_ADDR_R))
 384                         return -EFAULT;
 385         return 0;
 386 }
 387
 388 /**
 389  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 390  * @mtd: MTD device structure
 391  * @buf: buffer containing the data to compare
 392  * @len: number of bytes to compare
 393  *
 394  * Default verify function for 16bit buswidth.
 395  */
 396 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 397 {
 398         int i;
 399         struct nand_chip *chip = mtd->priv;
 400         u16 *p = (u16 *) buf;
 401         len >>= 1;
 402
 403         for (i = 0; i < len; i++)
 404                 if (p[i] != readw(chip->IO_ADDR_R))
 405                         return -EFAULT;
 406
 407         return 0;
 408 }
 409 #endif
 410 #endif
 411
 412 /**
 413  * nand_write_buf16 - [DEFAULT] write buffer to chip
 414  * @mtd: MTD device structure
 415  * @buf: data buffer
 416  * @len: number of bytes to write
 417  *
 418  * Default write function for 16bit buswidth.
 419  */
 420 #ifndef __UBOOT__
 421 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 422 #else
 423 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 424 #endif
 425 {
 426         struct nand_chip *chip = mtd->priv;
 427         u16 *p = (u16 *) buf;
 428
 429         iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
 430 }
 431
 432 /**
 433  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 434  * @mtd: MTD device structure
 435  * @buf: buffer to store date
 436  * @len: number of bytes to read
 437  *
 438  * Default read function for 16bit buswidth.
 439  */
 440 #ifndef __UBOOT__
 441 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 442 #else
 443 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 444 #endif
 445 {
 446         struct nand_chip *chip = mtd->priv;
 447         u16 *p = (u16 *) buf;
 448
 449         ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
 450 }
 451
 452 /**
 453  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 454  * @mtd: MTD device structure
 455  * @ofs: offset from device start
 456  * @getchip: 0, if the chip is already selected
 457  *
 458  * Check, if the block is bad.
 459  */
 460 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 461 {
 462         int page, chipnr, res = 0, i = 0;
 463         struct nand_chip *chip = mtd->priv;
 464         u16 bad;
 465
 466         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 467                 ofs += mtd->erasesize - mtd->writesize;
 468
 469         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 470
 471         if (getchip) {
 472                 chipnr = (int)(ofs >> chip->chip_shift);
 473
 474                 nand_get_device(mtd, FL_READING);
 475
 476                 /* Select the NAND device */
 477                 chip->select_chip(mtd, chipnr);
 478         }
 479
 480         do {
 481                 if (chip->options & NAND_BUSWIDTH_16) {
 482                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 483                                         chip->badblockpos & 0xFE, page);
 484                         bad = cpu_to_le16(chip->read_word(mtd));
 485                         if (chip->badblockpos & 0x1)
 486                                 bad >>= 8;
 487                         else
 488                                 bad &= 0xFF;
 489                 } else {
 490                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 491                                         page);
 492                         bad = chip->read_byte(mtd);
 493                 }
 494
 495                 if (likely(chip->badblockbits == 8))
 496                         res = bad != 0xFF;
 497                 else
 498                         res = hweight8(bad) < chip->badblockbits;
 499                 ofs += mtd->writesize;
 500                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 501                 i++;
 502         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 503
 504         if (getchip) {
 505                 chip->select_chip(mtd, -1);
 506                 nand_release_device(mtd);
 507         }
 508
 509         return res;
 510 }
 511
 512 /**
 513  * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
 514  * @mtd: MTD device structure
 515  * @ofs: offset from device start
 516  *
 517  * This is the default implementation, which can be overridden by a hardware
 518  * specific driver. It provides the details for writing a bad block marker to a
 519  * block.
 520  */
 521 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 522 {
 523         struct nand_chip *chip = mtd->priv;
 524         struct mtd_oob_ops ops;
 525         uint8_t buf[2] = { 0, 0 };
 526         int ret = 0, res, i = 0;
 527
 528         ops.datbuf = NULL;
 529         ops.oobbuf = buf;
 530         ops.ooboffs = chip->badblockpos;
 531         if (chip->options & NAND_BUSWIDTH_16) {
 532                 ops.ooboffs &= ~0x01;
 533                 ops.len = ops.ooblen = 2;
 534         } else {
 535                 ops.len = ops.ooblen = 1;
 536         }
 537         ops.mode = MTD_OPS_PLACE_OOB;
 538
 539         /* Write to first/last page(s) if necessary */
 540         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 541                 ofs += mtd->erasesize - mtd->writesize;
 542         do {
 543                 res = nand_do_write_oob(mtd, ofs, &ops);
 544                 if (!ret)
 545                         ret = res;
 546
 547                 i++;
 548                 ofs += mtd->writesize;
 549         } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 550
 551         return ret;
 552 }
 553
 554 /**
 555  * nand_block_markbad_lowlevel - mark a block bad
 556  * @mtd: MTD device structure
 557  * @ofs: offset from device start
 558  *
 559  * This function performs the generic NAND bad block marking steps (i.e., bad
 560  * block table(s) and/or marker(s)). We only allow the hardware driver to
 561  * specify how to write bad block markers to OOB (chip->block_markbad).
 562  *
 563  * We try operations in the following order:
 564  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 565  *  (2) write bad block marker to OOB area of affected block (unless flag
 566  *      NAND_BBT_NO_OOB_BBM is present)
 567  *  (3) update the BBT
 568  * Note that we retain the first error encountered in (2) or (3), finish the
 569  * procedures, and dump the error in the end.
 570 */
 571 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 572 {
 573         struct nand_chip *chip = mtd->priv;
 574         int res, ret = 0;
 575
 576         if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
 577                 struct erase_info einfo;
 578
 579                 /* Attempt erase before marking OOB */
 580                 memset(&einfo, 0, sizeof(einfo));
 581                 einfo.mtd = mtd;
 582                 einfo.addr = ofs;
 583                 einfo.len = 1ULL << chip->phys_erase_shift;
 584                 nand_erase_nand(mtd, &einfo, 0);
 585
 586                 /* Write bad block marker to OOB */
 587                 nand_get_device(mtd, FL_WRITING);
 588                 ret = chip->block_markbad(mtd, ofs);
 589                 nand_release_device(mtd);
 590         }
 591
 592         /* Mark block bad in BBT */
 593         if (chip->bbt) {
 594                 res = nand_markbad_bbt(mtd, ofs);
 595                 if (!ret)
 596                         ret = res;
 597         }
 598
 599         if (!ret)
 600                 mtd->ecc_stats.badblocks++;
 601
 602         return ret;
 603 }
 604
 605 /**
 606  * nand_check_wp - [GENERIC] check if the chip is write protected
 607  * @mtd: MTD device structure
 608  *
 609  * Check, if the device is write protected. The function expects, that the
 610  * device is already selected.
 611  */
 612 static int nand_check_wp(struct mtd_info *mtd)
 613 {
 614         struct nand_chip *chip = mtd->priv;
 615
 616         /* Broken xD cards report WP despite being writable */
 617         if (chip->options & NAND_BROKEN_XD)
 618                 return 0;
 619
 620         /* Check the WP bit */
 621         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 622         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 623 }
 624
 625 /**
 626  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 627  * @mtd: MTD device structure
 628  * @ofs: offset from device start
 629  * @getchip: 0, if the chip is already selected
 630  * @allowbbt: 1, if its allowed to access the bbt area
 631  *
 632  * Check, if the block is bad. Either by reading the bad block table or
 633  * calling of the scan function.
 634  */
 635 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 636                                int allowbbt)
 637 {
 638         struct nand_chip *chip = mtd->priv;
 639
 640         if (!chip->bbt)
 641                 return chip->block_bad(mtd, ofs, getchip);
 642
 643         /* Return info from the table */
 644         return nand_isbad_bbt(mtd, ofs, allowbbt);
 645 }
 646
 647 #ifndef __UBOOT__
 648 /**
 649  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 650  * @mtd: MTD device structure
 651  * @timeo: Timeout
 652  *
 653  * Helper function for nand_wait_ready used when needing to wait in interrupt
 654  * context.
 655  */
 656 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 657 {
 658         struct nand_chip *chip = mtd->priv;
 659         int i;
 660
 661         /* Wait for the device to get ready */
 662         for (i = 0; i < timeo; i++) {
 663                 if (chip->dev_ready(mtd))
 664                         break;
 665                 touch_softlockup_watchdog();
 666                 mdelay(1);
 667         }
 668 }
 669 #endif
 670
 671 /* Wait for the ready pin, after a command. The timeout is caught later. */
 672 void nand_wait_ready(struct mtd_info *mtd)
 673 {
 674         struct nand_chip *chip = mtd->priv;
 675 #ifndef __UBOOT__
 676         unsigned long timeo = jiffies + msecs_to_jiffies(20);
 677
 678         /* 400ms timeout */
 679         if (in_interrupt() || oops_in_progress)
 680                 return panic_nand_wait_ready(mtd, 400);
 681
 682         led_trigger_event(nand_led_trigger, LED_FULL);
 683         /* Wait until command is processed or timeout occurs */
 684         do {
 685                 if (chip->dev_ready(mtd))
 686                         break;
 687                 touch_softlockup_watchdog();
 688         } while (time_before(jiffies, timeo));
 689         led_trigger_event(nand_led_trigger, LED_OFF);
 690 #else
 691         u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
 692         u32 time_start;
 693
 694         time_start = get_timer(0);
 695         /* Wait until command is processed or timeout occurs */
 696         while (get_timer(time_start) < timeo) {
 697                 if (chip->dev_ready)
 698                         if (chip->dev_ready(mtd))
 699                                 break;
 700         }
 701 #endif
 702 }
 703 EXPORT_SYMBOL_GPL(nand_wait_ready);
 704
 705 /**
 706  * nand_command - [DEFAULT] Send command to NAND device
 707  * @mtd: MTD device structure
 708  * @command: the command to be sent
 709  * @column: the column address for this command, -1 if none
 710  * @page_addr: the page address for this command, -1 if none
 711  *
 712  * Send command to NAND device. This function is used for small page devices
 713  * (512 Bytes per page).
 714  */
 715 static void nand_command(struct mtd_info *mtd, unsigned int command,
 716                          int column, int page_addr)
 717 {
 718         register struct nand_chip *chip = mtd->priv;
 719         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 720         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 721
 722         /* Write out the command to the device */
 723         if (command == NAND_CMD_SEQIN) {
 724                 int readcmd;
 725
 726                 if (column >= mtd->writesize) {
 727                         /* OOB area */
 728                         column -= mtd->writesize;
 729                         readcmd = NAND_CMD_READOOB;
 730                 } else if (column < 256) {
 731                         /* First 256 bytes --> READ0 */
 732                         readcmd = NAND_CMD_READ0;
 733                 } else {
 734                         column -= 256;
 735                         readcmd = NAND_CMD_READ1;
 736                 }
 737                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 738                 ctrl &= ~NAND_CTRL_CHANGE;
 739         }
 740         chip->cmd_ctrl(mtd, command, ctrl);
 741
 742         /* Address cycle, when necessary */
 743         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 744         /* Serially input address */
 745         if (column != -1) {
 746                 /* Adjust columns for 16 bit buswidth */
 747                 if (chip->options & NAND_BUSWIDTH_16 &&
 748                                 !nand_opcode_8bits(command))
 749                         column >>= 1;
 750                 chip->cmd_ctrl(mtd, column, ctrl);
 751                 ctrl &= ~NAND_CTRL_CHANGE;
 752         }
 753         if (page_addr != -1) {
 754                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 755                 ctrl &= ~NAND_CTRL_CHANGE;
 756                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 757                 /* One more address cycle for devices > 32MiB */
 758                 if (chip->chipsize > (32 << 20))
 759                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 760         }
 761         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 762
 763         /*
 764          * Program and erase have their own busy handlers status and sequential
 765          * in needs no delay
 766          */
 767         switch (command) {
 768
 769         case NAND_CMD_PAGEPROG:
 770         case NAND_CMD_ERASE1:
 771         case NAND_CMD_ERASE2:
 772         case NAND_CMD_SEQIN:
 773         case NAND_CMD_STATUS:
 774                 return;
 775
 776         case NAND_CMD_RESET:
 777                 if (chip->dev_ready)
 778                         break;
 779                 udelay(chip->chip_delay);
 780                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 781                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 782                 chip->cmd_ctrl(mtd,
 783                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 784                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 785                         (rst_sts_cnt--));
 786                 return;
 787
 788                 /* This applies to read commands */
 789         default:
 790                 /*
 791                  * If we don't have access to the busy pin, we apply the given
 792                  * command delay
 793                  */
 794                 if (!chip->dev_ready) {
 795                         udelay(chip->chip_delay);
 796                         return;
 797                 }
 798         }
 799         /*
 800          * Apply this short delay always to ensure that we do wait tWB in
 801          * any case on any machine.
 802          */
 803         ndelay(100);
 804
 805         nand_wait_ready(mtd);
 806 }
 807
 808 /**
 809  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 810  * @mtd: MTD device structure
 811  * @command: the command to be sent
 812  * @column: the column address for this command, -1 if none
 813  * @page_addr: the page address for this command, -1 if none
 814  *
 815  * Send command to NAND device. This is the version for the new large page
 816  * devices. We don't have the separate regions as we have in the small page
 817  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 818  */
 819 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 820                             int column, int page_addr)
 821 {
 822         register struct nand_chip *chip = mtd->priv;
 823         uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
 824
 825         /* Emulate NAND_CMD_READOOB */
 826         if (command == NAND_CMD_READOOB) {
 827                 column += mtd->writesize;
 828                 command = NAND_CMD_READ0;
 829         }
 830
 831         /* Command latch cycle */
 832         chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 833
 834         if (column != -1 || page_addr != -1) {
 835                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 836
 837                 /* Serially input address */
 838                 if (column != -1) {
 839                         /* Adjust columns for 16 bit buswidth */
 840                         if (chip->options & NAND_BUSWIDTH_16 &&
 841                                         !nand_opcode_8bits(command))
 842                                 column >>= 1;
 843                         chip->cmd_ctrl(mtd, column, ctrl);
 844                         ctrl &= ~NAND_CTRL_CHANGE;
 845                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 846                 }
 847                 if (page_addr != -1) {
 848                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 849                         chip->cmd_ctrl(mtd, page_addr >> 8,
 850                                        NAND_NCE | NAND_ALE);
 851                         /* One more address cycle for devices > 128MiB */
 852                         if (chip->chipsize > (128 << 20))
 853                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 854                                                NAND_NCE | NAND_ALE);
 855                 }
 856         }
 857         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 858
 859         /*
 860          * Program and erase have their own busy handlers status, sequential
 861          * in, and deplete1 need no delay.
 862          */
 863         switch (command) {
 864
 865         case NAND_CMD_CACHEDPROG:
 866         case NAND_CMD_PAGEPROG:
 867         case NAND_CMD_ERASE1:
 868         case NAND_CMD_ERASE2:
 869         case NAND_CMD_SEQIN:
 870         case NAND_CMD_RNDIN:
 871         case NAND_CMD_STATUS:
 872                 return;
 873
 874         case NAND_CMD_RESET:
 875                 if (chip->dev_ready)
 876                         break;
 877                 udelay(chip->chip_delay);
 878                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 879                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 880                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 881                                NAND_NCE | NAND_CTRL_CHANGE);
 882                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
 883                         (rst_sts_cnt--));
 884                 return;
 885
 886         case NAND_CMD_RNDOUT:
 887                 /* No ready / busy check necessary */
 888                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 889                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 890                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 891                                NAND_NCE | NAND_CTRL_CHANGE);
 892                 return;
 893
 894         case NAND_CMD_READ0:
 895                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 896                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 897                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 898                                NAND_NCE | NAND_CTRL_CHANGE);
 899
 900                 /* This applies to read commands */
 901         default:
 902                 /*
 903                  * If we don't have access to the busy pin, we apply the given
 904                  * command delay.
 905                  */
 906                 if (!chip->dev_ready) {
 907                         udelay(chip->chip_delay);
 908                         return;
 909                 }
 910         }
 911
 912         /*
 913          * Apply this short delay always to ensure that we do wait tWB in
 914          * any case on any machine.
 915          */
 916         ndelay(100);
 917
 918         nand_wait_ready(mtd);
 919 }
 920
 921 /**
 922  * panic_nand_get_device - [GENERIC] Get chip for selected access
 923  * @chip: the nand chip descriptor
 924  * @mtd: MTD device structure
 925  * @new_state: the state which is requested
 926  *
 927  * Used when in panic, no locks are taken.
 928  */
 929 static void panic_nand_get_device(struct nand_chip *chip,
 930                       struct mtd_info *mtd, int new_state)
 931 {
 932         /* Hardware controller shared among independent devices */
 933         chip->controller->active = chip;
 934         chip->state = new_state;
 935 }
 936
 937 /**
 938  * nand_get_device - [GENERIC] Get chip for selected access
 939  * @mtd: MTD device structure
 940  * @new_state: the state which is requested
 941  *
 942  * Get the device and lock it for exclusive access
 943  */
 944 static int
 945 nand_get_device(struct mtd_info *mtd, int new_state)
 946 {
 947         struct nand_chip *chip = mtd->priv;
 948 #ifndef __UBOOT__
 949         spinlock_t *lock = &chip->controller->lock;
 950         wait_queue_head_t *wq = &chip->controller->wq;
 951         DECLARE_WAITQUEUE(wait, current);
 952 retry:
 953         spin_lock(lock);
 954
 955         /* Hardware controller shared among independent devices */
 956         if (!chip->controller->active)
 957                 chip->controller->active = chip;
 958
 959         if (chip->controller->active == chip && chip->state == FL_READY) {
 960                 chip->state = new_state;
 961                 spin_unlock(lock);
 962                 return 0;
 963         }
 964         if (new_state == FL_PM_SUSPENDED) {
 965                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 966                         chip->state = FL_PM_SUSPENDED;
 967                         spin_unlock(lock);
 968                         return 0;
 969                 }
 970         }
 971         set_current_state(TASK_UNINTERRUPTIBLE);
 972         add_wait_queue(wq, &wait);
 973         spin_unlock(lock);
 974         schedule();
 975         remove_wait_queue(wq, &wait);
 976         goto retry;
 977 #else
 978         chip->state = new_state;
 979         return 0;
 980 #endif
 981 }
 982
 983 /**
 984  * panic_nand_wait - [GENERIC] wait until the command is done
 985  * @mtd: MTD device structure
 986  * @chip: NAND chip structure
 987  * @timeo: timeout
 988  *
 989  * Wait for command done. This is a helper function for nand_wait used when
 990  * we are in interrupt context. May happen when in panic and trying to write
 991  * an oops through mtdoops.
 992  */
 993 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 994                             unsigned long timeo)
 995 {
 996         int i;
 997         for (i = 0; i < timeo; i++) {
 998                 if (chip->dev_ready) {
 999                         if (chip->dev_ready(mtd))
1000                                 break;
1001                 } else {
1002                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
1003                                 break;
1004                 }
1005                 mdelay(1);
1006         }
1007 }
1008
1009 /**
1010  * nand_wait - [DEFAULT] wait until the command is done
1011  * @mtd: MTD device structure
1012  * @chip: NAND chip structure
1013  *
1014  * Wait for command done. This applies to erase and program only. Erase can
1015  * take up to 400ms and program up to 20ms according to general NAND and
1016  * SmartMedia specs.
1017  */
1018 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1019 {
1020
1021         int status, state = chip->state;
1022         unsigned long timeo = (state == FL_ERASING ? 400 : 20);
1023
1024         led_trigger_event(nand_led_trigger, LED_FULL);
1025
1026         /*
1027          * Apply this short delay always to ensure that we do wait tWB in any
1028          * case on any machine.
1029          */
1030         ndelay(100);
1031
1032         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1033
1034 #ifndef __UBOOT__
1035         if (in_interrupt() || oops_in_progress)
1036                 panic_nand_wait(mtd, chip, timeo);
1037         else {
1038                 timeo = jiffies + msecs_to_jiffies(timeo);
1039                 while (time_before(jiffies, timeo)) {
1040                         if (chip->dev_ready) {
1041                                 if (chip->dev_ready(mtd))
1042                                         break;
1043                         } else {
1044                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1045                                         break;
1046                         }
1047                         cond_resched();
1048                 }
1049         }
1050 #else
1051         u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1052         u32 time_start;
1053
1054         time_start = get_timer(0);
1055         while (get_timer(time_start) < timer) {
1056                 if (chip->dev_ready) {
1057                         if (chip->dev_ready(mtd))
1058                                 break;
1059                 } else {
1060                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
1061                                 break;
1062                 }
1063         }
1064 #endif
1065 #ifdef PPCHAMELON_NAND_TIMER_HACK
1066         time_start = get_timer(0);
1067         while (get_timer(time_start) < 10)
1068                 ;
1069 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
1070         led_trigger_event(nand_led_trigger, LED_OFF);
1071
1072         status = (int)chip->read_byte(mtd);
1073         /* This can happen if in case of timeout or buggy dev_ready */
1074         WARN_ON(!(status & NAND_STATUS_READY));
1075         return status;
1076 }
1077
1078 #ifndef __UBOOT__
1079 /**
1080  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1081  * @mtd: mtd info
1082  * @ofs: offset to start unlock from
1083  * @len: length to unlock
1084  * @invert: when = 0, unlock the range of blocks within the lower and
1085  *                    upper boundary address
1086  *          when = 1, unlock the range of blocks outside the boundaries
1087  *                    of the lower and upper boundary address
1088  *
1089  * Returs unlock status.
1090  */
1091 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1092                                         uint64_t len, int invert)
1093 {
1094         int ret = 0;
1095         int status, page;
1096         struct nand_chip *chip = mtd->priv;
1097
1098         /* Submit address of first page to unlock */
1099         page = ofs >> chip->page_shift;
1100         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1101
1102         /* Submit address of last page to unlock */
1103         page = (ofs + len) >> chip->page_shift;
1104         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1105                                 (page | invert) & chip->pagemask);
1106
1107         /* Call wait ready function */
1108         status = chip->waitfunc(mtd, chip);
1109         /* See if device thinks it succeeded */
1110         if (status & NAND_STATUS_FAIL) {
1111                 pr_debug("%s: error status = 0x%08x\n",
1112                                         __func__, status);
1113                 ret = -EIO;
1114         }
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1121  * @mtd: mtd info
1122  * @ofs: offset to start unlock from
1123  * @len: length to unlock
1124  *
1125  * Returns unlock status.
1126  */
1127 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1128 {
1129         int ret = 0;
1130         int chipnr;
1131         struct nand_chip *chip = mtd->priv;
1132
1133         pr_debug("%s: start = 0x%012llx, len = %llu\n",
1134                         __func__, (unsigned long long)ofs, len);
1135
1136         if (check_offs_len(mtd, ofs, len))
1137                 ret = -EINVAL;
1138
1139         /* Align to last block address if size addresses end of the device */
1140         if (ofs + len == mtd->size)
1141                 len -= mtd->erasesize;
1142
1143         nand_get_device(mtd, FL_UNLOCKING);
1144
1145         /* Shift to get chip number */
1146         chipnr = ofs >> chip->chip_shift;
1147
1148         chip->select_chip(mtd, chipnr);
1149
1150         /* Check, if it is write protected */
1151         if (nand_check_wp(mtd)) {
1152                 pr_debug("%s: device is write protected!\n",
1153                                         __func__);
1154                 ret = -EIO;
1155                 goto out;
1156         }
1157
1158         ret = __nand_unlock(mtd, ofs, len, 0);
1159
1160 out:
1161         chip->select_chip(mtd, -1);
1162         nand_release_device(mtd);
1163
1164         return ret;
1165 }
1166 EXPORT_SYMBOL(nand_unlock);
1167
1168 /**
1169  * nand_lock - [REPLACEABLE] locks all blocks present in the device
1170  * @mtd: mtd info
1171  * @ofs: offset to start unlock from
1172  * @len: length to unlock
1173  *
1174  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1175  * have this feature, but it allows only to lock all blocks, not for specified
1176  * range for block. Implementing 'lock' feature by making use of 'unlock', for
1177  * now.
1178  *
1179  * Returns lock status.
1180  */
1181 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1182 {
1183         int ret = 0;
1184         int chipnr, status, page;
1185         struct nand_chip *chip = mtd->priv;
1186
1187         pr_debug("%s: start = 0x%012llx, len = %llu\n",
1188                         __func__, (unsigned long long)ofs, len);
1189
1190         if (check_offs_len(mtd, ofs, len))
1191                 ret = -EINVAL;
1192
1193         nand_get_device(mtd, FL_LOCKING);
1194
1195         /* Shift to get chip number */
1196         chipnr = ofs >> chip->chip_shift;
1197
1198         chip->select_chip(mtd, chipnr);
1199
1200         /* Check, if it is write protected */
1201         if (nand_check_wp(mtd)) {
1202                 pr_debug("%s: device is write protected!\n",
1203                                         __func__);
1204                 status = MTD_ERASE_FAILED;
1205                 ret = -EIO;
1206                 goto out;
1207         }
1208
1209         /* Submit address of first page to lock */
1210         page = ofs >> chip->page_shift;
1211         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1212
1213         /* Call wait ready function */
1214         status = chip->waitfunc(mtd, chip);
1215         /* See if device thinks it succeeded */
1216         if (status & NAND_STATUS_FAIL) {
1217                 pr_debug("%s: error status = 0x%08x\n",
1218                                         __func__, status);
1219                 ret = -EIO;
1220                 goto out;
1221         }
1222
1223         ret = __nand_unlock(mtd, ofs, len, 0x1);
1224
1225 out:
1226         chip->select_chip(mtd, -1);
1227         nand_release_device(mtd);
1228
1229         return ret;
1230 }
1231 EXPORT_SYMBOL(nand_lock);
1232 #endif
1233
1234 /**
1235  * nand_read_page_raw - [INTERN] read raw page data without ecc
1236  * @mtd: mtd info structure
1237  * @chip: nand chip info structure
1238  * @buf: buffer to store read data
1239  * @oob_required: caller requires OOB data read to chip->oob_poi
1240  * @page: page number to read
1241  *
1242  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1243  */
1244 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1245                               uint8_t *buf, int oob_required, int page)
1246 {
1247         chip->read_buf(mtd, buf, mtd->writesize);
1248         if (oob_required)
1249                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1250         return 0;
1251 }
1252
1253 /**
1254  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1255  * @mtd: mtd info structure
1256  * @chip: nand chip info structure
1257  * @buf: buffer to store read data
1258  * @oob_required: caller requires OOB data read to chip->oob_poi
1259  * @page: page number to read
1260  *
1261  * We need a special oob layout and handling even when OOB isn't used.
1262  */
1263 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1264                                        struct nand_chip *chip, uint8_t *buf,
1265                                        int oob_required, int page)
1266 {
1267         int eccsize = chip->ecc.size;
1268         int eccbytes = chip->ecc.bytes;
1269         uint8_t *oob = chip->oob_poi;
1270         int steps, size;
1271
1272         for (steps = chip->ecc.steps; steps > 0; steps--) {
1273                 chip->read_buf(mtd, buf, eccsize);
1274                 buf += eccsize;
1275
1276                 if (chip->ecc.prepad) {
1277                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1278                         oob += chip->ecc.prepad;
1279                 }
1280
1281                 chip->read_buf(mtd, oob, eccbytes);
1282                 oob += eccbytes;
1283
1284                 if (chip->ecc.postpad) {
1285                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1286                         oob += chip->ecc.postpad;
1287                 }
1288         }
1289
1290         size = mtd->oobsize - (oob - chip->oob_poi);
1291         if (size)
1292                 chip->read_buf(mtd, oob, size);
1293
1294         return 0;
1295 }
1296
1297 /**
1298  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1299  * @mtd: mtd info structure
1300  * @chip: nand chip info structure
1301  * @buf: buffer to store read data
1302  * @oob_required: caller requires OOB data read to chip->oob_poi
1303  * @page: page number to read
1304  */
1305 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1306                                 uint8_t *buf, int oob_required, int page)
1307 {
1308         int i, eccsize = chip->ecc.size;
1309         int eccbytes = chip->ecc.bytes;
1310         int eccsteps = chip->ecc.steps;
1311         uint8_t *p = buf;
1312         uint8_t *ecc_calc = chip->buffers->ecccalc;
1313         uint8_t *ecc_code = chip->buffers->ecccode;
1314         uint32_t *eccpos = chip->ecc.layout->eccpos;
1315         unsigned int max_bitflips = 0;
1316
1317         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1318
1319         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1320                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1321
1322         for (i = 0; i < chip->ecc.total; i++)
1323                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1324
1325         eccsteps = chip->ecc.steps;
1326         p = buf;
1327
1328         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1329                 int stat;
1330
1331                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1332                 if (stat < 0) {
1333                         mtd->ecc_stats.failed++;
1334                 } else {
1335                         mtd->ecc_stats.corrected += stat;
1336                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1337                 }
1338         }
1339         return max_bitflips;
1340 }
1341
1342 /**
1343  * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1344  * @mtd: mtd info structure
1345  * @chip: nand chip info structure
1346  * @data_offs: offset of requested data within the page
1347  * @readlen: data length
1348  * @bufpoi: buffer to store read data
1349  * @page: page number to read
1350  */
1351 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1352                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1353                         int page)
1354 {
1355         int start_step, end_step, num_steps;
1356         uint32_t *eccpos = chip->ecc.layout->eccpos;
1357         uint8_t *p;
1358         int data_col_addr, i, gaps = 0;
1359         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1360         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1361         int index;
1362         unsigned int max_bitflips = 0;
1363
1364         /* Column address within the page aligned to ECC size (256bytes) */
1365         start_step = data_offs / chip->ecc.size;
1366         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1367         num_steps = end_step - start_step + 1;
1368         index = start_step * chip->ecc.bytes;
1369
1370         /* Data size aligned to ECC ecc.size */
1371         datafrag_len = num_steps * chip->ecc.size;
1372         eccfrag_len = num_steps * chip->ecc.bytes;
1373
1374         data_col_addr = start_step * chip->ecc.size;
1375         /* If we read not a page aligned data */
1376         if (data_col_addr != 0)
1377                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1378
1379         p = bufpoi + data_col_addr;
1380         chip->read_buf(mtd, p, datafrag_len);
1381
1382         /* Calculate ECC */
1383         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1384                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1385
1386         /*
1387          * The performance is faster if we position offsets according to
1388          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1389          */
1390         for (i = 0; i < eccfrag_len - 1; i++) {
1391                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1392                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1393                         gaps = 1;
1394                         break;
1395                 }
1396         }
1397         if (gaps) {
1398                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1399                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1400         } else {
1401                 /*
1402                  * Send the command to read the particular ECC bytes take care
1403                  * about buswidth alignment in read_buf.
1404                  */
1405                 aligned_pos = eccpos[index] & ~(busw - 1);
1406                 aligned_len = eccfrag_len;
1407                 if (eccpos[index] & (busw - 1))
1408                         aligned_len++;
1409                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1410                         aligned_len++;
1411
1412                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1413                                         mtd->writesize + aligned_pos, -1);
1414                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1415         }
1416
1417         for (i = 0; i < eccfrag_len; i++)
1418                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1419
1420         p = bufpoi + data_col_addr;
1421         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1422                 int stat;
1423
1424                 stat = chip->ecc.correct(mtd, p,
1425                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1426                 if (stat < 0) {
1427                         mtd->ecc_stats.failed++;
1428                 } else {
1429                         mtd->ecc_stats.corrected += stat;
1430                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1431                 }
1432         }
1433         return max_bitflips;
1434 }
1435
1436 /**
1437  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1438  * @mtd: mtd info structure
1439  * @chip: nand chip info structure
1440  * @buf: buffer to store read data
1441  * @oob_required: caller requires OOB data read to chip->oob_poi
1442  * @page: page number to read
1443  *
1444  * Not for syndrome calculating ECC controllers which need a special oob layout.
1445  */
1446 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1447                                 uint8_t *buf, int oob_required, int page)
1448 {
1449         int i, eccsize = chip->ecc.size;
1450         int eccbytes = chip->ecc.bytes;
1451         int eccsteps = chip->ecc.steps;
1452         uint8_t *p = buf;
1453         uint8_t *ecc_calc = chip->buffers->ecccalc;
1454         uint8_t *ecc_code = chip->buffers->ecccode;
1455         uint32_t *eccpos = chip->ecc.layout->eccpos;
1456         unsigned int max_bitflips = 0;
1457
1458         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1459                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1460                 chip->read_buf(mtd, p, eccsize);
1461                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1462         }
1463         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1464
1465         for (i = 0; i < chip->ecc.total; i++)
1466                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1467
1468         eccsteps = chip->ecc.steps;
1469         p = buf;
1470
1471         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1472                 int stat;
1473
1474                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1475                 if (stat < 0) {
1476                         mtd->ecc_stats.failed++;
1477                 } else {
1478                         mtd->ecc_stats.corrected += stat;
1479                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1480                 }
1481         }
1482         return max_bitflips;
1483 }
1484
1485 /**
1486  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1487  * @mtd: mtd info structure
1488  * @chip: nand chip info structure
1489  * @buf: buffer to store read data
1490  * @oob_required: caller requires OOB data read to chip->oob_poi
1491  * @page: page number to read
1492  *
1493  * Hardware ECC for large page chips, require OOB to be read first. For this
1494  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1495  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1496  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1497  * the data area, by overwriting the NAND manufacturer bad block markings.
1498  */
1499 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1500         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1501 {
1502         int i, eccsize = chip->ecc.size;
1503         int eccbytes = chip->ecc.bytes;
1504         int eccsteps = chip->ecc.steps;
1505         uint8_t *p = buf;
1506         uint8_t *ecc_code = chip->buffers->ecccode;
1507         uint32_t *eccpos = chip->ecc.layout->eccpos;
1508         uint8_t *ecc_calc = chip->buffers->ecccalc;
1509         unsigned int max_bitflips = 0;
1510
1511         /* Read the OOB area first */
1512         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1513         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1514         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1515
1516         for (i = 0; i < chip->ecc.total; i++)
1517                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1518
1519         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1520                 int stat;
1521
1522                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1523                 chip->read_buf(mtd, p, eccsize);
1524                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1525
1526                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1527                 if (stat < 0) {
1528                         mtd->ecc_stats.failed++;
1529                 } else {
1530                         mtd->ecc_stats.corrected += stat;
1531                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1532                 }
1533         }
1534         return max_bitflips;
1535 }
1536
1537 /**
1538  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1539  * @mtd: mtd info structure
1540  * @chip: nand chip info structure
1541  * @buf: buffer to store read data
1542  * @oob_required: caller requires OOB data read to chip->oob_poi
1543  * @page: page number to read
1544  *
1545  * The hw generator calculates the error syndrome automatically. Therefore we
1546  * need a special oob layout and handling.
1547  */
1548 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1549                                    uint8_t *buf, int oob_required, int page)
1550 {
1551         int i, eccsize = chip->ecc.size;
1552         int eccbytes = chip->ecc.bytes;
1553         int eccsteps = chip->ecc.steps;
1554         uint8_t *p = buf;
1555         uint8_t *oob = chip->oob_poi;
1556         unsigned int max_bitflips = 0;
1557
1558         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1559                 int stat;
1560
1561                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1562                 chip->read_buf(mtd, p, eccsize);
1563
1564                 if (chip->ecc.prepad) {
1565                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1566                         oob += chip->ecc.prepad;
1567                 }
1568
1569                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1570                 chip->read_buf(mtd, oob, eccbytes);
1571                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1572
1573                 if (stat < 0) {
1574                         mtd->ecc_stats.failed++;
1575                 } else {
1576                         mtd->ecc_stats.corrected += stat;
1577                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1578                 }
1579
1580                 oob += eccbytes;
1581
1582                 if (chip->ecc.postpad) {
1583                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1584                         oob += chip->ecc.postpad;
1585                 }
1586         }
1587
1588         /* Calculate remaining oob bytes */
1589         i = mtd->oobsize - (oob - chip->oob_poi);
1590         if (i)
1591                 chip->read_buf(mtd, oob, i);
1592
1593         return max_bitflips;
1594 }
1595
1596 /**
1597  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1598  * @chip: nand chip structure
1599  * @oob: oob destination address
1600  * @ops: oob ops structure
1601  * @len: size of oob to transfer
1602  */
1603 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1604                                   struct mtd_oob_ops *ops, size_t len)
1605 {
1606         switch (ops->mode) {
1607
1608         case MTD_OPS_PLACE_OOB:
1609         case MTD_OPS_RAW:
1610                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1611                 return oob + len;
1612
1613         case MTD_OPS_AUTO_OOB: {
1614                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1615                 uint32_t boffs = 0, roffs = ops->ooboffs;
1616                 size_t bytes = 0;
1617
1618                 for (; free->length && len; free++, len -= bytes) {
1619                         /* Read request not from offset 0? */
1620                         if (unlikely(roffs)) {
1621                                 if (roffs >= free->length) {
1622                                         roffs -= free->length;
1623                                         continue;
1624                                 }
1625                                 boffs = free->offset + roffs;
1626                                 bytes = min_t(size_t, len,
1627                                               (free->length - roffs));
1628                                 roffs = 0;
1629                         } else {
1630                                 bytes = min_t(size_t, len, free->length);
1631                                 boffs = free->offset;
1632                         }
1633                         memcpy(oob, chip->oob_poi + boffs, bytes);
1634                         oob += bytes;
1635                 }
1636                 return oob;
1637         }
1638         default:
1639                 BUG();
1640         }
1641         return NULL;
1642 }
1643
1644 /**
1645  * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1646  * @mtd: MTD device structure
1647  * @retry_mode: the retry mode to use
1648  *
1649  * Some vendors supply a special command to shift the Vt threshold, to be used
1650  * when there are too many bitflips in a page (i.e., ECC error). After setting
1651  * a new threshold, the host should retry reading the page.
1652  */
1653 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1654 {
1655         struct nand_chip *chip = mtd->priv;
1656
1657         pr_debug("setting READ RETRY mode %d\n", retry_mode);
1658
1659         if (retry_mode >= chip->read_retries)
1660                 return -EINVAL;
1661
1662         if (!chip->setup_read_retry)
1663                 return -EOPNOTSUPP;
1664
1665         return chip->setup_read_retry(mtd, retry_mode);
1666 }
1667
1668 /**
1669  * nand_do_read_ops - [INTERN] Read data with ECC
1670  * @mtd: MTD device structure
1671  * @from: offset to read from
1672  * @ops: oob ops structure
1673  *
1674  * Internal function. Called with chip held.
1675  */
1676 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1677                             struct mtd_oob_ops *ops)
1678 {
1679         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1680         struct nand_chip *chip = mtd->priv;
1681         int ret = 0;
1682         uint32_t readlen = ops->len;
1683         uint32_t oobreadlen = ops->ooblen;
1684         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1685                 mtd->oobavail : mtd->oobsize;
1686
1687         uint8_t *bufpoi, *oob, *buf;
1688         unsigned int max_bitflips = 0;
1689         int retry_mode = 0;
1690         bool ecc_fail = false;
1691
1692         chipnr = (int)(from >> chip->chip_shift);
1693         chip->select_chip(mtd, chipnr);
1694
1695         realpage = (int)(from >> chip->page_shift);
1696         page = realpage & chip->pagemask;
1697
1698         col = (int)(from & (mtd->writesize - 1));
1699
1700         buf = ops->datbuf;
1701         oob = ops->oobbuf;
1702         oob_required = oob ? 1 : 0;
1703
1704         while (1) {
1705                 unsigned int ecc_failures = mtd->ecc_stats.failed;
1706
1707                 WATCHDOG_RESET();
1708                 bytes = min(mtd->writesize - col, readlen);
1709                 aligned = (bytes == mtd->writesize);
1710
1711                 /* Is the current page in the buffer? */
1712                 if (realpage != chip->pagebuf || oob) {
1713                         bufpoi = aligned ? buf : chip->buffers->databuf;
1714
1715 read_retry:
1716                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1717
1718                         /*
1719                          * Now read the page into the buffer.  Absent an error,
1720                          * the read methods return max bitflips per ecc step.
1721                          */
1722                         if (unlikely(ops->mode == MTD_OPS_RAW))
1723                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1724                                                               oob_required,
1725                                                               page);
1726                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1727                                  !oob)
1728                                 ret = chip->ecc.read_subpage(mtd, chip,
1729                                                         col, bytes, bufpoi,
1730                                                         page);
1731                         else
1732                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1733                                                           oob_required, page);
1734                         if (ret < 0) {
1735                                 if (!aligned)
1736                                         /* Invalidate page cache */
1737                                         chip->pagebuf = -1;
1738                                 break;
1739                         }
1740
1741                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1742
1743                         /* Transfer not aligned data */
1744                         if (!aligned) {
1745                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1746                                     !(mtd->ecc_stats.failed - ecc_failures) &&
1747                                     (ops->mode != MTD_OPS_RAW)) {
1748                                         chip->pagebuf = realpage;
1749                                         chip->pagebuf_bitflips = ret;
1750                                 } else {
1751                                         /* Invalidate page cache */
1752                                         chip->pagebuf = -1;
1753                                 }
1754                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1755                         }
1756
1757                         if (unlikely(oob)) {
1758                                 int toread = min(oobreadlen, max_oobsize);
1759
1760                                 if (toread) {
1761                                         oob = nand_transfer_oob(chip,
1762                                                 oob, ops, toread);
1763                                         oobreadlen -= toread;
1764                                 }
1765                         }
1766
1767                         if (chip->options & NAND_NEED_READRDY) {
1768                                 /* Apply delay or wait for ready/busy pin */
1769                                 if (!chip->dev_ready)
1770                                         udelay(chip->chip_delay);
1771                                 else
1772                                         nand_wait_ready(mtd);
1773                         }
1774
1775                         if (mtd->ecc_stats.failed - ecc_failures) {
1776                                 if (retry_mode + 1 < chip->read_retries) {
1777                                         retry_mode++;
1778                                         ret = nand_setup_read_retry(mtd,
1779                                                         retry_mode);
1780                                         if (ret < 0)
1781                                                 break;
1782
1783                                         /* Reset failures; retry */
1784                                         mtd->ecc_stats.failed = ecc_failures;
1785                                         goto read_retry;
1786                                 } else {
1787                                         /* No more retry modes; real failure */
1788                                         ecc_fail = true;
1789                                 }
1790                         }
1791
1792                         buf += bytes;
1793                 } else {
1794                         memcpy(buf, chip->buffers->databuf + col, bytes);
1795                         buf += bytes;
1796                         max_bitflips = max_t(unsigned int, max_bitflips,
1797                                              chip->pagebuf_bitflips);
1798                 }
1799
1800                 readlen -= bytes;
1801
1802                 /* Reset to retry mode 0 */
1803                 if (retry_mode) {
1804                         ret = nand_setup_read_retry(mtd, 0);
1805                         if (ret < 0)
1806                                 break;
1807                         retry_mode = 0;
1808                 }
1809
1810                 if (!readlen)
1811                         break;
1812
1813                 /* For subsequent reads align to page boundary */
1814                 col = 0;
1815                 /* Increment page address */
1816                 realpage++;
1817
1818                 page = realpage & chip->pagemask;
1819                 /* Check, if we cross a chip boundary */
1820                 if (!page) {
1821                         chipnr++;
1822                         chip->select_chip(mtd, -1);
1823                         chip->select_chip(mtd, chipnr);
1824                 }
1825         }
1826         chip->select_chip(mtd, -1);
1827
1828         ops->retlen = ops->len - (size_t) readlen;
1829         if (oob)
1830                 ops->oobretlen = ops->ooblen - oobreadlen;
1831
1832         if (ret < 0)
1833                 return ret;
1834
1835         if (ecc_fail)
1836                 return -EBADMSG;
1837
1838         return max_bitflips;
1839 }
1840
1841 /**
1842  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1843  * @mtd: MTD device structure
1844  * @from: offset to read from
1845  * @len: number of bytes to read
1846  * @retlen: pointer to variable to store the number of read bytes
1847  * @buf: the databuffer to put data
1848  *
1849  * Get hold of the chip and call nand_do_read.
1850  */
1851 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1852                      size_t *retlen, uint8_t *buf)
1853 {
1854         struct mtd_oob_ops ops;
1855         int ret;
1856
1857         nand_get_device(mtd, FL_READING);
1858         ops.len = len;
1859         ops.datbuf = buf;
1860         ops.oobbuf = NULL;
1861         ops.mode = MTD_OPS_PLACE_OOB;
1862         ret = nand_do_read_ops(mtd, from, &ops);
1863         *retlen = ops.retlen;
1864         nand_release_device(mtd);
1865         return ret;
1866 }
1867
1868 /**
1869  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1870  * @mtd: mtd info structure
1871  * @chip: nand chip info structure
1872  * @page: page number to read
1873  */
1874 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1875                              int page)
1876 {
1877         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1878         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1879         return 0;
1880 }
1881
1882 /**
1883  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1884  *                          with syndromes
1885  * @mtd: mtd info structure
1886  * @chip: nand chip info structure
1887  * @page: page number to read
1888  */
1889 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1890                                   int page)
1891 {
1892         uint8_t *buf = chip->oob_poi;
1893         int length = mtd->oobsize;
1894         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1895         int eccsize = chip->ecc.size;
1896         uint8_t *bufpoi = buf;
1897         int i, toread, sndrnd = 0, pos;
1898
1899         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1900         for (i = 0; i < chip->ecc.steps; i++) {
1901                 if (sndrnd) {
1902                         pos = eccsize + i * (eccsize + chunk);
1903                         if (mtd->writesize > 512)
1904                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1905                         else
1906                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1907                 } else
1908                         sndrnd = 1;
1909                 toread = min_t(int, length, chunk);
1910                 chip->read_buf(mtd, bufpoi, toread);
1911                 bufpoi += toread;
1912                 length -= toread;
1913         }
1914         if (length > 0)
1915                 chip->read_buf(mtd, bufpoi, length);
1916
1917         return 0;
1918 }
1919
1920 /**
1921  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1922  * @mtd: mtd info structure
1923  * @chip: nand chip info structure
1924  * @page: page number to write
1925  */
1926 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1927                               int page)
1928 {
1929         int status = 0;
1930         const uint8_t *buf = chip->oob_poi;
1931         int length = mtd->oobsize;
1932
1933         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1934         chip->write_buf(mtd, buf, length);
1935         /* Send command to program the OOB data */
1936         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1937
1938         status = chip->waitfunc(mtd, chip);
1939
1940         return status & NAND_STATUS_FAIL ? -EIO : 0;
1941 }
1942
1943 /**
1944  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1945  *                           with syndrome - only for large page flash
1946  * @mtd: mtd info structure
1947  * @chip: nand chip info structure
1948  * @page: page number to write
1949  */
1950 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1951                                    struct nand_chip *chip, int page)
1952 {
1953         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1954         int eccsize = chip->ecc.size, length = mtd->oobsize;
1955         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1956         const uint8_t *bufpoi = chip->oob_poi;
1957
1958         /*
1959          * data-ecc-data-ecc ... ecc-oob
1960          * or
1961          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1962          */
1963         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1964                 pos = steps * (eccsize + chunk);
1965                 steps = 0;
1966         } else
1967                 pos = eccsize;
1968
1969         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1970         for (i = 0; i < steps; i++) {
1971                 if (sndcmd) {
1972                         if (mtd->writesize <= 512) {
1973                                 uint32_t fill = 0xFFFFFFFF;
1974
1975                                 len = eccsize;
1976                                 while (len > 0) {
1977                                         int num = min_t(int, len, 4);
1978                                         chip->write_buf(mtd, (uint8_t *)&fill,
1979                                                         num);
1980                                         len -= num;
1981                                 }
1982                         } else {
1983                                 pos = eccsize + i * (eccsize + chunk);
1984                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1985                         }
1986                 } else
1987                         sndcmd = 1;
1988                 len = min_t(int, length, chunk);
1989                 chip->write_buf(mtd, bufpoi, len);
1990                 bufpoi += len;
1991                 length -= len;
1992         }
1993         if (length > 0)
1994                 chip->write_buf(mtd, bufpoi, length);
1995
1996         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1997         status = chip->waitfunc(mtd, chip);
1998
1999         return status & NAND_STATUS_FAIL ? -EIO : 0;
2000 }
2001
2002 /**
2003  * nand_do_read_oob - [INTERN] NAND read out-of-band
2004  * @mtd: MTD device structure
2005  * @from: offset to read from
2006  * @ops: oob operations description structure
2007  *
2008  * NAND read out-of-band data from the spare area.
2009  */
2010 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
2011                             struct mtd_oob_ops *ops)
2012 {
2013         int page, realpage, chipnr;
2014         struct nand_chip *chip = mtd->priv;
2015         struct mtd_ecc_stats stats;
2016         int readlen = ops->ooblen;
2017         int len;
2018         uint8_t *buf = ops->oobbuf;
2019         int ret = 0;
2020
2021         pr_debug("%s: from = 0x%08Lx, len = %i\n",
2022                         __func__, (unsigned long long)from, readlen);
2023
2024         stats = mtd->ecc_stats;
2025
2026         if (ops->mode == MTD_OPS_AUTO_OOB)
2027                 len = chip->ecc.layout->oobavail;
2028         else
2029                 len = mtd->oobsize;
2030
2031         if (unlikely(ops->ooboffs >= len)) {
2032                 pr_debug("%s: attempt to start read outside oob\n",
2033                                 __func__);
2034                 return -EINVAL;
2035         }
2036
2037         /* Do not allow reads past end of device */
2038         if (unlikely(from >= mtd->size ||
2039                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
2040                                         (from >> chip->page_shift)) * len)) {
2041                 pr_debug("%s: attempt to read beyond end of device\n",
2042                                 __func__);
2043                 return -EINVAL;
2044         }
2045
2046         chipnr = (int)(from >> chip->chip_shift);
2047         chip->select_chip(mtd, chipnr);
2048
2049         /* Shift to get page */
2050         realpage = (int)(from >> chip->page_shift);
2051         page = realpage & chip->pagemask;
2052
2053         while (1) {
2054                 WATCHDOG_RESET();
2055
2056                 if (ops->mode == MTD_OPS_RAW)
2057                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
2058                 else
2059                         ret = chip->ecc.read_oob(mtd, chip, page);
2060
2061                 if (ret < 0)
2062                         break;
2063
2064                 len = min(len, readlen);
2065                 buf = nand_transfer_oob(chip, buf, ops, len);
2066
2067                 if (chip->options & NAND_NEED_READRDY) {
2068                         /* Apply delay or wait for ready/busy pin */
2069                         if (!chip->dev_ready)
2070                                 udelay(chip->chip_delay);
2071                         else
2072                                 nand_wait_ready(mtd);
2073                 }
2074
2075                 readlen -= len;
2076                 if (!readlen)
2077                         break;
2078
2079                 /* Increment page address */
2080                 realpage++;
2081
2082                 page = realpage & chip->pagemask;
2083                 /* Check, if we cross a chip boundary */
2084                 if (!page) {
2085                         chipnr++;
2086                         chip->select_chip(mtd, -1);
2087                         chip->select_chip(mtd, chipnr);
2088                 }
2089         }
2090         chip->select_chip(mtd, -1);
2091
2092         ops->oobretlen = ops->ooblen - readlen;
2093
2094         if (ret < 0)
2095                 return ret;
2096
2097         if (mtd->ecc_stats.failed - stats.failed)
2098                 return -EBADMSG;
2099
2100         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2101 }
2102
2103 /**
2104  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2105  * @mtd: MTD device structure
2106  * @from: offset to read from
2107  * @ops: oob operation description structure
2108  *
2109  * NAND read data and/or out-of-band data.
2110  */
2111 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2112                          struct mtd_oob_ops *ops)
2113 {
2114         int ret = -ENOTSUPP;
2115
2116         ops->retlen = 0;
2117
2118         /* Do not allow reads past end of device */
2119         if (ops->datbuf && (from + ops->len) > mtd->size) {
2120                 pr_debug("%s: attempt to read beyond end of device\n",
2121                                 __func__);
2122                 return -EINVAL;
2123         }
2124
2125         nand_get_device(mtd, FL_READING);
2126
2127         switch (ops->mode) {
2128         case MTD_OPS_PLACE_OOB:
2129         case MTD_OPS_AUTO_OOB:
2130         case MTD_OPS_RAW:
2131                 break;
2132
2133         default:
2134                 goto out;
2135         }
2136
2137         if (!ops->datbuf)
2138                 ret = nand_do_read_oob(mtd, from, ops);
2139         else
2140                 ret = nand_do_read_ops(mtd, from, ops);
2141
2142 out:
2143         nand_release_device(mtd);
2144         return ret;
2145 }
2146
2147
2148 /**
2149  * nand_write_page_raw - [INTERN] raw page write function
2150  * @mtd: mtd info structure
2151  * @chip: nand chip info structure
2152  * @buf: data buffer
2153  * @oob_required: must write chip->oob_poi to OOB
2154  *
2155  * Not for syndrome calculating ECC controllers, which use a special oob layout.
2156  */
2157 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2158                                 const uint8_t *buf, int oob_required)
2159 {
2160         chip->write_buf(mtd, buf, mtd->writesize);
2161         if (oob_required)
2162                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2163
2164         return 0;
2165 }
2166
2167 /**
2168  * nand_write_page_raw_syndrome - [INTERN] raw page write function
2169  * @mtd: mtd info structure
2170  * @chip: nand chip info structure
2171  * @buf: data buffer
2172  * @oob_required: must write chip->oob_poi to OOB
2173  *
2174  * We need a special oob layout and handling even when ECC isn't checked.
2175  */
2176 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2177                                         struct nand_chip *chip,
2178                                         const uint8_t *buf, int oob_required)
2179 {
2180         int eccsize = chip->ecc.size;
2181         int eccbytes = chip->ecc.bytes;
2182         uint8_t *oob = chip->oob_poi;
2183         int steps, size;
2184
2185         for (steps = chip->ecc.steps; steps > 0; steps--) {
2186                 chip->write_buf(mtd, buf, eccsize);
2187                 buf += eccsize;
2188
2189                 if (chip->ecc.prepad) {
2190                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2191                         oob += chip->ecc.prepad;
2192                 }
2193
2194                 chip->write_buf(mtd, oob, eccbytes);
2195                 oob += eccbytes;
2196
2197                 if (chip->ecc.postpad) {
2198                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2199                         oob += chip->ecc.postpad;
2200                 }
2201         }
2202
2203         size = mtd->oobsize - (oob - chip->oob_poi);
2204         if (size)
2205                 chip->write_buf(mtd, oob, size);
2206
2207         return 0;
2208 }
2209 /**
2210  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2211  * @mtd: mtd info structure
2212  * @chip: nand chip info structure
2213  * @buf: data buffer
2214  * @oob_required: must write chip->oob_poi to OOB
2215  */
2216 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2217                                   const uint8_t *buf, int oob_required)
2218 {
2219         int i, eccsize = chip->ecc.size;
2220         int eccbytes = chip->ecc.bytes;
2221         int eccsteps = chip->ecc.steps;
2222         uint8_t *ecc_calc = chip->buffers->ecccalc;
2223         const uint8_t *p = buf;
2224         uint32_t *eccpos = chip->ecc.layout->eccpos;
2225
2226         /* Software ECC calculation */
2227         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2228                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2229
2230         for (i = 0; i < chip->ecc.total; i++)
2231                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2232
2233         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2234 }
2235
2236 /**
2237  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2238  * @mtd: mtd info structure
2239  * @chip: nand chip info structure
2240  * @buf: data buffer
2241  * @oob_required: must write chip->oob_poi to OOB
2242  */
2243 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2244                                   const uint8_t *buf, int oob_required)
2245 {
2246         int i, eccsize = chip->ecc.size;
2247         int eccbytes = chip->ecc.bytes;
2248         int eccsteps = chip->ecc.steps;
2249         uint8_t *ecc_calc = chip->buffers->ecccalc;
2250         const uint8_t *p = buf;
2251         uint32_t *eccpos = chip->ecc.layout->eccpos;
2252
2253         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2254                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2255                 chip->write_buf(mtd, p, eccsize);
2256                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2257         }
2258
2259         for (i = 0; i < chip->ecc.total; i++)
2260                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2261
2262         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2263
2264         return 0;
2265 }
2266
2267
2268 /**
2269  * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2270  * @mtd:        mtd info structure
2271  * @chip:       nand chip info structure
2272  * @offset:     column address of subpage within the page
2273  * @data_len:   data length
2274  * @buf:        data buffer
2275  * @oob_required: must write chip->oob_poi to OOB
2276  */
2277 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2278                                 struct nand_chip *chip, uint32_t offset,
2279                                 uint32_t data_len, const uint8_t *buf,
2280                                 int oob_required)
2281 {
2282         uint8_t *oob_buf  = chip->oob_poi;
2283         uint8_t *ecc_calc = chip->buffers->ecccalc;
2284         int ecc_size      = chip->ecc.size;
2285         int ecc_bytes     = chip->ecc.bytes;
2286         int ecc_steps     = chip->ecc.steps;
2287         uint32_t *eccpos  = chip->ecc.layout->eccpos;
2288         uint32_t start_step = offset / ecc_size;
2289         uint32_t end_step   = (offset + data_len - 1) / ecc_size;
2290         int oob_bytes       = mtd->oobsize / ecc_steps;
2291         int step, i;
2292
2293         for (step = 0; step < ecc_steps; step++) {
2294                 /* configure controller for WRITE access */
2295                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2296
2297                 /* write data (untouched subpages already masked by 0xFF) */
2298                 chip->write_buf(mtd, buf, ecc_size);
2299
2300                 /* mask ECC of un-touched subpages by padding 0xFF */
2301                 if ((step < start_step) || (step > end_step))
2302                         memset(ecc_calc, 0xff, ecc_bytes);
2303                 else
2304                         chip->ecc.calculate(mtd, buf, ecc_calc);
2305
2306                 /* mask OOB of un-touched subpages by padding 0xFF */
2307                 /* if oob_required, preserve OOB metadata of written subpage */
2308                 if (!oob_required || (step < start_step) || (step > end_step))
2309                         memset(oob_buf, 0xff, oob_bytes);
2310
2311                 buf += ecc_size;
2312                 ecc_calc += ecc_bytes;
2313                 oob_buf  += oob_bytes;
2314         }
2315
2316         /* copy calculated ECC for whole page to chip->buffer->oob */
2317         /* this include masked-value(0xFF) for unwritten subpages */
2318         ecc_calc = chip->buffers->ecccalc;
2319         for (i = 0; i < chip->ecc.total; i++)
2320                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2321
2322         /* write OOB buffer to NAND device */
2323         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2324
2325         return 0;
2326 }
2327
2328
2329 /**
2330  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2331  * @mtd: mtd info structure
2332  * @chip: nand chip info structure
2333  * @buf: data buffer
2334  * @oob_required: must write chip->oob_poi to OOB
2335  *
2336  * The hw generator calculates the error syndrome automatically. Therefore we
2337  * need a special oob layout and handling.
2338  */
2339 static int nand_write_page_syndrome(struct mtd_info *mtd,
2340                                     struct nand_chip *chip,
2341                                     const uint8_t *buf, int oob_required)
2342 {
2343         int i, eccsize = chip->ecc.size;
2344         int eccbytes = chip->ecc.bytes;
2345         int eccsteps = chip->ecc.steps;
2346         const uint8_t *p = buf;
2347         uint8_t *oob = chip->oob_poi;
2348
2349         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2350
2351                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2352                 chip->write_buf(mtd, p, eccsize);
2353
2354                 if (chip->ecc.prepad) {
2355                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2356                         oob += chip->ecc.prepad;
2357                 }
2358
2359                 chip->ecc.calculate(mtd, p, oob);
2360                 chip->write_buf(mtd, oob, eccbytes);
2361                 oob += eccbytes;
2362
2363                 if (chip->ecc.postpad) {
2364                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2365                         oob += chip->ecc.postpad;
2366                 }
2367         }
2368
2369         /* Calculate remaining oob bytes */
2370         i = mtd->oobsize - (oob - chip->oob_poi);
2371         if (i)
2372                 chip->write_buf(mtd, oob, i);
2373
2374         return 0;
2375 }
2376
2377 /**
2378  * nand_write_page - [REPLACEABLE] write one page
2379  * @mtd: MTD device structure
2380  * @chip: NAND chip descriptor
2381  * @offset: address offset within the page
2382  * @data_len: length of actual data to be written
2383  * @buf: the data to write
2384  * @oob_required: must write chip->oob_poi to OOB
2385  * @page: page number to write
2386  * @cached: cached programming
2387  * @raw: use _raw version of write_page
2388  */
2389 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2390                 uint32_t offset, int data_len, const uint8_t *buf,
2391                 int oob_required, int page, int cached, int raw)
2392 {
2393         int status, subpage;
2394
2395         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2396                 chip->ecc.write_subpage)
2397                 subpage = offset || (data_len < mtd->writesize);
2398         else
2399                 subpage = 0;
2400
2401         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2402
2403         if (unlikely(raw))
2404                 status = chip->ecc.write_page_raw(mtd, chip, buf,
2405                                                         oob_required);
2406         else if (subpage)
2407                 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2408                                                          buf, oob_required);
2409         else
2410                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2411
2412         if (status < 0)
2413                 return status;
2414
2415         /*
2416          * Cached progamming disabled for now. Not sure if it's worth the
2417          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2418          */
2419         cached = 0;
2420
2421         if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2422
2423                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2424                 status = chip->waitfunc(mtd, chip);
2425                 /*
2426                  * See if operation failed and additional status checks are
2427                  * available.
2428                  */
2429                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2430                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2431                                                page);
2432
2433                 if (status & NAND_STATUS_FAIL)
2434                         return -EIO;
2435         } else {
2436                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2437                 status = chip->waitfunc(mtd, chip);
2438         }
2439
2440
2441 #ifdef __UBOOT__
2442 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
2443         /* Send command to read back the data */
2444         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2445
2446         if (chip->verify_buf(mtd, buf, mtd->writesize))
2447                 return -EIO;
2448
2449         /* Make sure the next page prog is preceded by a status read */
2450         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
2451 #endif
2452 #endif
2453
2454         return 0;
2455 }
2456
2457 /**
2458  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2459  * @mtd: MTD device structure
2460  * @oob: oob data buffer
2461  * @len: oob data write length
2462  * @ops: oob ops structure
2463  */
2464 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2465                               struct mtd_oob_ops *ops)
2466 {
2467         struct nand_chip *chip = mtd->priv;
2468
2469         /*
2470          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2471          * data from a previous OOB read.
2472          */
2473         memset(chip->oob_poi, 0xff, mtd->oobsize);
2474
2475         switch (ops->mode) {
2476
2477         case MTD_OPS_PLACE_OOB:
2478         case MTD_OPS_RAW:
2479                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2480                 return oob + len;
2481
2482         case MTD_OPS_AUTO_OOB: {
2483                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2484                 uint32_t boffs = 0, woffs = ops->ooboffs;
2485                 size_t bytes = 0;
2486
2487                 for (; free->length && len; free++, len -= bytes) {
2488                         /* Write request not from offset 0? */
2489                         if (unlikely(woffs)) {
2490                                 if (woffs >= free->length) {
2491                                         woffs -= free->length;
2492                                         continue;
2493                                 }
2494                                 boffs = free->offset + woffs;
2495                                 bytes = min_t(size_t, len,
2496                                               (free->length - woffs));
2497                                 woffs = 0;
2498                         } else {
2499                                 bytes = min_t(size_t, len, free->length);
2500                                 boffs = free->offset;
2501                         }
2502                         memcpy(chip->oob_poi + boffs, oob, bytes);
2503                         oob += bytes;
2504                 }
2505                 return oob;
2506         }
2507         default:
2508                 BUG();
2509         }
2510         return NULL;
2511 }
2512
2513 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2514
2515 /**
2516  * nand_do_write_ops - [INTERN] NAND write with ECC
2517  * @mtd: MTD device structure
2518  * @to: offset to write to
2519  * @ops: oob operations description structure
2520  *
2521  * NAND write with ECC.
2522  */
2523 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2524                              struct mtd_oob_ops *ops)
2525 {
2526         int chipnr, realpage, page, blockmask, column;
2527         struct nand_chip *chip = mtd->priv;
2528         uint32_t writelen = ops->len;
2529
2530         uint32_t oobwritelen = ops->ooblen;
2531         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2532                                 mtd->oobavail : mtd->oobsize;
2533
2534         uint8_t *oob = ops->oobbuf;
2535         uint8_t *buf = ops->datbuf;
2536         int ret;
2537         int oob_required = oob ? 1 : 0;
2538
2539         ops->retlen = 0;
2540         if (!writelen)
2541                 return 0;
2542
2543 #ifndef __UBOOT__
2544         /* Reject writes, which are not page aligned */
2545         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2546 #else
2547         /* Reject writes, which are not page aligned */
2548         if (NOTALIGNED(to)) {
2549 #endif
2550                 pr_notice("%s: attempt to write non page aligned data\n",
2551                            __func__);
2552                 return -EINVAL;
2553         }
2554
2555         column = to & (mtd->writesize - 1);
2556
2557         chipnr = (int)(to >> chip->chip_shift);
2558         chip->select_chip(mtd, chipnr);
2559
2560         /* Check, if it is write protected */
2561         if (nand_check_wp(mtd)) {
2562                 ret = -EIO;
2563                 goto err_out;
2564         }
2565
2566         realpage = (int)(to >> chip->page_shift);
2567         page = realpage & chip->pagemask;
2568         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2569
2570         /* Invalidate the page cache, when we write to the cached page */
2571         if (to <= (chip->pagebuf << chip->page_shift) &&
2572             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2573                 chip->pagebuf = -1;
2574
2575         /* Don't allow multipage oob writes with offset */
2576         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2577                 ret = -EINVAL;
2578                 goto err_out;
2579         }
2580
2581         while (1) {
2582                 int bytes = mtd->writesize;
2583                 int cached = writelen > bytes && page != blockmask;
2584                 uint8_t *wbuf = buf;
2585
2586                 WATCHDOG_RESET();
2587                 /* Partial page write? */
2588                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2589                         cached = 0;
2590                         bytes = min_t(int, bytes - column, (int) writelen);
2591                         chip->pagebuf = -1;
2592                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2593                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2594                         wbuf = chip->buffers->databuf;
2595                 }
2596
2597                 if (unlikely(oob)) {
2598                         size_t len = min(oobwritelen, oobmaxlen);
2599                         oob = nand_fill_oob(mtd, oob, len, ops);
2600                         oobwritelen -= len;
2601                 } else {
2602                         /* We still need to erase leftover OOB data */
2603                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2604                 }
2605                 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2606                                         oob_required, page, cached,
2607                                         (ops->mode == MTD_OPS_RAW));
2608                 if (ret)
2609                         break;
2610
2611                 writelen -= bytes;
2612                 if (!writelen)
2613                         break;
2614
2615                 column = 0;
2616                 buf += bytes;
2617                 realpage++;
2618
2619                 page = realpage & chip->pagemask;
2620                 /* Check, if we cross a chip boundary */
2621                 if (!page) {
2622                         chipnr++;
2623                         chip->select_chip(mtd, -1);
2624                         chip->select_chip(mtd, chipnr);
2625                 }
2626         }
2627
2628         ops->retlen = ops->len - writelen;
2629         if (unlikely(oob))
2630                 ops->oobretlen = ops->ooblen;
2631
2632 err_out:
2633         chip->select_chip(mtd, -1);
2634         return ret;
2635 }
2636
2637 /**
2638  * panic_nand_write - [MTD Interface] NAND write with ECC
2639  * @mtd: MTD device structure
2640  * @to: offset to write to
2641  * @len: number of bytes to write
2642  * @retlen: pointer to variable to store the number of written bytes
2643  * @buf: the data to write
2644  *
2645  * NAND write with ECC. Used when performing writes in interrupt context, this
2646  * may for example be called by mtdoops when writing an oops while in panic.
2647  */
2648 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2649                             size_t *retlen, const uint8_t *buf)
2650 {
2651         struct nand_chip *chip = mtd->priv;
2652         struct mtd_oob_ops ops;
2653         int ret;
2654
2655         /* Wait for the device to get ready */
2656         panic_nand_wait(mtd, chip, 400);
2657
2658         /* Grab the device */
2659         panic_nand_get_device(chip, mtd, FL_WRITING);
2660
2661         ops.len = len;
2662         ops.datbuf = (uint8_t *)buf;
2663         ops.oobbuf = NULL;
2664         ops.mode = MTD_OPS_PLACE_OOB;
2665
2666         ret = nand_do_write_ops(mtd, to, &ops);
2667
2668         *retlen = ops.retlen;
2669         return ret;
2670 }
2671
2672 /**
2673  * nand_write - [MTD Interface] NAND write with ECC
2674  * @mtd: MTD device structure
2675  * @to: offset to write to
2676  * @len: number of bytes to write
2677  * @retlen: pointer to variable to store the number of written bytes
2678  * @buf: the data to write
2679  *
2680  * NAND write with ECC.
2681  */
2682 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2683                           size_t *retlen, const uint8_t *buf)
2684 {
2685         struct mtd_oob_ops ops;
2686         int ret;
2687
2688         nand_get_device(mtd, FL_WRITING);
2689         ops.len = len;
2690         ops.datbuf = (uint8_t *)buf;
2691         ops.oobbuf = NULL;
2692         ops.mode = MTD_OPS_PLACE_OOB;
2693         ret = nand_do_write_ops(mtd, to, &ops);
2694         *retlen = ops.retlen;
2695         nand_release_device(mtd);
2696         return ret;
2697 }
2698
2699 /**
2700  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2701  * @mtd: MTD device structure
2702  * @to: offset to write to
2703  * @ops: oob operation description structure
2704  *
2705  * NAND write out-of-band.
2706  */
2707 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2708                              struct mtd_oob_ops *ops)
2709 {
2710         int chipnr, page, status, len;
2711         struct nand_chip *chip = mtd->priv;
2712
2713         pr_debug("%s: to = 0x%08x, len = %i\n",
2714                          __func__, (unsigned int)to, (int)ops->ooblen);
2715
2716         if (ops->mode == MTD_OPS_AUTO_OOB)
2717                 len = chip->ecc.layout->oobavail;
2718         else
2719                 len = mtd->oobsize;
2720
2721         /* Do not allow write past end of page */
2722         if ((ops->ooboffs + ops->ooblen) > len) {
2723                 pr_debug("%s: attempt to write past end of page\n",
2724                                 __func__);
2725                 return -EINVAL;
2726         }
2727
2728         if (unlikely(ops->ooboffs >= len)) {
2729                 pr_debug("%s: attempt to start write outside oob\n",
2730                                 __func__);
2731                 return -EINVAL;
2732         }
2733
2734         /* Do not allow write past end of device */
2735         if (unlikely(to >= mtd->size ||
2736                      ops->ooboffs + ops->ooblen >
2737                         ((mtd->size >> chip->page_shift) -
2738                          (to >> chip->page_shift)) * len)) {
2739                 pr_debug("%s: attempt to write beyond end of device\n",
2740                                 __func__);
2741                 return -EINVAL;
2742         }
2743
2744         chipnr = (int)(to >> chip->chip_shift);
2745         chip->select_chip(mtd, chipnr);
2746
2747         /* Shift to get page */
2748         page = (int)(to >> chip->page_shift);
2749
2750         /*
2751          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2752          * of my DiskOnChip 2000 test units) will clear the whole data page too
2753          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2754          * it in the doc2000 driver in August 1999.  dwmw2.
2755          */
2756         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2757
2758         /* Check, if it is write protected */
2759         if (nand_check_wp(mtd)) {
2760                 chip->select_chip(mtd, -1);
2761                 return -EROFS;
2762         }
2763
2764         /* Invalidate the page cache, if we write to the cached page */
2765         if (page == chip->pagebuf)
2766                 chip->pagebuf = -1;
2767
2768         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2769
2770         if (ops->mode == MTD_OPS_RAW)
2771                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2772         else
2773                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2774
2775         chip->select_chip(mtd, -1);
2776
2777         if (status)
2778                 return status;
2779
2780         ops->oobretlen = ops->ooblen;
2781
2782         return 0;
2783 }
2784
2785 /**
2786  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2787  * @mtd: MTD device structure
2788  * @to: offset to write to
2789  * @ops: oob operation description structure
2790  */
2791 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2792                           struct mtd_oob_ops *ops)
2793 {
2794         int ret = -ENOTSUPP;
2795
2796         ops->retlen = 0;
2797
2798         /* Do not allow writes past end of device */
2799         if (ops->datbuf && (to + ops->len) > mtd->size) {
2800                 pr_debug("%s: attempt to write beyond end of device\n",
2801                                 __func__);
2802                 return -EINVAL;
2803         }
2804
2805         nand_get_device(mtd, FL_WRITING);
2806
2807         switch (ops->mode) {
2808         case MTD_OPS_PLACE_OOB:
2809         case MTD_OPS_AUTO_OOB:
2810         case MTD_OPS_RAW:
2811                 break;
2812
2813         default:
2814                 goto out;
2815         }
2816
2817         if (!ops->datbuf)
2818                 ret = nand_do_write_oob(mtd, to, ops);
2819         else
2820                 ret = nand_do_write_ops(mtd, to, ops);
2821
2822 out:
2823         nand_release_device(mtd);
2824         return ret;
2825 }
2826
2827 /**
2828  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2829  * @mtd: MTD device structure
2830  * @page: the page address of the block which will be erased
2831  *
2832  * Standard erase command for NAND chips.
2833  */
2834 static void single_erase_cmd(struct mtd_info *mtd, int page)
2835 {
2836         struct nand_chip *chip = mtd->priv;
2837         /* Send commands to erase a block */
2838         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2839         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2840 }
2841
2842 /**
2843  * nand_erase - [MTD Interface] erase block(s)
2844  * @mtd: MTD device structure
2845  * @instr: erase instruction
2846  *
2847  * Erase one ore more blocks.
2848  */
2849 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2850 {
2851         return nand_erase_nand(mtd, instr, 0);
2852 }
2853
2854 /**
2855  * nand_erase_nand - [INTERN] erase block(s)
2856  * @mtd: MTD device structure
2857  * @instr: erase instruction
2858  * @allowbbt: allow erasing the bbt area
2859  *
2860  * Erase one ore more blocks.
2861  */
2862 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2863                     int allowbbt)
2864 {
2865         int page, status, pages_per_block, ret, chipnr;
2866         struct nand_chip *chip = mtd->priv;
2867         loff_t len;
2868
2869         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2870                         __func__, (unsigned long long)instr->addr,
2871                         (unsigned long long)instr->len);
2872
2873         if (check_offs_len(mtd, instr->addr, instr->len))
2874                 return -EINVAL;
2875
2876         /* Grab the lock and see if the device is available */
2877         nand_get_device(mtd, FL_ERASING);
2878
2879         /* Shift to get first page */
2880         page = (int)(instr->addr >> chip->page_shift);
2881         chipnr = (int)(instr->addr >> chip->chip_shift);
2882
2883         /* Calculate pages in each block */
2884         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2885
2886         /* Select the NAND device */
2887         chip->select_chip(mtd, chipnr);
2888
2889         /* Check, if it is write protected */
2890         if (nand_check_wp(mtd)) {
2891                 pr_debug("%s: device is write protected!\n",
2892                                 __func__);
2893                 instr->state = MTD_ERASE_FAILED;
2894                 goto erase_exit;
2895         }
2896
2897         /* Loop through the pages */
2898         len = instr->len;
2899
2900         instr->state = MTD_ERASING;
2901
2902         while (len) {
2903                 WATCHDOG_RESET();
2904
2905                 /* Check if we have a bad block, we do not erase bad blocks! */
2906                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2907                                         chip->page_shift, 0, allowbbt)) {
2908                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2909                                     __func__, page);
2910                         instr->state = MTD_ERASE_FAILED;
2911                         goto erase_exit;
2912                 }
2913
2914                 /*
2915                  * Invalidate the page cache, if we erase the block which
2916                  * contains the current cached page.
2917                  */
2918                 if (page <= chip->pagebuf && chip->pagebuf <
2919                     (page + pages_per_block))
2920                         chip->pagebuf = -1;
2921
2922                 chip->erase_cmd(mtd, page & chip->pagemask);
2923
2924                 status = chip->waitfunc(mtd, chip);
2925
2926                 /*
2927                  * See if operation failed and additional status checks are
2928                  * available
2929                  */
2930                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2931                         status = chip->errstat(mtd, chip, FL_ERASING,
2932                                                status, page);
2933
2934                 /* See if block erase succeeded */
2935                 if (status & NAND_STATUS_FAIL) {
2936                         pr_debug("%s: failed erase, page 0x%08x\n",
2937                                         __func__, page);
2938                         instr->state = MTD_ERASE_FAILED;
2939                         instr->fail_addr =
2940                                 ((loff_t)page << chip->page_shift);
2941                         goto erase_exit;
2942                 }
2943
2944                 /* Increment page address and decrement length */
2945                 len -= (1ULL << chip->phys_erase_shift);
2946                 page += pages_per_block;
2947
2948                 /* Check, if we cross a chip boundary */
2949                 if (len && !(page & chip->pagemask)) {
2950                         chipnr++;
2951                         chip->select_chip(mtd, -1);
2952                         chip->select_chip(mtd, chipnr);
2953                 }
2954         }
2955         instr->state = MTD_ERASE_DONE;
2956
2957 erase_exit:
2958
2959         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2960
2961         /* Deselect and wake up anyone waiting on the device */
2962         chip->select_chip(mtd, -1);
2963         nand_release_device(mtd);
2964
2965         /* Do call back function */
2966         if (!ret)
2967                 mtd_erase_callback(instr);
2968
2969         /* Return more or less happy */
2970         return ret;
2971 }
2972
2973 /**
2974  * nand_sync - [MTD Interface] sync
2975  * @mtd: MTD device structure
2976  *
2977  * Sync is actually a wait for chip ready function.
2978  */
2979 static void nand_sync(struct mtd_info *mtd)
2980 {
2981         pr_debug("%s: called\n", __func__);
2982
2983         /* Grab the lock and see if the device is available */
2984         nand_get_device(mtd, FL_SYNCING);
2985         /* Release it and go back */
2986         nand_release_device(mtd);
2987 }
2988
2989 /**
2990  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2991  * @mtd: MTD device structure
2992  * @offs: offset relative to mtd start
2993  */
2994 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2995 {
2996         return nand_block_checkbad(mtd, offs, 1, 0);
2997 }
2998
2999 /**
3000  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
3001  * @mtd: MTD device structure
3002  * @ofs: offset relative to mtd start
3003  */
3004 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3005 {
3006         int ret;
3007
3008         ret = nand_block_isbad(mtd, ofs);
3009         if (ret) {
3010                 /* If it was bad already, return success and do nothing */
3011                 if (ret > 0)
3012                         return 0;
3013                 return ret;
3014         }
3015
3016         return nand_block_markbad_lowlevel(mtd, ofs);
3017 }
3018
3019 /**
3020  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
3021  * @mtd: MTD device structure
3022  * @chip: nand chip info structure
3023  * @addr: feature address.
3024  * @subfeature_param: the subfeature parameters, a four bytes array.
3025  */
3026 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
3027                         int addr, uint8_t *subfeature_param)
3028 {
3029         int status;
3030         int i;
3031
3032 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3033         if (!chip->onfi_version ||
3034             !(le16_to_cpu(chip->onfi_params.opt_cmd)
3035               & ONFI_OPT_CMD_SET_GET_FEATURES))
3036                 return -EINVAL;
3037 #endif
3038
3039         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
3040         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3041                 chip->write_byte(mtd, subfeature_param[i]);
3042
3043         status = chip->waitfunc(mtd, chip);
3044         if (status & NAND_STATUS_FAIL)
3045                 return -EIO;
3046         return 0;
3047 }
3048
3049 /**
3050  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
3051  * @mtd: MTD device structure
3052  * @chip: nand chip info structure
3053  * @addr: feature address.
3054  * @subfeature_param: the subfeature parameters, a four bytes array.
3055  */
3056 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
3057                         int addr, uint8_t *subfeature_param)
3058 {
3059         int i;
3060
3061 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3062         if (!chip->onfi_version ||
3063             !(le16_to_cpu(chip->onfi_params.opt_cmd)
3064               & ONFI_OPT_CMD_SET_GET_FEATURES))
3065                 return -EINVAL;
3066 #endif
3067
3068         /* clear the sub feature parameters */
3069         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3070
3071         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3072         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3073                 *subfeature_param++ = chip->read_byte(mtd);
3074         return 0;
3075 }
3076
3077 #ifndef __UBOOT__
3078 /**
3079  * nand_suspend - [MTD Interface] Suspend the NAND flash
3080  * @mtd: MTD device structure
3081  */
3082 static int nand_suspend(struct mtd_info *mtd)
3083 {
3084         return nand_get_device(mtd, FL_PM_SUSPENDED);
3085 }
3086
3087 /**
3088  * nand_resume - [MTD Interface] Resume the NAND flash
3089  * @mtd: MTD device structure
3090  */
3091 static void nand_resume(struct mtd_info *mtd)
3092 {
3093         struct nand_chip *chip = mtd->priv;
3094
3095         if (chip->state == FL_PM_SUSPENDED)
3096                 nand_release_device(mtd);
3097         else
3098                 pr_err("%s called for a chip which is not in suspended state\n",
3099                         __func__);
3100 }
3101 #endif
3102
3103 /* Set default functions */
3104 static void nand_set_defaults(struct nand_chip *chip, int busw)
3105 {
3106         /* check for proper chip_delay setup, set 20us if not */
3107         if (!chip->chip_delay)
3108                 chip->chip_delay = 20;
3109
3110         /* check, if a user supplied command function given */
3111         if (chip->cmdfunc == NULL)
3112                 chip->cmdfunc = nand_command;
3113
3114         /* check, if a user supplied wait function given */
3115         if (chip->waitfunc == NULL)
3116                 chip->waitfunc = nand_wait;
3117
3118         if (!chip->select_chip)
3119                 chip->select_chip = nand_select_chip;
3120
3121         /* set for ONFI nand */
3122         if (!chip->onfi_set_features)
3123                 chip->onfi_set_features = nand_onfi_set_features;
3124         if (!chip->onfi_get_features)
3125                 chip->onfi_get_features = nand_onfi_get_features;
3126
3127         /* If called twice, pointers that depend on busw may need to be reset */
3128         if (!chip->read_byte || chip->read_byte == nand_read_byte)
3129                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3130         if (!chip->read_word)
3131                 chip->read_word = nand_read_word;
3132         if (!chip->block_bad)
3133                 chip->block_bad = nand_block_bad;
3134         if (!chip->block_markbad)
3135                 chip->block_markbad = nand_default_block_markbad;
3136         if (!chip->write_buf || chip->write_buf == nand_write_buf)
3137                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3138         if (!chip->write_byte || chip->write_byte == nand_write_byte)
3139                 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3140         if (!chip->read_buf || chip->read_buf == nand_read_buf)
3141                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3142         if (!chip->scan_bbt)
3143                 chip->scan_bbt = nand_default_bbt;
3144 #ifdef __UBOOT__
3145 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
3146         if (!chip->verify_buf)
3147                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
3148 #endif
3149 #endif
3150
3151         if (!chip->controller) {
3152                 chip->controller = &chip->hwcontrol;
3153                 spin_lock_init(&chip->controller->lock);
3154                 init_waitqueue_head(&chip->controller->wq);
3155         }
3156
3157 }
3158
3159 /* Sanitize ONFI strings so we can safely print them */
3160 #ifndef __UBOOT__
3161 static void sanitize_string(uint8_t *s, size_t len)
3162 #else
3163 static void sanitize_string(char *s, size_t len)
3164 #endif
3165 {
3166         ssize_t i;
3167
3168         /* Null terminate */
3169         s[len - 1] = 0;
3170
3171         /* Remove non printable chars */
3172         for (i = 0; i < len - 1; i++) {
3173                 if (s[i] < ' ' || s[i] > 127)
3174                         s[i] = '?';
3175         }
3176
3177         /* Remove trailing spaces */
3178         strim(s);
3179 }
3180
3181 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3182 {
3183         int i;
3184         while (len--) {
3185                 crc ^= *p++ << 8;
3186                 for (i = 0; i < 8; i++)
3187                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3188         }
3189
3190         return crc;
3191 }
3192
3193 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3194 /* Parse the Extended Parameter Page. */
3195 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3196                 struct nand_chip *chip, struct nand_onfi_params *p)
3197 {
3198         struct onfi_ext_param_page *ep;
3199         struct onfi_ext_section *s;
3200         struct onfi_ext_ecc_info *ecc;
3201         uint8_t *cursor;
3202         int ret = -EINVAL;
3203         int len;
3204         int i;
3205
3206         len = le16_to_cpu(p->ext_param_page_length) * 16;
3207         ep = kmalloc(len, GFP_KERNEL);
3208         if (!ep)
3209                 return -ENOMEM;
3210
3211         /* Send our own NAND_CMD_PARAM. */
3212         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3213
3214         /* Use the Change Read Column command to skip the ONFI param pages. */
3215         chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3216                         sizeof(*p) * p->num_of_param_pages , -1);
3217
3218         /* Read out the Extended Parameter Page. */
3219         chip->read_buf(mtd, (uint8_t *)ep, len);
3220         if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3221                 != le16_to_cpu(ep->crc))) {
3222                 pr_debug("fail in the CRC.\n");
3223                 goto ext_out;
3224         }
3225
3226         /*
3227          * Check the signature.
3228          * Do not strictly follow the ONFI spec, maybe changed in future.
3229          */
3230 #ifndef __UBOOT__
3231         if (strncmp(ep->sig, "EPPS", 4)) {
3232 #else
3233         if (strncmp((char *)ep->sig, "EPPS", 4)) {
3234 #endif
3235                 pr_debug("The signature is invalid.\n");
3236                 goto ext_out;
3237         }
3238
3239         /* find the ECC section. */
3240         cursor = (uint8_t *)(ep + 1);
3241         for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3242                 s = ep->sections + i;
3243                 if (s->type == ONFI_SECTION_TYPE_2)
3244                         break;
3245                 cursor += s->length * 16;
3246         }
3247         if (i == ONFI_EXT_SECTION_MAX) {
3248                 pr_debug("We can not find the ECC section.\n");
3249                 goto ext_out;
3250         }
3251
3252         /* get the info we want. */
3253         ecc = (struct onfi_ext_ecc_info *)cursor;
3254
3255         if (!ecc->codeword_size) {
3256                 pr_debug("Invalid codeword size\n");
3257                 goto ext_out;
3258         }
3259
3260         chip->ecc_strength_ds = ecc->ecc_bits;
3261         chip->ecc_step_ds = 1 << ecc->codeword_size;
3262         ret = 0;
3263
3264 ext_out:
3265         kfree(ep);
3266         return ret;
3267 }
3268
3269 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3270 {
3271         struct nand_chip *chip = mtd->priv;
3272         uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3273
3274         return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3275                         feature);
3276 }
3277
3278 /*
3279  * Configure chip properties from Micron vendor-specific ONFI table
3280  */
3281 static void nand_onfi_detect_micron(struct nand_chip *chip,
3282                 struct nand_onfi_params *p)
3283 {
3284         struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3285
3286         if (le16_to_cpu(p->vendor_revision) < 1)
3287                 return;
3288
3289         chip->read_retries = micron->read_retry_options;
3290         chip->setup_read_retry = nand_setup_read_retry_micron;
3291 }
3292
3293 /*
3294  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3295  */
3296 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3297                                         int *busw)
3298 {
3299         struct nand_onfi_params *p = &chip->onfi_params;
3300         int i, j;
3301         int val;
3302
3303         /* Try ONFI for unknown chip or LP */
3304         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3305         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3306                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3307                 return 0;
3308
3309         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3310         for (i = 0; i < 3; i++) {
3311                 for (j = 0; j < sizeof(*p); j++)
3312                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
3313                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3314                                 le16_to_cpu(p->crc)) {
3315                         break;
3316                 }
3317         }
3318
3319         if (i == 3) {
3320                 pr_err("Could not find valid ONFI parameter page; aborting\n");
3321                 return 0;
3322         }
3323
3324         /* Check version */
3325         val = le16_to_cpu(p->revision);
3326         if (val & (1 << 5))
3327                 chip->onfi_version = 23;
3328         else if (val & (1 << 4))
3329                 chip->onfi_version = 22;
3330         else if (val & (1 << 3))
3331                 chip->onfi_version = 21;
3332         else if (val & (1 << 2))
3333                 chip->onfi_version = 20;
3334         else if (val & (1 << 1))
3335                 chip->onfi_version = 10;
3336
3337         if (!chip->onfi_version) {
3338                 pr_info("unsupported ONFI version: %d\n", val);
3339                 return 0;
3340         }
3341
3342         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3343         sanitize_string(p->model, sizeof(p->model));
3344         if (!mtd->name)
3345                 mtd->name = p->model;
3346
3347         mtd->writesize = le32_to_cpu(p->byte_per_page);
3348
3349         /*
3350          * pages_per_block and blocks_per_lun may not be a power-of-2 size
3351          * (don't ask me who thought of this...). MTD assumes that these
3352          * dimensions will be power-of-2, so just truncate the remaining area.
3353          */
3354         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3355         mtd->erasesize *= mtd->writesize;
3356
3357         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3358
3359         /* See erasesize comment */
3360         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3361         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3362         chip->bits_per_cell = p->bits_per_cell;
3363
3364         if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3365                 *busw = NAND_BUSWIDTH_16;
3366         else
3367                 *busw = 0;
3368
3369         if (p->ecc_bits != 0xff) {
3370                 chip->ecc_strength_ds = p->ecc_bits;
3371                 chip->ecc_step_ds = 512;
3372         } else if (chip->onfi_version >= 21 &&
3373                 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3374
3375                 /*
3376                  * The nand_flash_detect_ext_param_page() uses the
3377                  * Change Read Column command which maybe not supported
3378                  * by the chip->cmdfunc. So try to update the chip->cmdfunc
3379                  * now. We do not replace user supplied command function.
3380                  */
3381                 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3382                         chip->cmdfunc = nand_command_lp;
3383
3384                 /* The Extended Parameter Page is supported since ONFI 2.1. */
3385                 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3386                         pr_warn("Failed to detect ONFI extended param page\n");
3387         } else {
3388                 pr_warn("Could not retrieve ONFI ECC requirements\n");
3389         }
3390
3391         if (p->jedec_id == NAND_MFR_MICRON)
3392                 nand_onfi_detect_micron(chip, p);
3393
3394         return 1;
3395 }
3396 #else
3397 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3398                                         int *busw)
3399 {
3400         return 0;
3401 }
3402 #endif
3403
3404 /*
3405  * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3406  */
3407 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3408                                         int *busw)
3409 {
3410         struct nand_jedec_params *p = &chip->jedec_params;
3411         struct jedec_ecc_info *ecc;
3412         int val;
3413         int i, j;
3414
3415         /* Try JEDEC for unknown chip or LP */
3416         chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3417         if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3418                 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3419                 chip->read_byte(mtd) != 'C')
3420                 return 0;
3421
3422         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3423         for (i = 0; i < 3; i++) {
3424                 for (j = 0; j < sizeof(*p); j++)
3425                         ((uint8_t *)p)[j] = chip->read_byte(mtd);
3426
3427                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3428                                 le16_to_cpu(p->crc))
3429                         break;
3430         }
3431
3432         if (i == 3) {
3433                 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3434                 return 0;
3435         }
3436
3437         /* Check version */
3438         val = le16_to_cpu(p->revision);
3439         if (val & (1 << 2))
3440                 chip->jedec_version = 10;
3441         else if (val & (1 << 1))
3442                 chip->jedec_version = 1; /* vendor specific version */
3443
3444         if (!chip->jedec_version) {
3445                 pr_info("unsupported JEDEC version: %d\n", val);
3446                 return 0;
3447         }
3448
3449         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3450         sanitize_string(p->model, sizeof(p->model));
3451         if (!mtd->name)
3452                 mtd->name = p->model;
3453
3454         mtd->writesize = le32_to_cpu(p->byte_per_page);
3455
3456         /* Please reference to the comment for nand_flash_detect_onfi. */
3457         mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3458         mtd->erasesize *= mtd->writesize;
3459
3460         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3461
3462         /* Please reference to the comment for nand_flash_detect_onfi. */
3463         chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3464         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3465         chip->bits_per_cell = p->bits_per_cell;
3466
3467         if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3468                 *busw = NAND_BUSWIDTH_16;
3469         else
3470                 *busw = 0;
3471
3472         /* ECC info */
3473         ecc = &p->ecc_info[0];
3474
3475         if (ecc->codeword_size >= 9) {
3476                 chip->ecc_strength_ds = ecc->ecc_bits;
3477                 chip->ecc_step_ds = 1 << ecc->codeword_size;
3478         } else {
3479                 pr_warn("Invalid codeword size\n");
3480         }
3481
3482         return 1;
3483 }
3484
3485 /*
3486  * nand_id_has_period - Check if an ID string has a given wraparound period
3487  * @id_data: the ID string
3488  * @arrlen: the length of the @id_data array
3489  * @period: the period of repitition
3490  *
3491  * Check if an ID string is repeated within a given sequence of bytes at
3492  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3493  * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3494  * if the repetition has a period of @period; otherwise, returns zero.
3495  */
3496 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3497 {
3498         int i, j;
3499         for (i = 0; i < period; i++)
3500                 for (j = i + period; j < arrlen; j += period)
3501                         if (id_data[i] != id_data[j])
3502                                 return 0;
3503         return 1;
3504 }
3505
3506 /*
3507  * nand_id_len - Get the length of an ID string returned by CMD_READID
3508  * @id_data: the ID string
3509  * @arrlen: the length of the @id_data array
3510
3511  * Returns the length of the ID string, according to known wraparound/trailing
3512  * zero patterns. If no pattern exists, returns the length of the array.
3513  */
3514 static int nand_id_len(u8 *id_data, int arrlen)
3515 {
3516         int last_nonzero, period;
3517
3518         /* Find last non-zero byte */
3519         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3520                 if (id_data[last_nonzero])
3521                         break;
3522
3523         /* All zeros */
3524         if (last_nonzero < 0)
3525                 return 0;
3526
3527         /* Calculate wraparound period */
3528         for (period = 1; period < arrlen; period++)
3529                 if (nand_id_has_period(id_data, arrlen, period))
3530                         break;
3531
3532         /* There's a repeated pattern */
3533         if (period < arrlen)
3534                 return period;
3535
3536         /* There are trailing zeros */
3537         if (last_nonzero < arrlen - 1)
3538                 return last_nonzero + 1;
3539
3540         /* No pattern detected */
3541         return arrlen;
3542 }
3543
3544 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3545 static int nand_get_bits_per_cell(u8 cellinfo)
3546 {
3547         int bits;
3548
3549         bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3550         bits >>= NAND_CI_CELLTYPE_SHIFT;
3551         return bits + 1;
3552 }
3553
3554 /*
3555  * Many new NAND share similar device ID codes, which represent the size of the
3556  * chip. The rest of the parameters must be decoded according to generic or
3557  * manufacturer-specific "extended ID" decoding patterns.
3558  */
3559 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3560                                 u8 id_data[8], int *busw)
3561 {
3562         int extid, id_len;
3563         /* The 3rd id byte holds MLC / multichip data */
3564         chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3565         /* The 4th id byte is the important one */
3566         extid = id_data[3];
3567
3568         id_len = nand_id_len(id_data, 8);
3569
3570         /*
3571          * Field definitions are in the following datasheets:
3572          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3573          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3574          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
3575          *
3576          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3577          * ID to decide what to do.
3578          */
3579         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3580                         !nand_is_slc(chip) && id_data[5] != 0x00) {
3581                 /* Calc pagesize */
3582                 mtd->writesize = 2048 << (extid & 0x03);
3583                 extid >>= 2;
3584                 /* Calc oobsize */
3585                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3586                 case 1:
3587                         mtd->oobsize = 128;
3588                         break;
3589                 case 2:
3590                         mtd->oobsize = 218;
3591                         break;
3592                 case 3:
3593                         mtd->oobsize = 400;
3594                         break;
3595                 case 4:
3596                         mtd->oobsize = 436;
3597                         break;
3598                 case 5:
3599                         mtd->oobsize = 512;
3600                         break;
3601                 case 6:
3602                         mtd->oobsize = 640;
3603                         break;
3604                 case 7:
3605                 default: /* Other cases are "reserved" (unknown) */
3606                         mtd->oobsize = 1024;
3607                         break;
3608                 }
3609                 extid >>= 2;
3610                 /* Calc blocksize */
3611                 mtd->erasesize = (128 * 1024) <<
3612                         (((extid >> 1) & 0x04) | (extid & 0x03));
3613                 *busw = 0;
3614         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3615                         !nand_is_slc(chip)) {
3616                 unsigned int tmp;
3617
3618                 /* Calc pagesize */
3619                 mtd->writesize = 2048 << (extid & 0x03);
3620                 extid >>= 2;
3621                 /* Calc oobsize */
3622                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3623                 case 0:
3624                         mtd->oobsize = 128;
3625                         break;
3626                 case 1:
3627                         mtd->oobsize = 224;
3628                         break;
3629                 case 2:
3630                         mtd->oobsize = 448;
3631                         break;
3632                 case 3:
3633                         mtd->oobsize = 64;
3634                         break;
3635                 case 4:
3636                         mtd->oobsize = 32;
3637                         break;
3638                 case 5:
3639                         mtd->oobsize = 16;
3640                         break;
3641                 default:
3642                         mtd->oobsize = 640;
3643                         break;
3644                 }
3645                 extid >>= 2;
3646                 /* Calc blocksize */
3647                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3648                 if (tmp < 0x03)
3649                         mtd->erasesize = (128 * 1024) << tmp;
3650                 else if (tmp == 0x03)
3651                         mtd->erasesize = 768 * 1024;
3652                 else
3653                         mtd->erasesize = (64 * 1024) << tmp;
3654                 *busw = 0;
3655         } else {
3656                 /* Calc pagesize */
3657                 mtd->writesize = 1024 << (extid & 0x03);
3658                 extid >>= 2;
3659                 /* Calc oobsize */
3660                 mtd->oobsize = (8 << (extid & 0x01)) *
3661                         (mtd->writesize >> 9);
3662                 extid >>= 2;
3663                 /* Calc blocksize. Blocksize is multiples of 64KiB */
3664                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3665                 extid >>= 2;
3666                 /* Get buswidth information */
3667                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3668
3669                 /*
3670                  * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3671                  * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3672                  * follows:
3673                  * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3674                  *                         110b -> 24nm
3675                  * - ID byte 5, bit[7]:    1 -> BENAND, 0 -> raw SLC
3676                  */
3677                 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3678                                 nand_is_slc(chip) &&
3679                                 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3680                                 !(id_data[4] & 0x80) /* !BENAND */) {
3681                         mtd->oobsize = 32 * mtd->writesize >> 9;
3682                 }
3683
3684         }
3685 }
3686
3687 /*
3688  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3689  * decodes a matching ID table entry and assigns the MTD size parameters for
3690  * the chip.
3691  */
3692 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3693                                 struct nand_flash_dev *type, u8 id_data[8],
3694                                 int *busw)
3695 {
3696         int maf_id = id_data[0];
3697
3698         mtd->erasesize = type->erasesize;
3699         mtd->writesize = type->pagesize;
3700         mtd->oobsize = mtd->writesize / 32;
3701         *busw = type->options & NAND_BUSWIDTH_16;
3702
3703         /* All legacy ID NAND are small-page, SLC */
3704         chip->bits_per_cell = 1;
3705
3706         /*
3707          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3708          * some Spansion chips have erasesize that conflicts with size
3709          * listed in nand_ids table.
3710          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3711          */
3712         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3713                         && id_data[6] == 0x00 && id_data[7] == 0x00
3714                         && mtd->writesize == 512) {
3715                 mtd->erasesize = 128 * 1024;
3716                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3717         }
3718 }
3719
3720 /*
3721  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3722  * heuristic patterns using various detected parameters (e.g., manufacturer,
3723  * page size, cell-type information).
3724  */
3725 static void nand_decode_bbm_options(struct mtd_info *mtd,
3726                                     struct nand_chip *chip, u8 id_data[8])
3727 {
3728         int maf_id = id_data[0];
3729
3730         /* Set the bad block position */
3731         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3732                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3733         else
3734                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3735
3736         /*
3737          * Bad block marker is stored in the last page of each block on Samsung
3738          * and Hynix MLC devices; stored in first two pages of each block on
3739          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3740          * AMD/Spansion, and Macronix.  All others scan only the first page.
3741          */
3742         if (!nand_is_slc(chip) &&
3743                         (maf_id == NAND_MFR_SAMSUNG ||
3744                          maf_id == NAND_MFR_HYNIX))
3745                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3746         else if ((nand_is_slc(chip) &&
3747                                 (maf_id == NAND_MFR_SAMSUNG ||
3748                                  maf_id == NAND_MFR_HYNIX ||
3749                                  maf_id == NAND_MFR_TOSHIBA ||
3750                                  maf_id == NAND_MFR_AMD ||
3751                                  maf_id == NAND_MFR_MACRONIX)) ||
3752                         (mtd->writesize == 2048 &&
3753                          maf_id == NAND_MFR_MICRON))
3754                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3755 }
3756
3757 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3758 {
3759         return type->id_len;
3760 }
3761
3762 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3763                    struct nand_flash_dev *type, u8 *id_data, int *busw)
3764 {
3765 #ifndef __UBOOT__
3766         if (!strncmp(type->id, id_data, type->id_len)) {
3767 #else
3768         if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3769 #endif
3770                 mtd->writesize = type->pagesize;
3771                 mtd->erasesize = type->erasesize;
3772                 mtd->oobsize = type->oobsize;
3773
3774                 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3775                 chip->chipsize = (uint64_t)type->chipsize << 20;
3776                 chip->options |= type->options;
3777                 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3778                 chip->ecc_step_ds = NAND_ECC_STEP(type);
3779
3780                 *busw = type->options & NAND_BUSWIDTH_16;
3781
3782                 if (!mtd->name)
3783                         mtd->name = type->name;
3784
3785                 return true;
3786         }
3787         return false;
3788 }
3789
3790 /*
3791  * Get the flash and manufacturer id and lookup if the type is supported.
3792  */
3793 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3794                                                   struct nand_chip *chip,
3795                                                   int *maf_id, int *dev_id,
3796                                                   struct nand_flash_dev *type)
3797 {
3798         int busw;
3799         int i, maf_idx;
3800         u8 id_data[8];
3801
3802         /* Select the device */
3803         chip->select_chip(mtd, 0);
3804
3805         /*
3806          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3807          * after power-up.
3808          */
3809         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3810
3811         /* Send the command for reading device ID */
3812         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3813
3814         /* Read manufacturer and device IDs */
3815         *maf_id = chip->read_byte(mtd);
3816         *dev_id = chip->read_byte(mtd);
3817
3818         /*
3819          * Try again to make sure, as some systems the bus-hold or other
3820          * interface concerns can cause random data which looks like a
3821          * possibly credible NAND flash to appear. If the two results do
3822          * not match, ignore the device completely.
3823          */
3824
3825         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3826
3827         /* Read entire ID string */
3828         for (i = 0; i < 8; i++)
3829                 id_data[i] = chip->read_byte(mtd);
3830
3831         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3832                 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3833                         *maf_id, *dev_id, id_data[0], id_data[1]);
3834                 return ERR_PTR(-ENODEV);
3835         }
3836
3837         if (!type)
3838                 type = nand_flash_ids;
3839
3840         for (; type->name != NULL; type++) {
3841                 if (is_full_id_nand(type)) {
3842                         if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3843                                 goto ident_done;
3844                 } else if (*dev_id == type->dev_id) {
3845                                 break;
3846                 }
3847         }
3848
3849         chip->onfi_version = 0;
3850         if (!type->name || !type->pagesize) {
3851                 /* Check is chip is ONFI compliant */
3852                 if (nand_flash_detect_onfi(mtd, chip, &busw))
3853                         goto ident_done;
3854
3855                 /* Check if the chip is JEDEC compliant */
3856                 if (nand_flash_detect_jedec(mtd, chip, &busw))
3857                         goto ident_done;
3858         }
3859
3860         if (!type->name)
3861                 return ERR_PTR(-ENODEV);
3862
3863         if (!mtd->name)
3864                 mtd->name = type->name;
3865
3866         chip->chipsize = (uint64_t)type->chipsize << 20;
3867
3868         if (!type->pagesize && chip->init_size) {
3869                 /* Set the pagesize, oobsize, erasesize by the driver */
3870                 busw = chip->init_size(mtd, chip, id_data);
3871         } else if (!type->pagesize) {
3872                 /* Decode parameters from extended ID */
3873                 nand_decode_ext_id(mtd, chip, id_data, &busw);
3874         } else {
3875                 nand_decode_id(mtd, chip, type, id_data, &busw);
3876         }
3877         /* Get chip options */
3878         chip->options |= type->options;
3879
3880         /*
3881          * Check if chip is not a Samsung device. Do not clear the
3882          * options for chips which do not have an extended id.
3883          */
3884         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3885                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3886 ident_done:
3887
3888         /* Try to identify manufacturer */
3889         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3890                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3891                         break;
3892         }
3893
3894         if (chip->options & NAND_BUSWIDTH_AUTO) {
3895                 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3896                 chip->options |= busw;
3897                 nand_set_defaults(chip, busw);
3898         } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3899                 /*
3900                  * Check, if buswidth is correct. Hardware drivers should set
3901                  * chip correct!
3902                  */
3903                 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3904                         *maf_id, *dev_id);
3905                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3906                 pr_warn("bus width %d instead %d bit\n",
3907                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3908                            busw ? 16 : 8);
3909                 return ERR_PTR(-EINVAL);
3910         }
3911
3912         nand_decode_bbm_options(mtd, chip, id_data);
3913
3914         /* Calculate the address shift from the page size */
3915         chip->page_shift = ffs(mtd->writesize) - 1;
3916         /* Convert chipsize to number of pages per chip -1 */
3917         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3918
3919         chip->bbt_erase_shift = chip->phys_erase_shift =
3920                 ffs(mtd->erasesize) - 1;
3921         if (chip->chipsize & 0xffffffff)
3922                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3923         else {
3924                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3925                 chip->chip_shift += 32 - 1;
3926         }
3927
3928         chip->badblockbits = 8;
3929         chip->erase_cmd = single_erase_cmd;
3930
3931         /* Do not replace user supplied command function! */
3932         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3933                 chip->cmdfunc = nand_command_lp;
3934
3935         pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3936                 *maf_id, *dev_id);
3937
3938 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3939         if (chip->onfi_version)
3940                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3941                                 chip->onfi_params.model);
3942         else if (chip->jedec_version)
3943                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3944                                 chip->jedec_params.model);
3945         else
3946                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3947                                 type->name);
3948 #else
3949         if (chip->jedec_version)
3950                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3951                                 chip->jedec_params.model);
3952         else
3953                 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3954                                 type->name);
3955
3956         pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3957                 type->name);
3958 #endif
3959
3960         pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3961                 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3962                 mtd->writesize, mtd->oobsize);
3963         return type;
3964 }
3965
3966 /**
3967  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3968  * @mtd: MTD device structure
3969  * @maxchips: number of chips to scan for
3970  * @table: alternative NAND ID table
3971  *
3972  * This is the first phase of the normal nand_scan() function. It reads the
3973  * flash ID and sets up MTD fields accordingly.
3974  *
3975  * The mtd->owner field must be set to the module of the caller.
3976  */
3977 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3978                     struct nand_flash_dev *table)
3979 {
3980         int i, nand_maf_id, nand_dev_id;
3981         struct nand_chip *chip = mtd->priv;
3982         struct nand_flash_dev *type;
3983
3984         /* Set the default functions */
3985         nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3986
3987         /* Read the flash type */
3988         type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3989                                    &nand_dev_id, table);
3990
3991         if (IS_ERR(type)) {
3992                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3993                         pr_warn("No NAND device found\n");
3994                 chip->select_chip(mtd, -1);
3995                 return PTR_ERR(type);
3996         }
3997
3998         chip->select_chip(mtd, -1);
3999
4000         /* Check for a chip array */
4001         for (i = 1; i < maxchips; i++) {
4002                 chip->select_chip(mtd, i);
4003                 /* See comment in nand_get_flash_type for reset */
4004                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4005                 /* Send the command for reading device ID */
4006                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
4007                 /* Read manufacturer and device IDs */
4008                 if (nand_maf_id != chip->read_byte(mtd) ||
4009                     nand_dev_id != chip->read_byte(mtd)) {
4010                         chip->select_chip(mtd, -1);
4011                         break;
4012                 }
4013                 chip->select_chip(mtd, -1);
4014         }
4015
4016 #ifdef DEBUG
4017         if (i > 1)
4018                 pr_info("%d chips detected\n", i);
4019 #endif
4020
4021         /* Store the number of chips and calc total size for mtd */
4022         chip->numchips = i;
4023         mtd->size = i * chip->chipsize;
4024
4025         return 0;
4026 }
4027 EXPORT_SYMBOL(nand_scan_ident);
4028
4029
4030 /**
4031  * nand_scan_tail - [NAND Interface] Scan for the NAND device
4032  * @mtd: MTD device structure
4033  *
4034  * This is the second phase of the normal nand_scan() function. It fills out
4035  * all the uninitialized function pointers with the defaults and scans for a
4036  * bad block table if appropriate.
4037  */
4038 int nand_scan_tail(struct mtd_info *mtd)
4039 {
4040         int i;
4041         struct nand_chip *chip = mtd->priv;
4042         struct nand_ecc_ctrl *ecc = &chip->ecc;
4043         struct nand_buffers *nbuf;
4044
4045         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
4046         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
4047                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
4048
4049         if (!(chip->options & NAND_OWN_BUFFERS)) {
4050 #ifndef __UBOOT__
4051                 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
4052                                 + mtd->oobsize * 3, GFP_KERNEL);
4053                 if (!nbuf)
4054                         return -ENOMEM;
4055                 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
4056                 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
4057                 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
4058 #else
4059                 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
4060 #endif
4061
4062                 chip->buffers = nbuf;
4063         } else {
4064                 if (!chip->buffers)
4065                         return -ENOMEM;
4066         }
4067
4068         /* Set the internal oob buffer location, just after the page data */
4069         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4070
4071         /*
4072          * If no default placement scheme is given, select an appropriate one.
4073          */
4074         if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4075                 switch (mtd->oobsize) {
4076                 case 8:
4077                         ecc->layout = &nand_oob_8;
4078                         break;
4079                 case 16:
4080                         ecc->layout = &nand_oob_16;
4081                         break;
4082                 case 64:
4083                         ecc->layout = &nand_oob_64;
4084                         break;
4085                 case 128:
4086                         ecc->layout = &nand_oob_128;
4087                         break;
4088                 default:
4089                         pr_warn("No oob scheme defined for oobsize %d\n",
4090                                    mtd->oobsize);
4091                         BUG();
4092                 }
4093         }
4094
4095         if (!chip->write_page)
4096                 chip->write_page = nand_write_page;
4097
4098         /*
4099          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4100          * selected and we have 256 byte pagesize fallback to software ECC
4101          */
4102
4103         switch (ecc->mode) {
4104         case NAND_ECC_HW_OOB_FIRST:
4105                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4106                 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4107                         pr_warn("No ECC functions supplied; "
4108                                    "hardware ECC not possible\n");
4109                         BUG();
4110                 }
4111                 if (!ecc->read_page)
4112                         ecc->read_page = nand_read_page_hwecc_oob_first;
4113
4114         case NAND_ECC_HW:
4115                 /* Use standard hwecc read page function? */
4116                 if (!ecc->read_page)
4117                         ecc->read_page = nand_read_page_hwecc;
4118                 if (!ecc->write_page)
4119                         ecc->write_page = nand_write_page_hwecc;
4120                 if (!ecc->read_page_raw)
4121                         ecc->read_page_raw = nand_read_page_raw;
4122                 if (!ecc->write_page_raw)
4123                         ecc->write_page_raw = nand_write_page_raw;
4124                 if (!ecc->read_oob)
4125                         ecc->read_oob = nand_read_oob_std;
4126                 if (!ecc->write_oob)
4127                         ecc->write_oob = nand_write_oob_std;
4128                 if (!ecc->read_subpage)
4129                         ecc->read_subpage = nand_read_subpage;
4130                 if (!ecc->write_subpage)
4131                         ecc->write_subpage = nand_write_subpage_hwecc;
4132
4133         case NAND_ECC_HW_SYNDROME:
4134                 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4135                     (!ecc->read_page ||
4136                      ecc->read_page == nand_read_page_hwecc ||
4137                      !ecc->write_page ||
4138                      ecc->write_page == nand_write_page_hwecc)) {
4139                         pr_warn("No ECC functions supplied; "
4140                                    "hardware ECC not possible\n");
4141                         BUG();
4142                 }
4143                 /* Use standard syndrome read/write page function? */
4144                 if (!ecc->read_page)
4145                         ecc->read_page = nand_read_page_syndrome;
4146                 if (!ecc->write_page)
4147                         ecc->write_page = nand_write_page_syndrome;
4148                 if (!ecc->read_page_raw)
4149                         ecc->read_page_raw = nand_read_page_raw_syndrome;
4150                 if (!ecc->write_page_raw)
4151                         ecc->write_page_raw = nand_write_page_raw_syndrome;
4152                 if (!ecc->read_oob)
4153                         ecc->read_oob = nand_read_oob_syndrome;
4154                 if (!ecc->write_oob)
4155                         ecc->write_oob = nand_write_oob_syndrome;
4156
4157                 if (mtd->writesize >= ecc->size) {
4158                         if (!ecc->strength) {
4159                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4160                                 BUG();
4161                         }
4162                         break;
4163                 }
4164                 pr_warn("%d byte HW ECC not possible on "
4165                            "%d byte page size, fallback to SW ECC\n",
4166                            ecc->size, mtd->writesize);
4167                 ecc->mode = NAND_ECC_SOFT;
4168
4169         case NAND_ECC_SOFT:
4170                 ecc->calculate = nand_calculate_ecc;
4171                 ecc->correct = nand_correct_data;
4172                 ecc->read_page = nand_read_page_swecc;
4173                 ecc->read_subpage = nand_read_subpage;
4174                 ecc->write_page = nand_write_page_swecc;
4175                 ecc->read_page_raw = nand_read_page_raw;
4176                 ecc->write_page_raw = nand_write_page_raw;
4177                 ecc->read_oob = nand_read_oob_std;
4178                 ecc->write_oob = nand_write_oob_std;
4179                 if (!ecc->size)
4180                         ecc->size = 256;
4181                 ecc->bytes = 3;
4182                 ecc->strength = 1;
4183                 break;
4184
4185         case NAND_ECC_SOFT_BCH:
4186                 if (!mtd_nand_has_bch()) {
4187                         pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4188                         BUG();
4189                 }
4190                 ecc->calculate = nand_bch_calculate_ecc;
4191                 ecc->correct = nand_bch_correct_data;
4192                 ecc->read_page = nand_read_page_swecc;
4193                 ecc->read_subpage = nand_read_subpage;
4194                 ecc->write_page = nand_write_page_swecc;
4195                 ecc->read_page_raw = nand_read_page_raw;
4196                 ecc->write_page_raw = nand_write_page_raw;
4197                 ecc->read_oob = nand_read_oob_std;
4198                 ecc->write_oob = nand_write_oob_std;
4199                 /*
4200                  * Board driver should supply ecc.size and ecc.bytes values to
4201                  * select how many bits are correctable; see nand_bch_init()
4202                  * for details. Otherwise, default to 4 bits for large page
4203                  * devices.
4204                  */
4205                 if (!ecc->size && (mtd->oobsize >= 64)) {
4206                         ecc->size = 512;
4207                         ecc->bytes = 7;
4208                 }
4209                 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4210                                                &ecc->layout);
4211                 if (!ecc->priv) {
4212                         pr_warn("BCH ECC initialization failed!\n");
4213                         BUG();
4214                 }
4215                 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4216                 break;
4217
4218         case NAND_ECC_NONE:
4219                 pr_warn("NAND_ECC_NONE selected by board driver. "
4220                            "This is not recommended!\n");
4221                 ecc->read_page = nand_read_page_raw;
4222                 ecc->write_page = nand_write_page_raw;
4223                 ecc->read_oob = nand_read_oob_std;
4224                 ecc->read_page_raw = nand_read_page_raw;
4225                 ecc->write_page_raw = nand_write_page_raw;
4226                 ecc->write_oob = nand_write_oob_std;
4227                 ecc->size = mtd->writesize;
4228                 ecc->bytes = 0;
4229                 ecc->strength = 0;
4230                 break;
4231
4232         default:
4233                 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4234                 BUG();
4235         }
4236
4237         /* For many systems, the standard OOB write also works for raw */
4238         if (!ecc->read_oob_raw)
4239                 ecc->read_oob_raw = ecc->read_oob;
4240         if (!ecc->write_oob_raw)
4241                 ecc->write_oob_raw = ecc->write_oob;
4242
4243         /*
4244          * The number of bytes available for a client to place data into
4245          * the out of band area.
4246          */
4247         ecc->layout->oobavail = 0;
4248         for (i = 0; ecc->layout->oobfree[i].length
4249                         && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4250                 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4251         mtd->oobavail = ecc->layout->oobavail;
4252
4253         /*
4254          * Set the number of read / write steps for one page depending on ECC
4255          * mode.
4256          */
4257         ecc->steps = mtd->writesize / ecc->size;
4258         if (ecc->steps * ecc->size != mtd->writesize) {
4259                 pr_warn("Invalid ECC parameters\n");
4260                 BUG();
4261         }
4262         ecc->total = ecc->steps * ecc->bytes;
4263
4264         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4265         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4266                 switch (ecc->steps) {
4267                 case 2:
4268                         mtd->subpage_sft = 1;
4269                         break;
4270                 case 4:
4271                 case 8:
4272                 case 16:
4273                         mtd->subpage_sft = 2;
4274                         break;
4275                 }
4276         }
4277         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4278
4279         /* Initialize state */
4280         chip->state = FL_READY;
4281
4282         /* Invalidate the pagebuffer reference */
4283         chip->pagebuf = -1;
4284
4285         /* Large page NAND with SOFT_ECC should support subpage reads */
4286         if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4287                 chip->options |= NAND_SUBPAGE_READ;
4288
4289         /* Fill in remaining MTD driver data */
4290         mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4291         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4292                                                 MTD_CAP_NANDFLASH;
4293         mtd->_erase = nand_erase;
4294 #ifndef __UBOOT__
4295         mtd->_point = NULL;
4296         mtd->_unpoint = NULL;
4297 #endif
4298         mtd->_read = nand_read;
4299         mtd->_write = nand_write;
4300         mtd->_panic_write = panic_nand_write;
4301         mtd->_read_oob = nand_read_oob;
4302         mtd->_write_oob = nand_write_oob;
4303         mtd->_sync = nand_sync;
4304         mtd->_lock = NULL;
4305         mtd->_unlock = NULL;
4306 #ifndef __UBOOT__
4307         mtd->_suspend = nand_suspend;
4308         mtd->_resume = nand_resume;
4309 #endif
4310         mtd->_block_isbad = nand_block_isbad;
4311         mtd->_block_markbad = nand_block_markbad;
4312         mtd->writebufsize = mtd->writesize;
4313
4314         /* propagate ecc info to mtd_info */
4315         mtd->ecclayout = ecc->layout;
4316         mtd->ecc_strength = ecc->strength;
4317         mtd->ecc_step_size = ecc->size;
4318         /*
4319          * Initialize bitflip_threshold to its default prior scan_bbt() call.
4320          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4321          * properly set.
4322          */
4323         if (!mtd->bitflip_threshold)
4324                 mtd->bitflip_threshold = mtd->ecc_strength;
4325
4326         /* Check, if we should skip the bad block table scan */
4327         if (chip->options & NAND_SKIP_BBTSCAN)
4328                 return 0;
4329
4330         /* Build bad block table */
4331         return chip->scan_bbt(mtd);
4332 }
4333 EXPORT_SYMBOL(nand_scan_tail);
4334
4335 /*
4336  * is_module_text_address() isn't exported, and it's mostly a pointless
4337  * test if this is a module _anyway_ -- they'd have to try _really_ hard
4338  * to call us from in-kernel code if the core NAND support is modular.
4339  */
4340 #ifdef MODULE
4341 #define caller_is_module() (1)
4342 #else
4343 #define caller_is_module() \
4344         is_module_text_address((unsigned long)__builtin_return_address(0))
4345 #endif
4346
4347 /**
4348  * nand_scan - [NAND Interface] Scan for the NAND device
4349  * @mtd: MTD device structure
4350  * @maxchips: number of chips to scan for
4351  *
4352  * This fills out all the uninitialized function pointers with the defaults.
4353  * The flash ID is read and the mtd/chip structures are filled with the
4354  * appropriate values. The mtd->owner field must be set to the module of the
4355  * caller.
4356  */
4357 int nand_scan(struct mtd_info *mtd, int maxchips)
4358 {
4359         int ret;
4360
4361         /* Many callers got this wrong, so check for it for a while... */
4362         if (!mtd->owner && caller_is_module()) {
4363                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4364                 BUG();
4365         }
4366
4367         ret = nand_scan_ident(mtd, maxchips, NULL);
4368         if (!ret)
4369                 ret = nand_scan_tail(mtd);
4370         return ret;
4371 }
4372 EXPORT_SYMBOL(nand_scan);
4373
4374 #ifndef __UBOOT__
4375 /**
4376  * nand_release - [NAND Interface] Free resources held by the NAND device
4377  * @mtd: MTD device structure
4378  */
4379 void nand_release(struct mtd_info *mtd)
4380 {
4381         struct nand_chip *chip = mtd->priv;
4382
4383         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4384                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4385
4386         mtd_device_unregister(mtd);
4387
4388         /* Free bad block table memory */
4389         kfree(chip->bbt);
4390         if (!(chip->options & NAND_OWN_BUFFERS))
4391                 kfree(chip->buffers);
4392
4393         /* Free bad block descriptor memory */
4394         if (chip->badblock_pattern && chip->badblock_pattern->options
4395                         & NAND_BBT_DYNAMICSTRUCT)
4396                 kfree(chip->badblock_pattern);
4397 }
4398 EXPORT_SYMBOL_GPL(nand_release);
4399
4400 static int __init nand_base_init(void)
4401 {
4402         led_trigger_register_simple("nand-disk", &nand_led_trigger);
4403         return 0;
4404 }
4405
4406 static void __exit nand_base_exit(void)
4407 {
4408         led_trigger_unregister_simple(nand_led_trigger);
4409 }
4410 #endif
4411
4412 module_init(nand_base_init);
4413 module_exit(nand_base_exit);
4414
4415 MODULE_LICENSE("GPL");
4416 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4417 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4418 MODULE_DESCRIPTION("Generic NAND flash driver code");