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1 /*
2  * (C) Copyright 2006-2008
3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License as
7  * published by the Free Software Foundation; either version 2 of
8  * the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18  * MA 02111-1307 USA
19  */
20
21 #include <common.h>
22 #include <nand.h>
23 #include <asm/io.h>
24 #include <linux/mtd/nand_ecc.h>
25
26 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
27 static nand_info_t mtd;
28 static struct nand_chip nand_chip;
29
30 #define ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / \
31                                         CONFIG_SYS_NAND_ECCSIZE)
32 #define ECCTOTAL        (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
33
34
35 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
36 /*
37  * NAND command for small page NAND devices (512)
38  */
39 static int nand_command(int block, int page, uint32_t offs,
40         u8 cmd)
41 {
42         struct nand_chip *this = mtd.priv;
43         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
44
45         while (!this->dev_ready(&mtd))
46                 ;
47
48         /* Begin command latch cycle */
49         this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
50         /* Set ALE and clear CLE to start address cycle */
51         /* Column address */
52         this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
53         this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
54         this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
55                        NAND_CTRL_ALE); /* A[24:17] */
56 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
57         /* One more address cycle for devices > 32MiB */
58         this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
59                        NAND_CTRL_ALE); /* A[28:25] */
60 #endif
61         /* Latch in address */
62         this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
63
64         /*
65          * Wait a while for the data to be ready
66          */
67         while (!this->dev_ready(&mtd))
68                 ;
69
70         return 0;
71 }
72 #else
73 /*
74  * NAND command for large page NAND devices (2k)
75  */
76 static int nand_command(int block, int page, uint32_t offs,
77         u8 cmd)
78 {
79         struct nand_chip *this = mtd.priv;
80         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
81         void (*hwctrl)(struct mtd_info *mtd, int cmd,
82                         unsigned int ctrl) = this->cmd_ctrl;
83
84         while (!this->dev_ready(&mtd))
85                 ;
86
87         /* Emulate NAND_CMD_READOOB */
88         if (cmd == NAND_CMD_READOOB) {
89                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
90                 cmd = NAND_CMD_READ0;
91         }
92
93         /* Shift the offset from byte addressing to word addressing. */
94         if (this->options & NAND_BUSWIDTH_16)
95                 offs >>= 1;
96
97         /* Begin command latch cycle */
98         hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
99         /* Set ALE and clear CLE to start address cycle */
100         /* Column address */
101         hwctrl(&mtd, offs & 0xff,
102                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
103         hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
104         /* Row address */
105         hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
106         hwctrl(&mtd, ((page_addr >> 8) & 0xff),
107                        NAND_CTRL_ALE); /* A[27:20] */
108 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
109         /* One more address cycle for devices > 128MiB */
110         hwctrl(&mtd, (page_addr >> 16) & 0x0f,
111                        NAND_CTRL_ALE); /* A[31:28] */
112 #endif
113         /* Latch in address */
114         hwctrl(&mtd, NAND_CMD_READSTART,
115                        NAND_CTRL_CLE | NAND_CTRL_CHANGE);
116         hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
117
118         /*
119          * Wait a while for the data to be ready
120          */
121         while (!this->dev_ready(&mtd))
122                 ;
123
124         return 0;
125 }
126 #endif
127
128 static int nand_is_bad_block(int block)
129 {
130         struct nand_chip *this = mtd.priv;
131
132         nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
133                 NAND_CMD_READOOB);
134
135         /*
136          * Read one byte (or two if it's a 16 bit chip).
137          */
138         if (this->options & NAND_BUSWIDTH_16) {
139                 if (readw(this->IO_ADDR_R) != 0xffff)
140                         return 1;
141         } else {
142                 if (readb(this->IO_ADDR_R) != 0xff)
143                         return 1;
144         }
145
146         return 0;
147 }
148
149 #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
150 static int nand_read_page(int block, int page, uchar *dst)
151 {
152         struct nand_chip *this = mtd.priv;
153         u_char ecc_calc[ECCTOTAL];
154         u_char ecc_code[ECCTOTAL];
155         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
156         int i;
157         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
158         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
159         int eccsteps = ECCSTEPS;
160         uint8_t *p = dst;
161
162         nand_command(block, page, 0, NAND_CMD_READOOB);
163         this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
164         nand_command(block, page, 0, NAND_CMD_READ0);
165
166         /* Pick the ECC bytes out of the oob data */
167         for (i = 0; i < ECCTOTAL; i++)
168                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
169
170
171         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
172                 this->ecc.hwctl(&mtd, NAND_ECC_READ);
173                 this->read_buf(&mtd, p, eccsize);
174                 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
175                 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
176         }
177
178         return 0;
179 }
180 #else
181 static int nand_read_page(int block, int page, void *dst)
182 {
183         struct nand_chip *this = mtd.priv;
184         u_char ecc_calc[ECCTOTAL];
185         u_char ecc_code[ECCTOTAL];
186         u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
187         int i;
188         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
189         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
190         int eccsteps = ECCSTEPS;
191         uint8_t *p = dst;
192
193         nand_command(block, page, 0, NAND_CMD_READ0);
194
195         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
196                 if (this->ecc.mode != NAND_ECC_SOFT)
197                         this->ecc.hwctl(&mtd, NAND_ECC_READ);
198                 this->read_buf(&mtd, p, eccsize);
199                 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
200         }
201         this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
202
203         /* Pick the ECC bytes out of the oob data */
204         for (i = 0; i < ECCTOTAL; i++)
205                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
206
207         eccsteps = ECCSTEPS;
208         p = dst;
209
210         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
211                 /* No chance to do something with the possible error message
212                  * from correct_data(). We just hope that all possible errors
213                  * are corrected by this routine.
214                  */
215                 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
216         }
217
218         return 0;
219 }
220 #endif
221
222 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
223 {
224         unsigned int block, lastblock, bad = 0;
225         unsigned int page;
226         const int ppb = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
227         int maxbad;
228
229 #ifdef CONFIG_SYS_NAND_MAXBAD
230         maxbad = CONFIG_SYS_NAND_MAXBAD;
231 #else
232         maxbad = mtd.size;
233 #endif
234         /*
235          * offs has to be aligned to a page address!
236          */
237         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
238         lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
239         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
240
241         while (block <= lastblock) {
242                 if (!nand_is_bad_block(block)) {
243                         /*
244                          * Skip bad blocks
245                          */
246                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
247                                 if (nand_chip.ecc.read_page) {
248                                         int ret;
249
250                                         ret = nand_chip.ecc.read_page(&mtd, &nand_chip,
251                                                 dst, block * ppb + page);
252                                         if (ret) {
253                                                 if (page > 0)
254                                                         dst -= (page - 1) * CONFIG_SYS_NAND_PAGE_SIZE;
255                                                 bad++;
256                                                 lastblock++;
257                                                 break;
258                                         }
259                                 } else {
260                                         nand_read_page(block, page, dst);
261                                 }
262                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
263                                 page++;
264                         }
265
266                         page = 0;
267                 } else {
268                         printf("Skipping bad block %d\n", block);
269                         bad++;
270                         lastblock++;
271                 }
272
273                 if (maxbad > 0 && bad > maxbad) {
274                         printf("Too many bad blocks encountered\n");
275                         return -1;
276                 }
277
278                 block++;
279         }
280
281         return 0;
282 }
283
284 /* nand_init() - initialize data to make nand usable by SPL */
285 void nand_init(void)
286 {
287         static struct nand_buffers ecc_buf;
288
289         /*
290          * Init board specific nand support
291          */
292         mtd.priv = &nand_chip;
293         mtd.erasesize = CONFIG_SYS_NAND_BLOCK_SIZE;
294         mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
295         mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
296
297         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
298                 (void  __iomem *)CONFIG_SYS_NAND_BASE;
299         nand_chip.oob_poi = ecc_buf.databuf;
300         nand_chip.buffers = &ecc_buf;
301
302         board_nand_init(&nand_chip);
303
304 #ifdef CONFIG_SPL_NAND_SOFTECC
305         if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
306                 nand_chip.ecc.calculate = nand_calculate_ecc;
307                 nand_chip.ecc.correct = nand_correct_data;
308         }
309 #endif
310
311         if (nand_chip.select_chip)
312                 nand_chip.select_chip(&mtd, 0);
313 }
314
315 /* Unselect after operation */
316 void nand_deselect(void)
317 {
318         if (nand_chip.select_chip)
319                 nand_chip.select_chip(&mtd, -1);
320 }